CHAPTER EIGHT
SHIFT REGISTERS
Basic shift register functions
• Shift registers (SR) consist of arrangements of FFs.
• Digital System : Important in application involving :
– a) Data storage
– b) Data transfer/movement
a ) The flip-flop as a storage element
b) Basic data movement in shift registers.
(Four bits are used for illustration. The bits move in the direction of the arrows.)
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Serial In/Serial Out (SISO)
• Accepts data serially, one bit at a time on a single line
• Output produced in serial form too
Figure 9.7 : Logic symbol for an 8-bit serial in/serial out shift register
Example 1
Figure .Four bits (1010) being entered serially into the register.
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Example 2
Serial In/Parallel Out (SIPO)
• Data bits are entered serially
• Output is parallel
– All bits are available simultaneously
Example SIPO :
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Parallel In/Serial Out (PISO)
• Inputs entered simultaneously into respective stages on parallel lines
• Outputs are one bit at a time
• SHIFT/LOAD
– = 0 ➔ Loads the input values
– =1 ➔ shifts them out at clock pulse
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Parallel In/Parallel Out (PIPO)
• Input and output done in parallel.
• Enter all inputs - Bits appear on the parallel outputs
Shift register counters
• A shift register with serial output connected back to the serial input to produce special
sequences.
• 2 most common types
– Johnson counter
– Ring counter
The Johnson Counter
• In the Johnson counter the last complemented output is fed back in as an input to the first
FF
• Examples shown with D FF, but can be implemented with other types of FF as well.
• Number of unique states are 2 times the number of bits (FF)
– 4 bits ➔ 4*2 = 8 states
– 5 bits ➔ 5*2 = 10 states
• Johnson counter will produce a modulus of 2n; (n = number of stages)
**modulus 10 a.k.a. mod 10
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4-bit Johnson Counter
The Ring Counter
• The ring counter uses 1 FF for each state in its sequence
• For a 10-bit ring counter, there is a unique output for each decimal digit
• Initially Q0 = 1 ➔ represents a zero
• The ‘1’ is shifted round the ring, so next Q 1 = 1 (represents a one)
• This goes on till Q9 = 1.
• Then the output Q9 is input back into the first FF
• **The ‘1’ is always retained and goes ‘round the ring’ at each clock pulse
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Shift register applications
• Time delay
• Serial-to-parallel converter
• Universal Asynchronous Receiver Transmitter (UART
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