Modern Digital Electronics Table 8.1 Shift Registers Available in 54/74 TTLand CMOS Families IG No. Description 7491, 74910 &.bit serial-in, serial-out 7494 4 bit parallel-in, serial-out 7495 4-bit serial/parallel-in, paralle|-out (right-shift, left-shift) 7496 ‘S-bit parallel-in/parallel-out, serial-in/serial-out 7499 4-bit bi-directional (universal) Ta164 8-bit serial-in, parallel-out 74165 8-bit serial/parallel-in, serial-out 7416 8.bit serial/parallel-in, serial-out 74178, 74179 4-bit bidirectional (universal) 74194 A bit bi-directional (universal) 74195 4-bit serial/parallel-in, paralic out 74198 bit bi-directional (universal) 74199 8-bit serial/parallel-in, parallel-out 74295 A 4-bit TRE-STATE serial/parallel-in, paratlel-out bi-directional 714395 4-bit TRISTATE cascadable serial/parallel-in, serialiparallel-out 8.2.1 Shift Register A S-bit shift register using five master-slave S-R (or J-K) FLIP-FLOBs is shown in Fig, 8.2. This circuit can be used in any of the four modes. The operation of this circuit is explained by assuming the 5-bit data 10110. For any other 5-bit data, the operation will be similar to the one explained, Serial Input ‘The data word in the serial form (Fig. 8.1) is applied at the serial input after clearing the FLIP-FLOPS using the clear line. The preset enable is to be held at 0 so that Pr for every FLIP-FLOP is 1. The input and Parallel inputs Preset enable Serial input Clear Clock Parallel outputs bese) = t Te ¢ Ry O, Fig. 8.2 A S-bit Shift Register (7496) output waveforms are illustrated in Fig. 8.3.Sequential Logie Design 1 Clock 0 Data input 9 Qs a The process of entering the digital word starts with the data input corresponding to the least-significant bit (0) at the serial input and first clock pulse. At the falling edge (7,) of the first clock pulse the output of FF4 (Q,) will be 0 and the outputs of all other FLI®-FLOPs are 0 since their inputs are 0. Next, the input corresponding to next bit is applied and, at the falling edge (7,) of the second clock pulse, the FLIP-FLOP outputs will be Q,=1 2,=2,= =o Similarly, the input corresponding to each bit is applied till the MSB and the bits go on shifting from left to right at the falling edge of each clock pulse as illustrated in Fig. 8.3. At the end of fifth clock pulse, the outputs of FLIP-FLOPS are which is the same as the number to be stored, The number of clock pulses required for entering the data, is the same as the number of bits, The process of entering the data is also referred to as writing into the register.316 Modern Digital Electronics ‘The data stored can be retrieved (also referred to as reading) in two ways: serial-out and parallel-out. The data in the serial form is obtained at Q, when clock pulses are applied. The number of clock pulses required will be same as the number of bits (five in this case). An the parallel form, the data is available at 2, O, Q, 2, Q, and clock is not required for reading, In the case of serial output, after the nth clock pulse, for an n-bit word, each FLIP-FLOP output is 0, This means that once the data is retrieved the register is empty. On the other hand, in the case of parallel output, the contents of the register can be read any number of times until new data is stored in the register. The clock rate may be different for the input data and the output data in case of a serial-in, serial-out shift register. Hence, this method can be used for changing the spacing in time of a binary code which is referred to as buffering. Parallel Input Data can be entered in the parallel form making use of the preset inputs. After clearing the FLIP-FLOPS, if the data lines are connected to the parallel inputs (D,, Dy, Dy D,, and D,) and a 1 is applied at the preset input, the data are written into the register. This is referred to as asynchronous ioading. As explained above, the stored word may be read in the serial form at @, by applying five clock pulses or in the parallel form at Q outputs The data can also be entered in parallel form by using D-type FLIP-FLOPS connected as shown in Fig. 7.24. In this, the data is loaded when a clock pulse is applied and hence, itis referred to as synchronous loading. Bi-directional Register ‘There are applications in which shifting data to the right and/or to the left is required, For example, a binary number can be divided by two by shitting it one stage to the right. In this process the least-significant bit is lost (unless additional circuitry is used to preserve it) causing an error of 0.5 if the number is odd, Similarly, a number stored in a shifl register can be multiplied by two by shifting it one stage to the left, provided a | is not shifted out of the most-significant stage. A 4-bit bi-directional shift register is shown in Fig. 8.4. When the mode control M = 1, all the A AND gates are enabled and the data at D, is shifted to the right when clock pulses are applied, On the other hand, when M = 0, the A gates are inhibited and B gates are enabled allowing the data at D, to be shifted to the left. M should be changed only when CK =, otherwise the data stored in the register may be altered. 8.3. APPLICATIONS OF SHIFT REGISTERS The primary uses of shift registers are temporary data storage and bit manipulations. Some of the common applications of shift registers are discussed below: 83.1 Delay Line A SISO shift register may be used to inéroduce time delay A¢ in digital signals given by 1 Ar=Nx — 8.1) f where Nis the number of stages and fis the clock frequency.Sequential Logic Design _ 317 Mode em FT TO] sninen oxi input (D;) 0 Wand shin o— right serial input (Dg) % FFO cr. ck Clear 84 44-bit Bi-directional Shift Register Thus, an input pulse train appears at the output delayed by At. The amount of delay can be controlled by the clock frequency or the number of FLIP-FLOPs in the shift register. 8.3.2 Serial-to-Parallel Converter Data in the serial form can be converted into parallel form by using a SIPO shift register. 8.3.3 Parallel-to-Serial Converter Data in the parallel form can be converted into serial form by using the PISO shift register. 8.3.4 Ring Counter Ifthe serial output Q, of the shift register of Fig. 8.2 is connected back to the serial input, then an injected pulse will keep circulating. This cireuit is referred to as a ring counter. The pulse is injected by entering 00001 in the parallel form after clearing the FLTP-FLOPs. When the clock pulses are applied, this 1 circulates around the circuit. The waveforms at the Q outputs are shown in Fig. 8.5. The outputs are sequential non-overlapping pulses which are useful for control-state counters, for stepper motor (which rotates in steps) which require sequential pulses to rotate it from one position to the next, etc. This circuit can also be used for counting the number of pulses, The number of pulses counted is read by noting which FLIP-FLOP is in | state, No decoding circuitry is required. Since there is one pulse at the output for cach of the N clock pulses, this circuit is referred to as a divide-by-N counter or an N : J scalar.Clock Qs a a a Modern Digital Electronics : 12 3 4 5 6 7 8 9 WH LB © JUVUUUU UU UU 1 Popo 4 Poy op d I rot ft a | 1 , | 'ori 1 o 1, — T 1 polio roid pot od hood iti toi 0 —— 1—1—t \ boro 1 hoy ot bo io 0 i—t i—+ \ 1 + i 1 5 i 1 1 0 Fig. 8.5 Output Waveforms of Ring Counter 8.3.5 Twisted-Ring Counter In the shift register of Fig. 8.2, if O, is connected to the serial input, the resulting circuit is referred to as a pwisted-ring, Johnson, ot moebius counter. If the clock pulses are applied after clearing the FLIP-FLOPS, square waveform is obtained at the Q outputs as shown in Fig. 8.6. % @ om SPLAT Output Waveforms of Twisted-Ring CounterSequential Logic Design | 319 Similar to ring-counter sequence, the moebius sequence is also useful for control-state counters, It is also useful for the generation of multiphase clock. The moebius counter is adivide-by-2 counter. For decoding the count, two- input AND gates are required. The decoder circuit for a five-stage counter is shown in Fig. 8.7. [ao a o—f J} 1 }—+ 6 % Q o— &% e—_f ) ‘ 2% e— % o— o— & =— a e—] % o—f Q of Y\e—] Q@ o—f %® e— 83.6 Sequence Generator A cireuit which generates a prescribed sequence of bits, in synchronism with a clock, is referred to as a sequence generator. Such generators can be used as 1. Counters, 2. Random bit generators, 3. Prescribed period and sequence generators, and 4. Code generators. “The basic structure ofa sequence generator is shown in Fig. 8.8. y Next State Deeoder Ons Qua 1 2 “| ift Register [p-——— Clock. Serial Suit Rede ‘put Fig. 88 Basie Structure of a Sequence Generator320 Moder ‘The output Y of the next state decoder is counter (Y= Q,) ora twisted-ring counter (¥= rn Digital Electronics function of Q,., Q,., «++ Q, Qy This system is similar to-a ring J,) which are special cases of sequence generators, The design of the decoder will be clear from Example 8.1 Example 8.1 Design a sequence generator to generate the sequence ... 1101011. Solution The minimum number of FLIP-FLOPS, N, required to generate a sequence of length S is given by: SP (82) In this ease S'= 7, therefore, the minimum value of NV, which may generate this sequence is 3. However, itis not gvaranteed (0 lead to a solution, If the given sequence leads to seven distinet states, then only three FLIP-FLOPS are sufficient otherwise we have to increase the number of FLIP-FLOPs, We write the states of the circuit as given in Table &.2. The prescribed sequence is listed under Q, and the sequence listed under @, and are the same sequence delayed by one and two clock pulses respectively, From the table we observe that all the states are not distinct, which means N’= 3 is not sufficient. Next we assume N= 4 and prepare Table 8.3 in a similar manner as Table 8.2. The last column gives the required serial input for getting the desired change of state when a clock pulse is applied. This is obtained by assuming D-type FLIP-FLOPs and looking at the Q, output. For example, at the falling edge of the fist clock pulse, Q, = 1. The second clock pulse must result in Q, = 1 which requires its D input to be 1. Inthe saine mainner, all the entries in column Yate determined. The K-map of Table 8.3 is given in Fig, 89 and the simplified expression is given by Y-G,+9,+ 8, (83) Table 8.2 State Table of Sequence Generaror (N= 3) FLIP-FLOP outputs Number of clock pulses e , 2, 2 1 —— =a! a ee ‘ fe 5 6 iss SS ble 8.3 Trueh Table of Sequence Generator (N = 4) Number of FLIP-FLOP outputs lock pulses a @ 2, @ 1 1 1 1 a 1 2 1 1 1 1 0 3 0 1 L 1 1 (Continued)321 Sequential Logic Design Table8.3 (Continued Number of FLIP-FLOP outputs Serial input clock pulses 0, 0, y 0 T o 1 0 1 1 0 1 0 1 T 0 i 1 1 x 0 1 o 1 asobor 1 1 0 1 o 1 1 1 1 1 1 0 1 1 o decoder circuit given by Eq. (83). ‘The sequence generator circuit ean be designed using a 4-stage shift register using D-type FLIP-FLOPS andthe 8.4 RIPPLEOR ASYNCHRONOUS COUNTERS A circuit used for counting the pulses is known as a counter. In Sec. 8.3, two types of counters have been discussed, The number of states in an N-stage ring counter is N, whereas it is 2N in the case of moebius counter, These counters are referred to as modulo N (or divide-by-N) and modulo 2M (or divide-by-2) counters respectively, where modulo indicates the number of states in the counter. When the pulses to be counted are applied to a counter, it goes from state to state and the output of the FLEP-FLOPs in the counter is decoded to read the count. The circuit comes back to its starting state after counting pulses in the case of modulo NV counter, ANE DON oo ort 0 |||} x x |] ox |x o1 Wy} x 1 i | x o uf] x a) wll} x | x 1 1 Fig. 89 Q K-Map of Table 83322 Modern Digital Electronics ‘The ring counter and the twisted-ring counter do not make efficient use of FLIP-FLOP, AFLIP-FLOP has two states, therefore a group of V FLIP-FLOPs will have 2" states, This means it is possible to make a modulo 2" counter using N FLEP-FLOPs. Basically there are two types of such counters: 1. Asynchronous counter (ripple counter), and 2, Synchronous counter, In the case of an asynchronous counter, all the FLIP-FLOPs are not clocked simultaneously, whereas in a synchronous counter all the FLIP-FLOPs are clocked sirmultancously. The ring- and the twisted-ring counters are examples of synchronous counters. Consider the count sequence shown in Table 8.4. The number of states in this sequence is 8 which requires 3 FLIP-FLOPs (2'= 8) and Q,, Q,, and Q, are the outputs of these FLIP-FLOPs. Assume master-slave FLIP-FLOPs. Table 8.4 Counting Sequence of a 3-bit Binary Counter Counter state Se 2. Q 2 ° 0 0 0 a 1 0 0 1 : 2 > 3 0 I 1 4 rv) 2 5 1 0 1 6 1 1? o2 1 I I 2 ‘The output Q, of the least-significant FLTP-FLOP, changes for every clock pulse. This can be achieved by using T-type FLIP-FLOP with 7,~ 1. The output Q, makes a transition (from O to | or | to 0) whenever @, changes from I to 0. Therefore, if Q, is connected to the clock input of next T-type FLIP-FLOP, FF] with 7, = 1, Q, will change whenever Q, goes from 1 to 0 (falling edge of clock pulse). Similarly, Q, makes ‘transition whenever Q, goes from 1 to 0 and this can be achieved by connecting Q, to the clock input of the most-significant FLIP-FLOP, FE2 (and 7,= 1), The resulting circuit is shown in Fig. 8.10, The waveforms of the outputs of the FLIP-FLOPs are shown in Fig. 8.11. Preset Iogie | o 3 4 lem a, Pulses10 gh FO be counted Clear o z gz logie 1 Fig. 810 43-bit Binary CounterSequential Logic Design 323 1 2 3 4 5s 6 7 & 8 10 Clock! | L| pulses 1 cc 0 1 a ° 1 & 0 {___ Time Fig. 8.11 Output Waveforms of Counter of Fig. 8.10 A decoder circuit for decoding the count is shown in Fig. 8.12. In this, the output corresponding to the number counted goes low (active-low), Be % Fig. 8.12 A Decoder Circuit for @ 3-bit Binary CounterModern Digital Electronics Atthe decoder outputs, false pulses of a short duration, known as spikes, accur as counter FLIP-FLOPS change state. This is because of the propagation delay of the FLIP-FLOPs due to which either all the FLIP-FLOPs do not change state at exactly the same time or only one FLIP-FLOP changes state for any clock pulse, The problems of spikes at the decoder outputs is eliminated by using a strobe pulse input. With this, the decoding will occur only when all the FLIP-FLOPs have come to steady state. ‘The frequency, f; of clock pulses for reliable operation of the counter is given by 1 f where NV = number of FLIP-FLOPS propagation delay of one FLIP-FLOP trobe pulse width. SN G)+tTE (8.4) Example 8.2 Ina4-stage ripple counter, the propagation delay of a FLT P-FLOP is 50 ns. Ifthe pulse width of the strobe is 30 ns, find the maximum frequency at which the counter operates reliably. Solution ‘The maximum frequency is ee 4x 50430 4.35 MHz 8.4.1 UP/DOWN Counters The counter of Fig. 8.10 counts in the UP direction, ic, the decimal equivalent of the counter output increases with successive clock pulses. It is also possible to make a counter in which the decimal equivalent of the counter output decreases with the application of successive clock pulses, ie. the counting proceeds in the DOWN direction (Prob. 8.5). The former is referred to as an UP counter and the laiter as a DOWN counter. An UP/DOWN counter can also be designed which can count in any direction depending upon the direction control input (Prob. 8.6). 8.4.2 Modulus of the Counter The counter discussed above is referred to as a ripple counter, since the pulses applied ripple from stage to stage. Itis a modulo n counter where n = 2%. If it is desired to have a modulo m counter, the number of PLIP-FLOPs required is determined using Eq, (8.5) as the minimum value of which satisfies the equation ms2 (8.5) For example, the value of Nis 4 for any value of m from 9:to 16. If m= 16, then the circuit can be designed as discussed above but ifit is less than 16, say 10, then out of 16 states only 10 states are used and the remaining six states are unused, The counter is required to be reset (i.e. the normal counting is to be terminated) at theSequential Logic Design 325 end of the tenth clock pulse, This can be achieved by generating a logic 0 signal immediately after the tenth pulse and applying it to the clear input of all the FLIP-FLOPs. For a modulo 10 counter (also referred to as a decade counter) the circuit for resetting the counter after the tenth pulse is shown in Fig. 8.13. ‘To clear input - “xd A Circuit to be Used to Obtain a Decade Counter from Modulo-16 Counter At the end of the tenth pulse, Q, 1, therefore, the output of the NAND gate G will be 0, making the output of the latch 0. This will reset the counter. The latch is used in order to keep the clear line at 0 till both the FLIP-FLOPs are cleared. ‘Acounter in which the starting state is not 0 can be designed by making use of the preset inputs of the FLIP-FLOPs, similarto Fig. 8.2. This is referred to.as /oading the counter asynchronously (not synchronous with the clock pulse), This is referred to as a presettable counter, 8.4.3 54/74 Series Asynchronous Counter ICs The design of asynchronous counters using PLIP-PLOPs has been discussed above. Some asynchronous counters are available in MSI and are given in Table 8.5 along with some of their features. Depending upon these features, these ICs are divided into three groups A, B, and C. The group to which a particular IC belongs is also indicated in the table. All these ICs consist of four master-slave positive edge-triggered FLIP-FLOPS. The load, set, and reset (clear) operations are asynchronous, i.e. independent of the clock pulse. Table $5 Available Asynchronous Counter ICs in TTL and CMOS Families IC No. Description Features Group 7490, 74290 BCD counter Set, reset A 7492 Divide-by-12 counter Reset B 7493, 74293, 4-bit binary counter Reset B 14176, 74196 Presettable BCD counter Reset, load c 74177, 74197 Presettable 4-bit binary counter Reset, load ie 74390, Dual decade counters Reset B 74393 Dual 4-bit binary counters Reset B 74490, Dual BCD counters Set, reset A326 Modern Digital Electronics Group A Asynchronous Counter ICs Figure 8.14 shows the basic internal structure of 7490. It consists of four FLI P-FLOPs internally connected to provide a mod-2 counter and a mod-5 counter. The mod-2 and mod-5 counters can be used independently or in combination. FLIP-FLOP FFA operates as a mod-2 counter whereas the combination of FLIP— FLOPs FFB, FFC, and FFD form.a mod-5 counter. There are two reset inputs R, and R, both of which are to be connected to logic 1 level for clearing all the FLIP-FLOPS. The two set inputs 5, and S, when connected to logic | level, are used for setting the counter to 1001 Outputs ia Input A A FEC FFD | Mod-$ Counter Lt Jd ii Inpue RRS 8; ‘Reset inputs Set inputs Fig.3.14 Basic Internal Structure of 7490 Ripple Counter IC IC 74490 is a dual BCD counter consisting of two independent BCD counters. Each section consists of four FLTP-FLOPs, all connected internally to form a decade counter. For cach scetion there isa reset (R) and a set (S) input which are active-high Example 8.3 Ina 7490 if Q, output is connected to B input and the pulses are appli waveforms at @ outputs. at A input, find the count sequence and the Solution When Q, output is connected to B input, we have the mod-2 counter followed by the mod- counter. The count sequence obtained is given in Table 8.6. rable Counter state rere o, a 2, a 0 0 0 0 7 1 oO 0 0 ; (ContneddSequential Logic Design _ 327 (Continued) 5 FLIP-FLOP outputs Counter state ee hath 2p Lz 2, 2, z 0 0 1 ° 3 0 0 1 1 4 0 1 ° 6 5 0 1 0 1 6 0 1 1 ° 7 0 1 1 1 8 1 0 0 0 9 1 0 o 1 10 oO 0 o 0 Itmay be noted that when @, changes from 0 to | , the state of the mod-5 counter does not change, whereas when Q, changes from 1 to 0, the mod- counter goes to the next state ‘The waveforms at Q outputs are illustrated in Fig. 8.15. 1 2 3 4 $ 6 7 8 9 0 Wt st, TUL UL L | a! f Lf Qe ec >! Fig 8.15 Waveforms at Q Outputs for Ex. 83 Example 8.4 Ina 7490, if, ouput is connected to A input and the pulses are applied at B input, find the count sequence and the waveform of output @, Compare its count sequence with that of Table 8 6. Solution When Q, output is connected to input and the pulses are applied at & input, we have the mod-5 counter followed by the mod-2 counter. The count sequence obtained is given in Table 8.7, Here the states of the mod-S counter change in a normal binary sequence and Q, changes whenever Q, goes from 1 to 0,328 Modern Digital Electronics Table 8.7 ‘Counter State FLIP-FLOP outputs 2, Q. 2, Q. a 0 a 0 0 1 0 0 1 0 z o 1 9 0 3 ° 1 1 0 4 1 0 ° 0 5 0 0 0 1 6 ° 0 1 1 7 0 I 0 1 8 0 1 1 1 9 1 0 9 1 10 o 0 0 a The waveforms of 0, output is illustrated in Fig. 8. 16 whic a square wave. 112364 5678 9 OU 2 4 Is 6 Fig. 8.16 Waveform of Ouput Q, ‘The count sequence of this counter is different from that of Table 86 although both are divide-by-10 counters. The waveform of (output is square wave. Hence this circuit can be used for the generation of square waves. Example 8.5 Design a divide-by-6 counter using 7490. Solution Connect the counter as divide-by-10 for normal binary sequence (Ex. 8.3). Gutputs Q, and Q,, are connected to the reset inputs, Therefore as soon as Q, and Q. both become 1, the counter is reset to 0000. Figure 8.17 shows the divide-by-6 ripple counter. Output oe tule % Sa CO 1490 Bee As) Ske Fig.8.17 4 Divide-by-6 Ripple Counter Using 7490Sequential Logic Design Group B Asynchronous Counter ICs ‘The basic internal structure of 7492, 7493, and 74293 asynchronous counter ICs is shown in Fig. 8.18. ‘The operation of these ICs is identical to the operation of IC 7490 except that the set inputs are not present and mod-6 counter does not count in straight binary sequence. The sequence of mod-6 counter is given in Table 8.8. These ICs are not used as counters but are used for frequency division. Outputs ae Q Oss % 29 Input A o- o> FFB FFC FFD Mod-<6 in 7492 He oe Mod-8 in 7493, 74293 Input Bk Re Reset inputs Basie Internal Structure of 7492, 7493 ared 74293 Counter ICs Table 88 Count Sequence of Mod-6 Counter 2, g. Q, a a 0 0 0 1 0 1 0 L 0 0 1 0 1 L 1 0 74390 IC is a dual BCD counter consisting of two independent BCD counters similar to 7490, There is one reset (R) input for each section, 74393 is a dual 4-bit binary counter with one reset () input foreach section which is active-high Example 8.6 Ifoutput Q, of a divide-by-12 ripple counter 7492 is connected to the B input ancl the pulses are applied at the 4 input, find the count sequence. Solution The count sequence is given in Table 8,9. It may be noted from it that simultaneous divisions of 2, 6, and 12 are performed at the Q,. Q,..and Q, outputs, respectively.Modern Digital Electronics Table 8.9 iS ies HH coco--soo58 coe eooccoseso Here ree ens Group C Asynchronous Counter ICs The basic internal structure of group C counter ICs is shown in Fig. 8.19. 74176 and 74196 are both BCD counters with a difference in only maximum clock frequency specification, Similarly, 74177 and 74197 are both 4-bit binary counters with the same difference, ‘Outputs: Qn Op Qc Op (MSR) Input A 6. FEB FRC FFD FFA Mod-S in 74176 & 74196 Mod-8 in 74177 & 74197 Load o—O) Clear Input Py Py Pe Py (MSB) Preset inputs 8.19 Basic Internal Structure of Group C Asynchronous Counter ICs These counters are presettable versions of 7490 and 7493 counters respectively. The counter is cleared by connecting logic 0 to clear input (active-low), Setting load input to logic 0 (while clear is at logic 1) stops the count and loads any binary number present at the preset inputs into the counter, For normal UP counting operation, both the load and clear inputs should be connected to logic 1. The presettable 4-bit binary counters can be used as variable mod-n counter in which the counter modulus is equal to 15 — P, where P is the binary number connected at the preset inputs. In other words, for designingSequential Logic Design a mod-n counter, the value of P is 15 ~n, When the counter output reaches the count 1111, the counter must be loaded again with P. This is made possible by using a 4-input NAND gate between the Q outputs of the counter and the load input. Example 8.7 Design a divide-by-12 counter using 74177. Solution The circuit of a divide-by-12 counter is shown in Fig. 8.20. The counter is loaded with P= 1111~1100=0011 as soon as the output becomes 11 11 Outputs —<— QW Qy- Qe Oy Input A Wee 4% Fig.820 4 Divide-by-12 Courter Using 74177 Cascading of Ripple Counter ICs Ripple counters of any cycle length can be obtained by cascading the ICs discussed above. The desired cycle length is decoded and used to reset all the counters to 0. The strobe should be used to climinate false data, ‘The cascading arrangement for all the asynchronous counter ICs is same where Q,, of preceding stage goes ta the clack input terminal of the succeeding stage. The load and clear inputs of all ICs are to be connected together. Example 8.8 Design a 2-decade BCD counter using the IC 74390, Solution The 74390 IC is a dual BCD counter, therefore only one IC is required to design a 2-decade BCD counter, The 2-decade counter is shown in Fig, 8.21.332 Modern Digital Electronics MSD. LsD Qn cr Om Aa Poo Sco Co Ono + Op Oc A % | QM % Ap %W ‘ Input B Input B 7 . Section 1 i Section 2 Input Al | input | " x rn B Input A Logic 0 8.21 A 2-Decade BCD Counter Using 74390.1C 8.5 SYNCHRONOUS COUNTERS The ripple counters have the advantage of simplicity (only FLIP-FLOPs are required) but their speed is low because of ripple action. The maximum time is required when the output changes from 111 ... 1 to 000... 0 and this limits the frequency of operation of ripple counters. The speed of operation improves significantly if all the FLIP-FLOPS are clocked simultaneously. The resulting circuit is known as a synchronous counter, Synchronous counters can be designed for any count sequence (need not be straight binary). These counters can be designed following a systematic approach. Before we discuss the formal method of design for such counters, we shall consider an intuitive method. Consider the count sequence of Table 8.4. The output Q, of the least-significant >LTP-PLOP changes for every clock pulse. This can be achieved by using a T-type FLIP-FLOP with 7, = 1. The output Q, changes whenever Q, changes from I to 0. Therefore, if Q, is connected to T input (F,) of the next FLIP- FLOP, Q, will change from 1 to 0 (or 0 to 1) when Q, = 1 (7, = 1) and will remain unaffected when Q,= T, = 0. Similarly, we observe from Table 8.4 that Q, changes whenever Q, and Q, are both 1, This can be achieved by making the F-input (T,) of the most-significant FLIP-FLOP equal to Q,- Q,. The circuit thus obiained is shown in Fig. 8.22. In addition to FFs, synchronous counters require some gates also. J-K FLIP-FLOPS are the most commonly used FLIP-FLOPs for the design of synchronous counters. In this, each FLIP-FLOP has two control inputs (Jand K) and circuit is required to be designed for each control input. Many programmable logic devices (PLDs) used for the design of digital systems utilise D FLIP-FLOPS for their memory elements, therefore, counter design using D FLIP-FLOPS will be useful for programming inside a PLD. It has only one control input which makes its design simpler than the design using J-K FLIP-FLOPS.Sequential Logic Design _ 333 Output 25 a > Preset Logie |e ™% Oy Tor 4h oy FEO ee FF ob rr Clear Clock: pulses 8.22 A S-bit Syrchronous Counter 8.5.1 Synchronous Counter Design ‘Synchronous counters for any given count sequence and modulus can be designed in the following way: 1. Find the number of FLIP-FLOPS required using Eq. (8.5). 2. Write the count sequence in the tabular form similar to Table 8.4. 3. Determine the FLIP-FLOP inputs which must be present for the desired next state from the present state using the excitation table of the FLIP-FLOPs (Table 7.6). 4, Prepare K-map for each FLIP-FLOP input in terms of FLIP-FLOP outputs as the input variables, Simplify the K-maps and obiain the minimized expressions. 5. Connect the circuit using FLIP-FLOPS and other gates corresponding to the minimized expressions. The above design steps can be clearly understood from the following examples. Example 8.9 Design a 3-bit synchronous counter using J-K FLIP-FLOPS, Solution ‘The number of FLIP-FLOPS required is 3, Let the FLTP-FLOPs be FFO, FFI, and FF2 and their inputs and outputs are given below: FLIP-FLOP Inputs, Output FFO Tok, @, FFI 9g, EF2 2,334 Modern Digital Electronics FLIP-FLOP inputs Counter state FO FFL FF2 2 2 a Ky a = i = oo o fe x 0 x 0 x 0 0 1 x 1 1 x 0 x 0 1 0 1 x * 0 0 Pe ° 1 1 x 1 x 1 1 x 1 0 0 1 x o x x 0 1 ° 1 x 1 1 x x 0 1 1 0 1 x x 0 x 0 1 1 1 x 1 x 1 x 1 0 0 0 ‘The count sequence and the required inputs of FLIP-FLOP are given in Table 8.10. The inputs to the FLIP— FLOPS are determined in the following manner: ooo ot a0 oo neo lea ale o| x)» | «| | rt] fx |x | x ‘fafa e] Ko=t 0) Qe L209 or 10 @ S209 oto ol of} x] x] o o| x | ojo] x vifa [efx] a v|fe | a |e] T Re ©) ©). a eo 0 QL oo oo of o}o |x] x o| x | «| o]o 1] o |[a | =]} x 1] x [fe fa]] o a= Qo ® Fig. 8.23 KeMaps of Ex. 8.9Sequential Logic Design ‘Consider one column of the counter stale ata time and start from the first Tow, for example, consider O,, Before the first pulse is applied, Q, = 0 and it is required to be I at the end of the first clock pulse. Therefore, to achieve this condition, the values of J, and X, are 1 and x respectively (from the excitation Table 7.6). These are entered in the table in the row corresponding to 0 pulse. When the second clock pulse is applied O, is to change from | to 0, therefore, the required inputs are T= K=1 Inva similar manner inputs of each PLEP-PLOP are determined, Now, we prepare the K-maps (Fig. 8.23) with Q,, Q,,and Q, as input variables and FLIP-FLOP inputs as output variables, We then minimize the K-maps and -the resulting minimized expressions are: Aol Kyat Fa K,=2, 479,0, K.=2,0, ‘The resulting counter eireuit is same as the circuit of Fig. 8.22. Example 8.10 Design a 3-bit binary UP/DOWN counter with a direction control M. Use J-K FLIP-PLOPs. Solution ‘The count sequence is given in Table 8.11, For M™=0, it acts ay an UP counter and for M= 1 as a DOWN counter. The number of FLIP-FLOPS required is 3. The inputs of the FLIP-PLOPs are determined in a manner similar to the one emplayed in Ex. 8.9. fab Direction control FLIP-FLOP inputs M 2, 2 % R 45 & 4 «, 0 0 0 1 x 0 x ox 0 0 1 x 1 I x o x 0 ° 9 1 x x a ox 0 0 1 x 1 x 1 1 x 0 I 0 1 x 0 x x 0 0 1 1 x 1 1 x x 0 0 1 0 1 x x o x 0 0 I 1 x 1 x t x 1 1 o 0 1 x 1 x 1 x 1 1 1 x 1 x 0 x 0 1 1 0 1 x x 1 x 0 1 I 1 x 1 ° x x 0 1 1 0 1 x 1 x x 1 1 o 1 x 1 x o 0 x I 0 0 1 x x 1 ox 1 ° 4 x 1 0 x ox 0 0Modern Digital Electronics From Table 8.11, we obtain =K=1 The K-maps for J, K,, Jy and K, are shown in Fig, 8.24, From the K-mnaps, the minimized expressions are obtained as J,=K,=O,M + OM 4, = K,= M0,0,+ MG, 0, ‘The counter cireuit can be drawn using the above expressions Mes MO, ae 2,05 00 oo a a i u 10 10 Mes MQz eax Wo wo OG 0 a 10 wlo |x |lx]a wo} x]o ffi] x a || o |e | x) ® a}|x]|o]o} x n ffi] «|| «| o uff] aj} o} x wl ox |x| o wl] x |o]o| x a e K-Maps for Ex. 8.10 Example 8.11 Design a decade UP counter. Use J-K FLIP-FLOPS. Solution ‘There are ten states in a decade counter, which requires four =LP-FTOPS, The remaining six states are unused states, The count sequence and the FLIP-FLOP inputs are given in Table 8.12.Sequential Logic Design _ 337 Counter state FLIP-FLOP inputs 2 2 % % 4, KS, Kd, OK Ji, K, oo 0 © 1 x 0 x oO % 0 x o 0 oO 1 x to x 0 -% oOo x o o 1 0 1 x x 0 0 -~ o x oo 1 1 x 1 x 1 1 x 0 x o 1 0 1 x 0 x x 0 0 x o 1 0 4 se 1 1 eS 0 6 x oot a) 1 x x 0 -“ 0 0 x o 4 1 I x 1 x De 1 1 x 1 0 0 9 1 x 0 x 0 x «x 0 1 0 09 1 x 1 0 x @ « x i a Rai J, = 0,0. K =, 4,=0,0, K,= 0,0, 4, = 2,2» zo; ‘The counter circuit can be drawn using the above expressions. Example 8.12 Design a natural binary sequence mod-8 synchronous counter sing D FLIP-FLOPS. Solution The number of FLIP-FLOPS required is 3, Let the FLIP-FLOPS be FFO, FFI and FF2 with inputs D,, D, and D, respectively. Their outputs are Q,,.(,,.and Q, respective. The count sequence and the corresponding FLTP-FLOPs input required are given in Table 8.13. Using the excitation Table 7.6, the FLIP-FLOPS inputs are determined in the same way as determined for the J-K PLIP-FLOPs. Counter States and D FLIP-FLOPS Input Counter state FLIP-FLOP inputs 2, 9, D, dD, D, 0 0 iI 1 0 0 0 ° o 1 0 0 1 0 1 1 0 0 1 1 o 0 1 1 0 0 1 0 1 1 0 1 o 1 1 L 1 0 1 1 1 1 1 1 0 0 0 o 0 0Modern Digital Electronics ooo oii oor a to o}ij}alx fa oo] x |x |x| x or] x | x] | x ofafafx]a TE | | | | TE) 2 | 1 | | x wf] i} il x | x wl x | x | x | x to Ky oon 11110 008% 01 10 o}o}o|x|o | x | x |x | x See ESS |e alfx | x |x |» ulfx [x] x] & i llp le ele w| x |x | x] x al alleal le ah Ry aos Pty o_o oo” oo oo 10 K-Maps for Ex. & 11 ofo] x] x oo| x| x |x] o aS ee alfx| «| «fa wl] xe |e | |x || || ee ee wo] x} x | x | x " KiSequential Logic Design _ 339 ‘The K-maps for D,, D,, and D, are given in Fig. 8.26, 220 00. o> ou 16 [tliat] 1Jo}|alojo Fig. 8.26 K-Maps of Ex. 8.12 The minimised expressions for D,, D,, and D,, are: 2-2 P= 2,2,+9,9, Dy = Q,2,+ 2, 2,+ 8,2,2, 2,8, + B,)* 2,0,9, =2,@B)+ 20,0) -200,-0, ‘The complete circuit of the synchronous counter using positive edge triggered D FLIP-FLOPs is shown in Fig. 827. Dy a4] », af o, 2, Fra FFI Fe 0, 0, Q, Clock, Fig. 827 Synchronous Counter Circuit of Ex. 8.12Modern Digital Electronics 8.5.2 Lock Out In the counter specified by Table 8.12, logic states, 0,.0,0,0,= 1010, 1011, 1100, 1101, 1110, and 1111 are not used. If, by chance, the counter happens to find itself in any one of the unused states, its next state would not be known, It may just be possible that the counter might go from one unused state to another and never arrive ata used state. Of course, such a situation makes the counter useless for ils intended purpose. A counter whose unused states have this feature is said to suffer from lack out. To make sure that at the starting point the counter is in its initial state or it comes to its initial state within a few clock cycles (count error due to noise), external logic circuitry is to be provided. To ensure that lock out does not occur, we design the counter assuming the next state to be the initial state, from each of the unused states. Beyond this, the design procedure is the same as discussed earlier. 8.5.3 54/74 Series Synchronous Counter ICs The design of synchronous counters using PLTP-FLOPs has been discussed above. Counters for any count sequence and modulus can be designed using these methods. Some synchronous counters are available in MSI and are given in Table 8.14 along with some of their features. All theses ICs are positive-edge-triggered, i.e. the change of state, synchronous loading, and clearing take place on the positive going edge of the input clock pulse, Basically these ICs can be divided into four groups—A, B, C, and D. A brief description of each group is given below: Table 8.14 Available Synchronous Counter Cs in TTL and CMOS Families Description Features: Group ‘Decade UP counter ‘Synchronous preset and asynchronous clear A 4-bit binary UP counter —do— A ‘Decade UP counter ‘Synchronous preset and clear A 4-bil binary UP counter —do— A Decade UP/DOWN counter Synchronous preset and no clear B 4-bit binary UP/DOWN counter do. B Decade UP/DOWN counter Asynchronous preset and no clear 3 T4191 4-bit binary UP/DOWN counter: do, Cc 74192 Decade UP/DOWN counter Asynchronous preset and clear D 7AN93 4-bit binary UP/DOWN counter do- dD Group A Synchronous Counter ICs uputs The block diagram and the function table of these 4 Oy Sc AntMSB) RE ICs are given in Fig. 8.28. In these ICs there are two Et tt separate enable inputs, ENT and £NP. Setting either of cko—+ these inputs to logic 0 stops counting asynchronously, ENTe—| 74160, 74161, 74162, T4163 Ripple carry (RC) output is normally at logic @ and ENP —| goes to logic | whenever the counter reaches its highest LTE Teel T count (binary 9 for BCD counters and binary 15 for 4-bit P, ews] binary counters). Setting ENT to logic 0 also inhibits RC ry oe changing from logic 0 to logic 1. 8.28 Group A Synchronous Counter ICs => (a Block DiagramToad L ENP ENT or cK 0 ~ # x 1 Tr 1 0 1 1 x Stop count 1 x 0 1 x Stop count, disable RC x x x 0 . Reset to zero 1 1 1 1 t UP count + x for 74160 and 74161 J for 74162 and 74163 Fig. 8.28 (6) Function Table Example 8.13 Design a normal med-12 counter using 74161. Solution The circuit is designed for the nomnal UP counting (last row of Fig. 8.288), The Q, and Q, outputs through a NAND gate are connected to the Cr terminal which clears the counter as soon as the output is 1100. The states of the counter are from 0000 through 1011. The mod12 counter is shown in Fig. 8.29. 4 A; Pe ———P Pules o—p cK ENT 761 Logic tet | ENP Load cr Tht 7 Fy Ma Pe Po Logic 1 8.29 Figure for Ex, 8.13 Using the approach followed in Ex. 8.13, thecount can be terminated at any desired value and a counter with any modulus (less than 16 for binary and less than 10 for decade counter) can be obtained, Example 8.14 Design a divide-by-11 counter using 74163. Make use of the RC output and preset inputs. Solution For obtaining a divide-by-11 counter, the counters preset at binary 0101 (decimal 5). When the count reaches 1111, RC output goes to 1, which is used to load the daia present at the preset inputs into the counter. The circuit of the counter is shown in Fig, 8.30.Modern Digital Electronics Qs Cp Cr A RC Pulses &—} Lage tof] Ph, Pp Po Py Load Cr Fig. 830 Counter for Ex. 8.14 In general, for obtaining a divide-by-m counter, the preset input, P, is given by P=16—m ford-bit binary counter =10-—m fordecade counter Cascading of group A counters in fully synchronous mode is shown in Fig. 8.31, Lsp Qe 20p a QpOeOy HALO cr ¢ ter o a] | & & ENP ENP rq ENP § oe if] rer rcleb]ewr cz ecb] ewe resec|_ecamy} & ENT g cK fp L & «oe leery —_ Lod +} t + toad | + ENP Py Pag Po Py By Py Pe Pa Be Pa Fe Po Group B Synchronous Counter ICs The block diagram and the function table of these ICs are given in Fig. 8.32. The functions of ENT and ENP are same as in group A ICs except that these are active-low. Ripple carry (RO) output is normally held at logic 1 and goes to logic 0 (i) when the count reaches maximum during UP counting, and (ii) when the count reaches minimum during DOWN counting. Signal at U/D terminal decides the tion of counting, U/D = 1 for UP counting and L/D = 0 for DOWN counting. In this group of ICs, the clear terminal is not available. Therefore, if it is desired to terminate the count before it reaches the maximum value, a NAND gate is used to detect the count corresponding to the required number and its output is connected to the load input terminal, The preset inputs can be given corresponding, to the required starting state of the counter.Sequential Logie Design ) Seannes wn Comsexmer344 Modern Digital Electronics Ifthe counter is required to count up to the maximum/minimum value then the RC output is tobe connected to the load input, for loading the initial count at the next pulse after maximum/minimum count has been reached. The frequency of the output waveform at RC (f,,) is related to the input clock frequency (f,) as follows: Binary Counter 74169 Si = outputs Clock Fig. 838 Block Diagram of a Moore Model 8.6.2 Basic Concepts The general block diagram of a clocked sequential circuit is shown in Fig, 7.1, which also represents Mealy model. The block diagram of Moore model is shown in Fig. 8.38. Both the models use clock signalSequential Logic Design 349 input for the memory elements which are FLIP-FLOPs. All the FLIP-FLOPs in the cireuit are clocked simultaneously. The outputs and the next state of a clocked sequential circuit depend upon the external inputs and the present state of the circuit. Systematic procedure for the design of clocked sequential circuits is based on the concept of ‘state’ For these circuits, the sequence of inputs, present and next states, and output can be represented by a state table oF a state diagram. ‘The behaviour of a combinational circuit can be described in the form of Boolean expression(s}, truth table, or K-map. Similarly, the behaviour of a synchronous sequential circuit can be described in a number of ways. Since the operation of a synchronous sequential circuit is always in synchronism with the clock pulses, therefore, the oceurrence of a clock pulse is vital to deseribe its operation. Before occurrence of any given clock pulse, the following items are required to be known, 1. Present state, i¢., the output of FLIB-FLOP(s) in the circuit 2. Signal(s) present at the extemal input(s), known as the input(s). ‘The combination of present state and external input results in a transition to the next state (when clock is applied) and an output. Similar process is repeated, when the next clock pulse occurs, except that the present state is now what the next state was after the completion of the preceding clock pulse, This process can be represented by the sequence as shown in Fig. 8.39. Present State Next State, Clock pulse | Input Output ‘The above operation of a clocked sequential circuit can be described in the form of a diagram, known as state diagranr; a table, known as state rable; or in the form of a flow chart, Known as algorithmic state machine (ASM) chart. 8.6.3 State Diagram It isa directed graph, consisting of vertices (or nodes) and directed arcs between the nodes. Every state of the circuit is represented by a node in the graph. A node is represented by a circle with the name of the state written inside the circle, The directed ares represent the state transitions. With the circuit in any one state, at the occurrence of a clock pulse, there will be a state transition to the next state and there will be an output, both in accordance with the requirements of the circuit. This state transition is represented by a directed line emanating from the node corresponding to the present state and terminating on the node corresponding to the next state. The labels are put on the directed arcs specifying the inputs and outputs separated by a slash (/). Consider a portion of a state diagram shown in Fig. 8.40a, In this, when the circuit is in state A, an input 1 causes the circuit to make a transition to the neat state B and gives an output 0. 4 and B represent the present state and next state respectively, connected by an arc from 4 to B (labelled 1/0), For a circuit with single input, when the circuit is in any state, the input can be 0 or 1. For each possibility of the input, there will be a directed arc, Thus two ares emanate from each node, one each for a0 and fora 1 input. In general, for an n-input machine, 2" arcs will emanate from each node, This is illustrated in Fig. 8.404. In some sequential350 Modern Digital Electronics circuits, the outputs are taken from the outputs of the FLIP-FLOPS directly, i, the output logic circuit is not there, such as FLTP-FLOPs and counters. In such cases, the directed arcs will have only inputs written adjacent to the arcs. Fig. 840 Illustrations of Directed Graph In some cases a state may be a terminal state, i. the corresponding vertex in the state diagram may be a sink vertex or a source vertex. A vertex is a sink vertex if there are no outgoing arcs which emanate from it and terminate in other vertices. For example in Fig. 8.41a, on vertex D, whatever may be the input (0 or 1), the are emanating from it terminates on itself and there is no arc emanating from 2 that terminates in any other vertex. Therefore, vertex D is a sink vertex. It means no state is accessible from a sink state. Similarly, a vertex is Known as a source vertex if there are no arcs which emanate from other vertices terminating in it. For example, vertex 4 in Fig. 8.415, is a source vertex. oo @& Fig. 8.41 Example of (a) Sink Vertex (b) Source Vertex Example 8.16 Draw the state diagram of a.D type FLIP-PLOP shown in Fig. 8,42. . ID Solution D CKo—_> FF This ‘cinouit has one input (D), two states (Q= 0 and O = 1), and a positive edge-triggered elock (CX) terminal. The two slatcs O and I are represented by two nodes as shown in Fig, $.43. Let us assume the circuit to be in state 0 and B= 0, when a clock pulse occurs, At the end of the clock pulse, the circuit remains inthe Fig. 8:42 D-fype FLTP-FLOP same state. ‘This is indicated by a directed are emanating from the state ** "for Ex. 816Sequential Logie Design Tand terminating on the same state. IFD = 1, while the oioult's present state is 0, state transition takes place taking the circuit to another state 1 or ea when a clock pulse oceurs. Similarly, ifthe circuit isin state 1, for D= 0 (o) C1) a clock pulse applied will cause state to change to 0, whereas for D = 1 a it remains in the same state, All these operations are clearly indicatedin pig 43 State Dlagram of @D ree FN Ste iar Example 8.17 Draw the state diagram of aJ-K FLIP-FLOP. Solution AJ-R FLIP-PLOP has two inputs (J and K) and one clock input (CK). There are two states (= 0 and Q = 1). Tts state diagram is shown in Fig, 8.44. Fig 844 State Diagram of a J-K #LI2-FLOP Since, there are two inputs (J and A), therefore, there are 2? = 4 possible input conditions and consequently, four directed arcs emanate from each state, The two inputs are indicated in JK order, ic. the first input is represented by the first bit and the second input is represented by the second bit. 8.6.4 State Table A state table is a tabular form of describing the operation of'a synchronous cireuit. Each row of the state table corresponds to a state of the circuit and each column corresponds to a combination of external inputs. The entries of the table denote the state transitions (next states) and the outputs associated with these transitions ‘The number of rows in the state table will be equal to the number of states of the circuit, and the number of columns will be same as the number of combinations of the inputs (2 for | input, 4 for 2 inputs, and so on). ‘state table can be easily constructed from a state diagram. In fact, whatever information is available in a state diagram is also available in its state table and one can be obtained from the other, Example 8.18 Construct state table for the state diagram of Fig. 8.406, Solution There are three states in this circuit A, B, and C, therefore, its state table will contain three rows. There is one input (2) and one output (1) variable. There is one column for each value of X, ie... =O and X= |. Each entry of the table contains two pieces of information; next state and output separated by a comma, The first entry is for the next state and after itis output.Modern Digital Electronics Lets start making entries in the state table starting from the stale 4, When the circuit is in state A, the extemal input present is 0, in response to-a clock pulse the state does not change, ie. the next state is also.4 and the output is 0, This is weitten in the first row and first column as 4, 0. If the present input is 1 while the cireuit is in state A, a clock pulse will cause next state to be B and output = 0. The corresponding entry in the first row second colurnn will be B, 0. Similarly, take the state # and find out the next state and the resulting output when X= O-and when X= I and the cortesponding entries are made in the second row: under the appropriate columns. Same procedure will give entries for the third row corresponding to the state C, ‘The complete table is given in Table 8.15. Table 81S State Table for the State Diagram of Fig. 8.40b Present state Neat state, Output AS PS Kat Xe a 4,0 BO B Cl AO € 4,0. G1 8.6.5 State Assignment For designing a clocked sequential circuit, the requirements (or specifications) may be specified as a set of statements. State diagram is constructed from the set of statements and state table can be prepared from the state diagram. For constructing the state diagram, normally the states are not specified in the binary form ‘Therefore, we make use of some letter symbols such as 4, B, C, ... etc. for the states, The exact number of states is also usually not known, but using the set of statements, arbitrary number of states may be chosen to satisfy the given requirements of the circuit, The states chosen in this way may contain more than the minimum number of states required. The inclusion of redundant states will help in the proper representation of the circuit. For the design of any system, itis always desirable to design a minimal-cost system i.e. a system costing minimum money. There are two issues involved in the design of clocked sequential circuits, These are given below. * The number of states must be minimum possible so as to be able to design a system with the minimum number of FLIP-FLOPS. Since one FLIP-FLOP has two states, therefore, the number of FLIP- FLOPs required can be determined from the number of states in the circuit. The redundant states get climinated by state recuction method which will be discussed later. + Combinational cireuitsare requiredto generate the excitation functionsand the output, The combinational circuits required should also be designed for minimal cost. For this purpose, the states which have been labeled as 4, B, C, ... etc. have to be assigned binary values suitably. This process is known as the state-assignment. There may be a number of different possibilities for assigning binary values to the states. Each option will lead to different logic expressions for the FLIP-FLOP excitations and output, but will produce the required sequence of outputs for any given sequence of inputs. In a case in which it is required to have a specific ourput sequence for a given input sequence, the binary values of theSequential Logie Design individual states may be of no consequence. However, the requirements of states for circuits whose external outputs are taken directly from the FLIP-FLOPs with binary sequence fully specified need only the specified binary values assigned to the states and therefore, no alternatives are available for such circuits, Therefore, for circuits requiring the specified input-output relationship, the binary values of the states are of no consequence and the state assignment should be made which produces a minimal- cost combinational circuit. Rules for State Assignment In the design of a sequential circuit, the complexity of the combinational circuit obtained depends on the chosen state assignment. There is no general procedure for the state assignment which produces the most cost effective design of the resulting combinational circuit, however, trial and error attempts at making state assignments are not practically feasible. The following thumb rules will help in generating simple combinational circuits. Rule1 Adjacent codes should be assigned to the states having the same next state for: (a) each input combination {b) different input combinations, if the next state can also be assigned adjacent codes (©) some of the input combinations, not all Rule 2 Adjacent codes should be assigned to the next state (s) of every present state. Rule 3 Adjacent codes should be assigned to states that have the same outputs. Fora given state table, it may not be possible to achieve all the adjacencies of the above rules. Application of some of these rules may lead to conflicting state assignments, in such eases, the higher-priority rules should be given precedence. Even if the rules can be fully implemented, they do not guarantee an optimal assignment, ie., these rales do not constitute an optimal algorithm, Example 8.19 Partial state diagram of a sequential machine is shown in Fig. 845, ‘Make suitable state assignment for obtaining minimal logic expression. Gy) LY Reeser ae anche wa siglo tapotsrs the bemsplcte sate dingracn Se contains seven stats, oF o ox Solution ee The portion of the state diagram shown hay state transitions from @) the state 4 to C and from B to € for both the values of the input X and ¥ is the output. Since, there are 7 states, therefore, the number of State Diagram for Ex. 8.19 FLIP-FLOPS required will be log) =3 (next higher integer). Its state354 Modern Digital Electronics ‘assignment map ean be prepared giving the state transitions trom the present state fo the next state, tis similar to a K-map. tt is shown in Fig. 90, 8.46. Q,, Q, and Q, are the FLIP-FLOP outputs and the states will be ON 00 or 10 assigned binary numbers in the order 0, 0.0, 4 : ‘The two states, A and B can be assigned two adjacent oclls according to Rule 1. One possible assignment is shown in the Fig. 8:46, for which eee B A= 100 and B= 110. When the Logic function is simplified using K-map or Quine-McCluskey method, combination of two adjacent cells will ‘give a term with only two literals, Whereas if the states are assigned as Fig. 8.46 State Assignment Map 010 and 101, the expression will contain two minterms whieh cannot be 2 of EX. 819 combined. Example 8.20 For the partial state diagram of a sequential circuit shown in Fig. 8.47 make suitable state assignment for obtaining ‘minimal logic expression, Assume one single input and a total of 6 states in the state diagram. @) So 1 0 G © 0 HG | : Fig.847 State Diagram for Ex. 8.20 Fig. 848 State Assignment Map of Ex. 8.20 Solution State assignment map can be prepared similar to the Ex. 8.19. Itis shown in Fig. & ‘One possible state assignment shown in the map gives B= 001 and C= 011 Example 8.21 ‘Table 8.16 gives state table of a sequential circuit, Give a good state assignment scheme. Table 816 State Table for Ex. 8.21 Present state PS ‘Next state, Output NS,Y X=0 XI 4 BA BO. B co DA ¢ El FO D FO EA E Go 4,0 Fr AO G0 G BO BOSequential Logic Design Solution Since there are seven states in this circuit, therefore, it will have three FLIP-FLOPs FF3, FF2, and FFI with state variables Q., Q,, and Q, respectively. Application of the rules of state assignment is given below. Rulel (@) Next state from the present states 4 and G is same. Itis B, Therefore, the states A and G should be assigned adjacent codes. (®) From the present state C, the next state is £ for X=0 and F for X= 1, whereas from the present state D, the next states are F and £ for ¥= and X= 1 respectively. Therefore, Cand D may be assigned adjacent codes. Similarly, £ and F may be assigned adjacent codes. Rule 2 From the state B, the next states are Cand D, therefore, C and D may be assigned adjacent states, Similarly, £ and F; G and A may be assigned adjacent states. Rule3 ‘The outputs are same for the present states 4 and C; B and D, therefore, 4 and C; B and D, may be assigned adjacent codes, ‘Now, the state assignment is to be made so that as many as possible of these adjacencies can be accommodated. For this assignment map is prepared. Let us assign the state 000 to 4, then G must be assigned an adjacent state. There are three possible adjacent states. Any one of them can be assigned to G, since Gis not required to be adjacent to any other state. Similarly, all the other assignments are made and the resulting assignment map is shown in Fig. 8.49. The binary states are given below. 4-000 2104 oo n_10 aut a — olalelrie DAO nea eel E001 ron ; Baia State Assignment ‘Map of Ex. 8.21 8.6.6 Design Procedure For the design of any clocked sequential circuit, the following general procedure is used. 1, The design specifications may be specified in the form of a set of statements, state table, or state diagram, In case a set of statements is given, a state diagram can be constructed and from the state diagram, a state table can be constructed. In general, a state table is needed for the design. When a state diagram is constructed, it is a normal practice to use some letter symbols for the states because of the non-availability of binary values for the states, Also, a number of redundant states may be included to avoid any confusion while constructing the state diagram. The state diagram is not unique. The number of states may be reduced in case there are equivalent states (discussed below) to obtain a reduced state table which will contain the minimum number of states. Since, the number ofModern Digital Electronics FLIP-FLOPs required depends upon the number of states, therefore, this step will ensure minimum number of FLIP-PLOPs. 3. Assign binary values to the letter symbols for each state, ic. the state assignment is to be done, 4. Choose the type of FLIP-FLOP to be used. J-K PLIP-PLOP is the most general type of FLIP- FLOP. It can be T-type or D-type also depending upon the circuit requirements 5. Construct state transition table and output table and from this obtain K-maps for FLIP-FLOP. excitations and output. Minimise the K-maps and obtain minimal logic expressions for excitations and output. 6. Construct logic circuit incorporating the FLIP-FLOPs and the combinational expressions obtained in step 5. suits based on the 8.6.7 State Equivalence and Minimisation Two states are said to be equivalent if, for each input condition, they give exactly the same output and goto the same next state, Ina state table, when twa states are found to be equivalent, one of them is eliminated without altering the input-output relations. This process is referred to as state-reduction. Using the concept of equivalent states and state reduction, all possible equivalent states are determined and the reduced state table is obtained which will contain the minimum number of states. This process minimises the number of states. Example 8.22 For the state table given in Table 8.17, obtain reduced state table with minimum number of states. Table 817 State Table for Ex. 8.22 Present state Next state Output x By a é 6 0 4 a ¢ o ¢ g d 1 a e f o € f @ 1 f g f I o g 3 @ 0 1 Solution @), By observing Table 8.17, we see that from the initial state e, the next state is /for ¥=O and it is a for ¥= 1 ‘The output is @ and | for X= 0 and X= | respectively. Similarly, from the initial state g also, the next state fand a for ¥ = 0 and X= | respectively: and the output is O and | for ¥ = 0 and X= 1 respectively. From this, ‘we conclude that the two states ¢ and g are equivalent, since for each input condition, they 20 to the same next state and give same output. We can eliminate one of them, say g. Thus g is replaced by e wherever it occurs. (ii) After replacing g by ¢ in the state ble, we notice that the states d and fare equivalent, Thus, one of them, say , can be eliminated, The effect of eliminating equivalent states is illustrated in Table 8.18 and the reduced state table is given in Table 8.19. The reduced state table contwins 5 states which is the minimum number of statcs required to implement the circuit represented by the given state table,Sequential Logic Design Table $18 Effect of Eliminating Equivalent States Present state Next state Output x=0 @ @ 0 6 or p e (ge 1 d ¢ 1 e f 0 f we u 8 f ° 1 Table 8.19 Redieced State Table Present state ‘Next state Output x=0 et x a é > a 6 r c 0 © e uf 1 ¢ f a ° f e : 1 0 8.6.8 Design Examples Using the various concepts discussed for the design of clocked sequential circuits, any synchronous sequential circuit ean be designed, The following designs will illustrate clearly the application of various concepts, Example 8.23 Design a minimal clocked sequential circuit for the reduced state table given in Table 8.19, Solution The reduced state table was obtained, using state equivalence and minimisation concepts, from Table 8.17. The next step in the design is (o assign binary values to the states. Since, there are § states in this machine, therefore, the number of FLIP-FLOPS required is three; Let the three FLEP-FLOPs be designated as FF2, FFI, and FFO; and their outputs are Q,, ,, and O, respectively. Therefore, every state will be a 3-bit number with Q, value as the MSB and Q, a8 LSB, Assume D FLIP-FLOPs, From application of the rules of state assignment, we find that (@) the next states are same for the states ¢ and f for ¥ = 0 and X= 1, therefore, the states ¢ and f'should be assigned adjacent codes (Rule 1 (a)). Gi) from the states band e, the next state is ffor X= 0, therefore, the states band ¢ should be assigned adjacent codes (Rule | (e)Modern Digitat Electronics State assignment map can then be constructed, Let us assume a = 000 as the initial state, The state assignment map is shown in Fig. 8.50. Therefore, the states assi 230) ¢ states assigned are: ew rs ojalels 1 ble ‘Te state transition and output table in constmcted next From thewaiva S590. StefeAstiguaent Mae (000) the next sue is ¢ = 010. When X= 0, The output corresponding 10 this is Y= 0, these entries are made inthe first row. Similarly all the entries are made in this table. Since D-type of FLIP-FLOPS have been chosen here, therefore, it is not necessary to construct excitation table sepantely. For a D-type FLIP-FLOP for next state to be 0, the D input must be 0 just before the clock pulse. Similarly, for the next state to be |, its D input must be 1. Therefore O2, O* and Q values are the same as the excitation values of D,, D,, and D, respectively. The state transition and output table is given in Table 8.20. Table 8.20 State Transition and Output Table Present state Input Next state Output 2 2 x eet e% a 0 0 0 oO 1 oO Oo oO 1 1 a i 1 oO 0 oO 1 o Oo 1 x d 1 1 1 1 o 1 1 o 0 1 1 o o i 1 1 1 0 6 ° 1 ° 1 1 0 a 1 1 x 0 1 i) 0 oO 1 o 1 1 1 oO 1 1 1 x L 0 0 0 1 1 1 oO 1 1 1 oO Oo ‘The next step involves finding out the minimised logic expressions for D,, D,, D,, and Yin terms of ,, 0,,. Oy» and X. This is a combinational logic design problem. For this K-maps are constructed for Dy, Dy, Dy, and Yand are minimised. The K-maps are shown in Fig. 8.51 Since, there are eight states possibie using three bits, out of which only five states are required forthis eireuit. The other three states do not exist and are therefore, taken as don’t cares (As). ‘The minimised expressions are: ¥=0,0,X+ ,0,0,+0,0,x ‘The complete circuit is given in Fig, 8.52.Sequential Logie Design 399 Fig.8.51 K-Maps for Dy Dy Dy and ¥ Seannes wn Comsexmer360 Modern Digital Electronics Example 8.24 For the reduced state table given in Table 8.19, design the circuit assuming the state assignment given below. Compare the hardware requirements of this state assignment with the state assignment done in Example 8.23, a= 000, 5=001,¢=010,e=011, and f= 100. Solution The state transition and output table is given in Table 8.21, and the K-maps are given in Fig, 8.53, The unused states hhave been taken as don’t care conditions. Table 8.21 State Transition and Output Table for Ex. 8.24 Present state Input Next state Output % 2% x u oO 0 0 oO Oo a 0 0 1 0 oO 0 1 i) 0 a 0 1 1 0 oO 1 o ) 1 Qo 1 oO L 1 oO 1 1 o 0 o 1 1 L 1 1 0 i) oO 1 L 0 o 1 Oo 2,0; 2:0) otto or 10 o_o or 0 oo] 0 x]o olf it= fa alo of of of xfo ufo wi] i1p*|= 853 K-Maps for Table 8.21Sequential Logic Design ‘The minimised expressions are: ¥=0,0,+0,-X+0,-¥ The complete circuit is given in Fig. 8.54. x FF2 5 PDP as H 3° : rep te Fig. 8.54 Sequential Circuit for Ex. 8.24Modern Digital Electronics ‘The circuit can be designed using J-K FFs also (Prob. 8.30). The requirement of gates for the circuits of Figs. 8.52 and 8.54 are given below. For Fig. 852 3-input NAND gates-4 (one NAND gate can be shared between D, and 7) 2-input NAND gates-5 3-input OR gate-T For Fig. 854 4-input NAND gate-1 3-input NAND gates-6 2-input NAND gates-7 (two NAND gates can be shared between D, and Y) From the requirement of gates by two different state assignments, we can conclude that a carefully done state assignment will lead to a eireuit requiring lesser number of gates, Example 8.25 A synchronous sequential circuit is to be designed having a single input X and a single output ¥ to detect single change of level (from 0 to 1 or from 1 to 0) in a 3-bit word and produce an output Y= 1, otherwise ¥= 0. When a new 3-bit word is to come, the circuit must be at its initial (reset) state and there should be a time delay of one clock cycle between the words. Solution ‘There are eight possible words of three bits, These are; 000, 001, 010, 011, 100, 101, 110, and 111, The number of level change is one in 001, 011, 100, and 110. When any one of these words is applied bit by bit at the X input, ¥ ‘must be 1 after three clock cycles, ie., when the third bit is applied. A state diagram is to be constructed first for this. The state diagram is given in Fig, 8.55. Fig.8.55 State Diagram of Ex. 8.25 Ais the initial state. For each 3-bit word, find the next state and output bit by bit. Let us take the input word 000. When first 0 is applied, the cirenit goes to state B and output is 0, next 0 will take the circuit to D-with output 0, the third 0 will take the circuit tof with output 0. Therefore, for this 3-bit word, the ougput is 0 at the end of the third bit, Hence, we conclude that the mumber of level changes from the first to the third bit is not 1. When the fourth clock pulse appears, the circuit is reset, ic., it reaches its initial state A irrespective of the value of X(0 or 1). ‘Now consider input word 110. From the reset state the circuit goes to C—>.G—> H and produces an output of 1 at the third clock pulse indicating I level change. On fourth clock pulse, the circuit resets. Similarly, it can be verified foreach input word. ‘Next a state table (Table 8.22) is constructed from the state diagram.Sequential Logic Design _ 363 Table 822 State Table of Ex. 8.25 Present State Neat state, Output, X=0 a Bo re B Do By c FO G, D HO HA E #0 HA F WA HO G wd Ho H 40 4.0 ‘Now the state reduction table is to be constructed. From the state table, we abserve the following. Gand X= 1, therefore, these two (i). From the present states D and £, the next state and output are same for states are equivalent and state D is eliminated and replaced by state £, Gi) From the present states # and G, the next state and output are same for X°= Q and X= 1, therefore, these two states are equivalent and state G is eliminated and replaced by state F. ‘The reduced sia table is given in Table 8.23 and Fig. 8.56 gives reduced state diagram Table 8.23 Reduced State Table of Ex. 8.25 Present state Next state, Output X=0 Xe A Bo oo B E, 0 ° Fo FO E HO HA F a HO #H AO 4.0. Fig. 856 Reduced State Diagram of Ex, 8.25364 Modern Digital Electronics Since, there ate six states, therefore, the number of FLIP-PLOPs required is 3. Let us assume D FLIP-PLOPs, From the states £ and F, the next state is H for both the values of X, therefore, E and F should be assigned adjacent codes, States having same outputs should be assigned adjacent states. These are: AB, AC, BC, AH, BH, CH ‘The state assignment map is shown in Fig, 8.57, ‘The states assigned are: A=000 o » Fig. 8:57 State Assignment Map of Ex. 8.25 State transition and output table is constructed om the basis of state assignment, It is given in Table 8.24 and K-osaps are given in Fig. 8.58. ‘The minimised logic expressions are: D,=2,+ 8X4 0,0, ), OX + 0,0,X Table 8.24 State Transition and Output Table of Ex. 8.25 Present state Input Next state Output Q Q, x @: a a ¥ a 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 1 0 1 0 1 0 1 0 o 0 0 1 1 0 1 0 1 0 0 1 1 1 0 1 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 1 1 0 0 0 0 0 1 1 i 0 1 0 1 9 0 1 0 1 i 1 1 0 1 1 0 1 1 0 ao 1 1 1 o 0 0 0Sequential Logie Design 20; 210) ono 10 X00 o_o og o {fr | x\] 0 D] 0 G of o {a | J] o oo} o|lx | 4 a}olol/@ely njo}o|x]o io] of 0 [@]D Fig. 858 K-Maps of Ex. 8.25 ‘The complete circuit can be drawn using three D FLEP-FLOPs and NAND gates, Example 8.26 Design a serial adder to add two binary numbers. Solution We are familiar with the process of decimal addition using paper and pencil. tn this, digits in the same significant position are added starting from the LSD alongwith a carry generated from the addition of digits from the previous significant position. A similar process is used for the serial addition of binary numbers. Let the two binary inputs be X, and X,, At X, and x, inputs are applied sequentially. Assume X,= 10010110 X,= 1011110 ¥ = 101110100 The sum output Y does not depend on the present inputs alone, it also depends on the carry from the previous position. In the LSB (6,) position both the input bits are 0 and the output is also 0; in the next position 6,, the sum of I and | is 0 and a carry c, is generated; in the next position ,, the two 1’s alongwith the carry c, are to be added resulting in sum bit Y= 1 and so on, Therefore, a memory deviee is required to keep track of the carry input. The memory should have two states 0 and 1 corresponding to carry = 0 or 1, We can construct a state transition and output table from the above discussion, ‘Table 8.25 gives the state transition and output table and Fig. 8.59 gives K-maps for the D input of D FLIP- FLOP and output ¥Modern Digital Electronics Table 8.25 State Transition and Ouiput Table for Serial Adder Present state Taputs Next state ‘Output PS(Q) x, x NS(Q") ¥ 0 0 0 0 @ 0 o 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 o 1 1 0 1 ° 1 1 1 1 1 Heo of fa oft uf a wt The logic expressions for D and Y are: MX, +XO+XO XK O+ RX,O+XAO+K KE Tis cireuitis shown in Fig. 8.60 DS SS a clos Pt Fig. 8.60 Serial Adder CirewitSequential Logic Design 367 Example 8.27 Design a sequence detector circuit to detect a serial input sequence of 1010. It should produce an output 1 when the input pattem has been detected. Solution Let the input string be 10101010, the desired output string can be determined, which is given below: px 1 09 1 O 1 0 1 0 Oupt¥ 9 0 O 1 0 1 0 1 Asiate diagram can be constructed for the required input-output relationship, Letus start with the initial state A. If the input is 0, the detection cycle must mot start and therefore, the state remains the same and output is 0, When itis 1, it should go to the next state B with output as 0, In the present state B, ifthe input is 0 the next state will be C and output 0, while for an input |, itis to be counted as the first correct bit in the string (since it isthe second 1 bit from the start) and the state of the circuit should remain unchanged. In the Present state C, if an input bit oecur, the ciseuit should go back to the inital state (since itis second consecutive 0), while an input 1 causes state transition to next state D. When the circuit is in the state D, a 0 input will detect the correct sequence and will produce an output of 1, Ifthe input is 1, itis a second consecutive 1 which must take the circuit to the state B. The complete state diagram is shown in Fig. 8.61. Its state table is constructed as given in Table 8.26. Fig, 861 State Diagram of Sequence Detector Circuit ‘There are four states in this circuit and no equivalent states are present. Therefore, two D-type FLIP -FLOPs can be used for the implementation of this circuit Table 8.26 State Table of Sequence Detector Present state Next state, Output = D368 Modern Digital Electronics ‘The two states B and D must be assigned adjacent codes, since the mext state is same from these states for X= 0 and X= 1. Therefore, the following state assignment is made. 4500 B01 C310 Dou ‘Table 8.27 gives state transition and output table. From this K-maps are constructed for the FLIP-FLOP inputs D, and Dj; and output ¥. These are given in Fig. 8.62. State Transition and Output Table Present state Input Next state ‘Output 2, a x o ¥ 0 0 0 0 o 0 1 0 0 0 1 0 0 0 0 0 1 1 ° 1 ° 1 0 0 1 0 1 0 0 1 1 0 1 0 1 0 1 1 1 0 1 1 1 0 1 0 2) 25 212 e ot 10 ae no of o/@[D] 0 of ojo}alo t}o]/e}o|@ ijaG[afit yp B 2199 *\_00_o1_ to of 0} o1@]o ifo}o]o]o ¥ 1 X+9,0,X D,-x ¥=0,0,%Sequential Logic Design _ 369 Tis circuit diagram is given in Fig, 8.63. Clock Fig. 8.63 Cireuid of Sequences Detector 8.7 ASYNCHRONOUS SEQUENTIAL CIRCUITS The two types of sequential circuits were introduced in Section 7.1. The design of clocked sequential circuits have been discussed in section 8.6. Another important class of sequential circuits, i.e, asynchronous sequential circuits have been discussed here. 8.7.1 Asynchronous versus Synchronous Sequential Circuits + In a clocked sequential circuit a change of state occurs only in response to a synchronizing clock pulse, All the PLT P-FLOPs are clocked simultaneously by a common clock pulse. In an asynchronous sequential circuit, the state of the circuit can change immediately when an input change accurs. It docs not usea clock. + In clocked sequential circuits input changes are assumed to occur between clock pulses. The circuit must be in the stable state before next clock pulse arrives. In asynchronous sequential circuits input changes should occur only when the circuit is in a stable state,370 Modern Digital Electronics + In clocked sequential circuits, the speed of operation depends on the maximum allowed clock frequency. Asynchronous sequential circuits do not require clock pulses and they can change state with the input change. Therefore, in general the asynchronous sequential circuits are faster than the synchrous sequential circuits. + Inclocked sequential cizcuits, the memory elements are clocked PLTP-PLOPs. In asynchronous sequential circuits, the memory elements are either unclocked FLIP-FLOPs (latches) or gate circuits with feedback producing the effect of latch operation. + Inclocked sequential circuits, any number of inputs can change simultaneously (during the absence of the clock). In asynchronous sequential circuits only one input is allowed to change at a time in the case of the level inputs and only one pulse input is allowed to be present in the case of the pulse inputs. If more than one level inputs change simultaneously or more that one pulse input is present, the circuit makes erroneous state transitions due to different delay paths for each input variable. 8.7.2 Applications of Asynchronous Sequential Circuits + An asynchronous circuit is preferred over synchronous circuit when high speed of operation is required since asynchronous sequential circuits respond immediately whenever there is a change in any input variable without having to wait for a clock pulse. + Asynchronous sequential circuits are useful in applications in which input signals may change at any c + Asynchronous. sequential circuits cost less than the sequential circuits, therefore, for economical reasons, they find useful applications. 8.7.3 Asynchronous Sequential Machine Modes There are two modes of operations of asynchronous sequential machines depending upon the type of input signals. These are: + Fundamental Mode + Pulse Mode Fundamental Mode Ina fundamental mode circuit, all of the input signals are considered to be levels. Fundamental mode operation assumes that the input signals will be changed only when the circuit is in a stable state and that only one variable can change at a given time. Pulse Mode In pulse mode circuits, the inputs are pulses rather than levels. In this mode of operation the width of the input pulses is critical o the circuit operation. The input pulse must be long enough for the circuit to respond to the input but it must not be so long as to be present even after new state is reached. In such a situation the state of the circuit may make another transition.Sequential Logic Design _ 371 The minimum pulse width requirement is based on the propagation delay through the next-state logic (Fig 7.1). The maximum pulse width is determined by the total propagation delay through the next state logic and the memory elements. Both fundamental and pulse mode asynchronous sequential circuits use unclocked S-R FLIB-FLOPs or latches. In pulse-made operation, only one input is allowed to have pulse present at any time, This means that when pulse occurs on any one input, while the circuit is in stable state, pulse must not arrive at any other input. Figure 8.40 illustrates unacceptable and acceptable input pulse change. X, and X, are the two inputs to a pulse mode circuit. In Fig. 8.64a at time , pulse at input X, arrives. While this pulse is still present, another pulse at X, input arrives at #,. Therefore, this kind of the presence of pulse inputs is not allowed, (a) Unacceptable Pulse Mode Input Changes % J 1 (b) Acceptable Pulse Mode Input Changes Fig. 8.64 8.74 Analysis of Asynchronous Sequential Machines Analysis of asynchronous sequential circuits operation in fundamental mode and pulse mode will help in clearly understanding the asynchronous sequential circuits. Fundamental Mode Circuits Fundamental mode circuits are of two types + Circuits without latches * Circuits with latches Circuits Without Latches Consider a fundamental mode circuit shown in Fig. 8.65, This circuit has only gates and no explicit memory elements are present. There are two feedback paths from @, and Q, to the next-state logic circuit, This feedback creates the latching effect due to delays, necessary to produce a sequential circuit, It may be noted that a memory element latch is created due to feedback in gate circuit (Fig. 7.4). The first step in the analysis is to identify the states and the state variables. The combination of level signals from external sources X,, X, is referred to as the input state and X,,.X, are the input state variables.Modern Digital Electronics ee Xje——+ +— External Next State Tua Inputs Logie é Logie Xo» + @ ‘Next State Do Logie Output Logic ® Fig. 8.65 Fundamental Mode Asynchronous Sequential Cireuit Without Latch TTT To "> Gq) Block Diagram (b) Circuit DiagramSequential Logic Design _ 373 ‘The combination of the outputs of memory elements are known as secondary, or internal states and these variables are known as internal or secondary state variables. Here, , and Q., are the internal variables since no explicit elements are present. The combination of both, input state and the secondary state (0, 0» Xj,%,) is known as the total state. Y is the output variable. ‘The next secondary state and output logic equations are derived from the logic circuit in the next-state logic block. The next secondary state variables are denoted by Q' and Q these are given by (8.6) 7) (8.8) Here, 0, and Q, are the present secondary state variables when X, X’,input-state variables oceur, the circuit ‘goes to next secondary state. A state table shown in Table 8.28 is constructed using these logic equations. If the resulting next secondary state is same as the present state, ie. Q;= Q, and Q} = Q,, the total state 0,0, X,X, is said to be stable. Otherwise it is unstable. The stability of the next total state is also shown in Table 8.28 Transition Table A state table can be represented in another form known as transition sable, The transition table for the state table of Table 8.28 is shown in Fig. 8.66. In a transition table, columns represent input states (one column for each input state) and rows represent secondary states (one row for each secondary state). The next secondary state values are written into the squares, each indicating a total state, The stable states are circled. For any given present secondary state (OQ, Q,), the next secondary state is located in the square corresponding to row for the present secondary state and the column for the input state (X,X,). For example, for Q, Q, = 1] and X,X,~ 00, the next secondary state is 00 (third row, first column) which is an unstable state. Table 8.28 State Table Present total state ‘Next total state Stable total state ‘Output x, YesiNo x fy iS ct bee 8 Yes No Yes No No No Yes No No Yes No Yes No Yes Yes Yes Ss seiee ope aseece a eee ee et+oo-H+co--soHus ie Ease a ees a skp ses | itModern Digital Electronics Next state Input state QQ! Preset intemal Sy me oe ool uN 10. 00 a 10 1 7 oa fioo | on | Cor] on Nett v ; ue fioo [Geo [yar 10 | 00 | (10) | (10) Fig. 8.66 Transition Table for Table 8.28 For a given input sequence, the total state sequence can be determined from the transition table. Example 8.28 For the transition table shown in Fig 8.66, the initial total state is Q, @, XX, = 0000. Find the total state sequence for an input sequence x, X,= 00, 01, 11, 10, 00. Solution For a given intemal state of the circuit, a change in the value of the cireuit input causes a horizantal move in the ‘eansition table to the column corresponding to the new input value. A change in the intemal state of the circuit is reflected by a vertical move, Since a change in the input eam occur only when the circuit is in a stable state, a horizontal move can emanate only from a eireled entry. ‘The initial total state is 0000 (first row, first column) which is a stable state, When the input state changes from 00-10 01, the circuit makes a transition (horizontal move) from the present total state to the next total state O10) (frst row, second column) which is unstable, Next, the circuit makes another transition from 0101 to 1101 (vertical move) (second row, second calumn) which is also an unstable state. Finally in the next transition (vertical move) it comes to stable state 1101 (third row, second column), All these transitions are indicated by arrows, Thus we see that a single input change produces two secondary state changes before a stable total state is reached, Ef the input ig next changed to 11 the circuit goes to total state O111 (horizontal move) which is unstable and then to stable total state OI11 (vertical move). Similarly, the next input change to 10 will take the circuit to unstable total state 1110 (horizontal move) and finally to stable total state 1110 (vertical move). A change in input state from 10 t0.00 causes a transition to unstable total state 0000 (horizontal move) and then to stable total state 0000 (vertical move), completing the state transitions for the input sequence, All the state transitions are indicated by arrows, The total state sequence is 01 — i> —- GD— G>—- Gi From the above discussions, we see that from the logic diagram of an asynchronous sequential circuit, logic equations, state table, and transition table can be determined, Similarly, from the transition table, logic equations can be written and the logic circuit can be designedSequential Logic Design 375 Flow table in asynchronous sequential circuits design, it is more convenient to use flow table rather than transition table, A flow table is basically similar to a transition table except that the internal states are represented symbolically rather than by gate eee binary states. The column headings are the present internal \X; X. ale Stat input combinations and the entries are the next state Q) Qs om uy 10 states, and outputs. The siate changes occur change of inputs (one input change at a time) ee? F 0) GAL dr and next state logic propagation delay. = The flow of states from one to another is b\lat tear |@.o]/eo clearly understood from the flow table, The 4 ion table of Fig, 8.66 constructed as a flow table is shown in Fig. 8,67. Here, a, 6, c, and d are the states. ‘The binary value of the output variable is indicated inside the square next to the state symbol and is separated by a comma. A stable state is circled. Fig 867 Flow Table From the flow table, we observe the following behaviour of the cireui When XX, = 00, the circuit is in state @. It isa stable state. IfX, changes to | while X, = 0, the circuit goes | 0 cflao |taof!nt [lot tran: wading) a] at |@D1]@.0]@o Unstable State move), which is again an unstable state. This causes another vertical move and finally the circuit reaches a stable state ©. Now consider X, changing to 1 while X,~ 1, there is a horizontal movement to the next column. Here 6 is an unstable state and therefore, there is a vertical move and the circuit comes (o a stable state @. Next change in X, from 1 to 0 while X, remaining 1 will cause horizontal move to state ¢ (unstable state) and finally to stable state @ due to the vertical move. Similarly changing X, from | to 0 while X,=0 will cause the circuit to go to the unstable state a and finally to stable state @. The flow of circuit states are shown by arrows. In the flow table of Fig. 8.67 there are more than one stable states in rows, For example, the first row contains stable states in two columns. If every row in a flow table has only one stable state, the flow table is known as a primitive flow tabie, From a flow table, transition table can be constructed by assigning binary values to each state and from the transition table logic circuit can be designed by constructing K-maps for Q} and Q} Circuits with Latches In Section 7.2 latch was introduced using NAND gates. Latch circuits using NAND and NOR gates are shown in Fig. 8.68. For the circuit of Fig 8,68c, the next-state equation is Q = 5-0 =5-(OR) =5+RO 9) Similarly, for the circuit of Fig. 8.682, the next-state equation is R-(S+Q) =SR+ROModern Digital Electronics = 1is not allowed, which means SR = 0, therefore, SR =SR+SR=S(R+R)=S §o—_{ —{ p——e R ° —| - * ‘ ~— "| (a) b) (a) 5-R Latch Using MAND Gates (b) S-R Latch Using NOR Gates 8.68 which gives, Q-5+Ro It is same as Eq. (8.9) ‘The transition table of S-R latch is shown in Fig. 8.69. ° oo ot u 10 1O/@O/@O]: |@)le|le|@| Pe Fig. 8.69 Transition Table of S-R Latch From the transition table of S-R FLIP-FLOP, we observe that when SR changes from 11 to 00 the circuit will attain cither the stable state @) (first row, first column) or @) (second row, first column) depending upon whether S goes to 0 first or R goes to 0 first respectively. Therefore, § = R= | must not be applied. Consider an asynchronous sequential circuit with latches shown in Fig, 8.70. For FF-1, R, = 0 and the excitation equation for S, is 5,=%, 40+ X9, ‘The next-state equation is O-5,+R0, Substituting the value of S, from Eq. (8.10) in Eq. (8.11) we obtain, 9; =X, 40, + X0,+ 2, (8.10) (@.1) (8.12)Sequential Logéc Design _ 377 ® Asynchronous Sequential Circuit with Latches ‘Similarly, the excitation equations for FF-2 are $= %,4X,0,,R,= XX, 0, @.13) ‘The next-state equation is 2: X,X,0,+ X%,0,- 0, (8.14) Using Eqs. (8.12) and (8.14), transition table is obtained as shown in Fig. 8.71. The output function is , ¥=X,X,0,0, (8.15) Xi% Q7 O; ou | nun] @|@ 1 ©) @|@}/@ Fig. 8.71 Transition Table for the Circuit of Fig. 8.70378 Modern Digital Electronics Mi Ae of oF 2,0, oo iu a} @0]@0| 60] a0 bl 640} 60 |@,0|/@o c]@o] 40} @1/ oo 4! @,o| @.0] @.0] @.o Fig. 8.72 Flow Table for the Circuit of Fig. 8.70 From a flow table, transition table can be obtained by assigning binary values to the states. From the transition table, logic equations can be obtained by constructing K-maps for S and R inputs of every latch. For this, the excitation table of S-R latch will be used. Logic circuit can then be designed using the logic equation for S, R inputs of every latch. Example 8.29 Design logic cireuit using S-R latches for the transition table of Fig. 8.66. Solution Since, there are two intemal states Q, and Q,, therefore, two S-2 latches are required forthe design of logic circuit, Let the two latches be Land £,. The inputs and outputs of these latches are given below. Latch Inputs Outputs L SiR 2 @, 1 SR OB ‘The excitation table ofan 5-f latch is given in Table 8.29: This is same as Table 7.1 for S-R FLIP-FLOP Table 829 Excitation Tabte of S-R Latch Present state ‘Next state Inputs 2 a s R °Sequential Logic Design _ 379 ‘To determine S, and R, for different values of X, X, we make use of Q, and QF values for every square of transition table. For example, the square in the first row and first column gives Q, = 0 and Q;=0. This means, for the present state 0 the circuit gives next state as 0 for Q,. Corresponding to this we find the value of S, and R, using, the Table 8.29, which are 5,=0 and R=X ‘Thus the entry in the cell corresponding to X, X,~00 and Q, Q, ~ 00 for K-map of $, will be @ and for K-map of R, it will be X. Similarly, K-map entries are determined for 5, and. Following similar procedure, K-maps for S, and R, are constructed. The K-maps are given in Fig. 8.73. Se S18 ee on ww wm oo }/t\| o | 0 oo} fx\ | O | x | x «la ellie ls dPlle[e[- tal [@ [= ofl [el (6) K-Map for 5 (@) K-Map for Ry From the K-map of Fig. 8.73, we abtain logic equations for 5,, R, S,,and R,. XH % 2, HE+K LO, 442, a= KR380 Modern Digital Electronics The logic circuit Xjo—_f %o— shown in Fig. 8.74. 5, 2 9% 2 % a {oo tye—_ —— } Qe Qe — %, % > a x, R. _ % * 2 Fig.8.74 Logie Circuit for Ex. 8.29 Races and Cycles Arace condition exists in an asynchronous sequential circuit a sie when more than one state variable change value in response gine OF Oo : Sa 0,0; oo ol ul 10 to.a change in an input variable. This is caused because of unequal propagation delays in the path of different secondary oof 1 | @ | wo | o variables in any practical electronic circuit, Consider a transition table shown in Fig. 8.75, When both the inputs X, af uo lan |@ and X, are 0 and the present state is Q, Q, = 00, the resulting \ next-state Q; Q will have Q+= 1 and Q;= 1 simultaneous } O10; Qi Q: ly i] @| w | a | @ if the propagation delays in the paths of 0, and Q, are equal. ‘Since Q, and Q, both are to change and in general the 7 propagation delays in the paths of Q, and Q, are not same, wo} 7] @ u therefore, either Q, or Q, may change first instead of both changing simultaneously. As a consequence of this the circuit ie. 875 will go to either state 01 or to state 10. .Sequential Logic Design If Q+changes faster than Q, the next state will be OL, then 11 (first column, second row) and then the stable state @ (first column, third row) will be reached. On the other hand, if QO! changes faster than Q}, the next- state will be 10, then 11 (first column, fourth row) and then to the stable state (1) (first column, third row) will be reached. In both the situations, the circuit goes to the same final stable state (1). This situation, where a change of more than one sccondary variable is required is known as a race. There are two types of races: noneritical race and critical race. In the case of noneritical race, the final stable state in which the circuit goes does not depend on the sequence in which the variables change. The race discussed above is a noncritical race, In the case of critical race, the final stable state reached by the eircuit depends on the sequence in which the secondary variables change. Since the critical race results in different stable states depending on the sequence in which the secondary states change, therefore, it must be avoided, Example 8.30 In the transition table of Fig. 8.75, consider the circuit in stable total state 1100, Will there be any race, if the input state changes to 01? If yes, find the type of race Solution Ay dy OF OF When the circuit is in stable total state, XX, = 00. Now XQ. g, o oo nu 10 changesto I while X, = 0. From Fig. 8.75 we see that the required transition isto state 00, If Q:and Q; become 00 simultaneously, i) 1 then the transition will be t OQ > 0 + @ OL 00 ‘These transitions are shown by solid arrows in Fig. 8.76, If: decomes 0 fasier than GQ}, the cireuit will go to the state 10 and ul @ | 00 then to (0, which isa stable state. The transition is sal @ > 0 = @ 10) ‘On the other hand, if Q; becomes 0 faster than Q3,the transition will be Fig. 8.76 Dra5.n+@ It is shown by dotted arrow in Fig. 8.76. Thus, we see that the circuit attains different stable states 69 or depending up on the sequence in which the secondary variables change. Therefore, the race condition cxists in this circuit and itis eritical race. Races can be avoided by making a proper binary assignment to the state variables in a flow table. The state variables must be assigned binary numbers in such a way so that only one state variable can change at any one time when a state transition occurs in the flow table. The state transition is directed through a unique sequence of unstable state variable change. This is referred to as a cycle. This unique sequence must terminate ina stable state, otherwise the eircuit will go from one unstable state to another unstable state making the entire circuit unstable,Modern Digital Electronics Example 831 In the state transition table of Fig, 8.7 changed to 1 while X, remaining 1 'X, X= 10 and the circuit is in stable state @, find the eyele when X, is Solution ‘The circuit is in stable state @D (fourth column, second row). When X, changes to 1, the circuit will go to the state 11 (third column, second row), then to state 10 (third column, third row) and finally to the stable state (0) (third column, fourth row). Thus the eyele is @>n 5h > @ Pulse-Mode Circuits Ina pulse mode asynchronous sequential circuit, an input pulse is permitted to occur only when the circuit is in stable state and there is no pulse present on any other input. When an input pulse arrives, it triggers the circuit and causes a transition from one stable state to another stable state so as to enable the circuit to receive another input pulse. In this mode of operation critical race can not occur. To keep the circuit stable between two pulses, FLIP-FLOPs whose outputs are levels must be used as memory elements. For the analysis of pulse-mode circuits, the model used for the fundamental-mode circuits is not valid since the circuit is stable when there are no inputs and the absence of a pulse conveys no information. For this a model similar to the one used for synchronous sequential circuits will be convenient to use. In pulse-mode asynchronous circuits the number of columns in the nextestate table is equal to the number of input terminals. Consider a pulse-mode circuit logic diagram shown in Fig. 8.77. In this circuit there are four input variables X,AyXy and X, and Y is the output variable, It has two states Q, and Q,, x e— o.°—1 Fig. 8.77 A Pulse-Mode Asynchronous Circuit