Unit-5: Combinational Circuit
Adders
Subtractor
Comparator
Parity Generator
Combinational Circuits
• output depends only on the present input
• The combinational circuit do not use any memory.
• The previous state of input does not have any effect on the present state of the circuit.
Half Adder
A combinational logic circuit with two inputs and two outputs.
The half adder circuit add two single bit Cary number
This circuit has two outputs carry and sum.
S(A, B) = ∑m (1, 2)
CY(A, B) = ∑m (3)
Full Adder (1-bit Adder)
A combinational logic circuit with 3 inputs and 2 outputs.
The Full adder circuit add 3 single bit Cary number
This circuit has two outputs carry and sum.
ABC ABC ABC ABC
Sum(A, B,C) = ∑m (1, 2, 4, 7)
Cout(A, B, C) = ∑m (3,5,6,7) A( BC BC ) A( BC BC )
A( B C ) A( BC )
Let B C D
AD AD
A D
A B C
For Cout
ABC ABC ABC ABC
C ( AB AB ) AB (C C )
( A B )C AB
Cout=AB+BC+AC
Full Adder using Half Adder
FA
Sum= A⊕B⊕C
Carry=AB+(A⊕B)C
HA
Sum= A⊕B
Carry=AB
4-bit Ripple Carry Adder
Half Subtractor
Combinational circuit perform binary Subtraction
Accepts 2 input and Two output Difference and Borrow
D(A, B) = ∑m (1, 2)
Br(A, B) = ∑m (1)
Full Subtractor
Performs subtraction of 3 bits
This circuit has three inputs and two outputs.
The three inputs A, B and C, denote the minuend, subtrahend, and previous borrow, respectively.
The two outputs, D and Bout Sum(A, B,C) = ∑m (1, 2, 4, 7)
Bout(A, B,C) = ∑m (1,2,3,7)
Bout = A’B’C + A’BC’ + A’BC + ABC
= C(AB + A’B’) + A’B(C + C’)
= C( A XNOR B) + A’B
= C (A XOR B)’ + A’B
Full Subtractor using Half Subtractor
FS
Sum= A⊕B⊕C
Carry=A’B+(A⊕B)’C
HS
Sum= A⊕B
Carry=A’B
1-BIT Magnitude Comparator
GT
A 1-Bit
Magnitude EQ
B Comparator LT
EQ
GT LT
GT=AB’
EQ=A’B’+AB
LT=A’B
Parity Generator Circuit
Even Parity Generator Odd Parity Generator
If odd number of ones present in the input, then If even number of ones present in the input,
even parity bit, P should be ‘1’ so that the then odd parity bit, P should be ‘1’ so that the
resultant word contains even number of ones. resultant word contains odd number of ones
Binary Even Parity
Input WXY bit P Binary Odd Parity
Input WXY bit P
000 0
000 1
001 1
001 0
010 1
010 0
011 0
011 1
100 1
100 0
101 0
101 1
110 0
110 1
111 1
111 0