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2006 IEEE Electrical Performance of Electronic Packaging

Multiple Edge Responses for Fast and Accurate System Simulations
Dan Oh
Rambus Inc.
4440 El Camino Real, Los Altos, CA 94022
Tel: 650-947-5363, Fax: 650-947-5001, dohgrambus.com
ABSTRACT
Fast and accurate simulation of the system response is important in high-speed I/O system design
because performance is severely limited by channel ISI and random noise. This paper presents a novel way to
simulate the signal response given an arbitrary bit pattern using multiple edge responses (MER). The presented
method provides an accuracy improvement over the traditional approaches which either uses the superposition
of single bit response (SBR) or double edge response (DER), while maintaining the equivalent numerical
efficiency.
I. INTRODUCTION
Modern high-speed I/O systems are more limited by channel intersymbolic interference (ISI) and
random noise than driver circuit performance; hence, accurate channel simulation including these deterministic
and random effects is crucial in designing high-speed I/O systems. Although conventional circuit simulators,
such as HSPICE, can accurately simulate the system response, it is computationally prohibitive for calculating
some of key system parameters such as bit error rates (BER). To overcome this limitation, the superposition of
single bit response (SBR) is widely used in many applications such as determining the worst case system
performance [1] and calculating the ISI probability distribution for statistical channel simulators which predict
system bit error rates [2]-[5]. As this paper will demonstrate, the techniques based on SBR assume the rising
and falling edges are symmetric. Although this is true for differential signaling systems, single-ended signaling
systems may have different rising and falling edge responses due to either asymmetric I/O design or
mismatches between pull-up and pull-down drivers. An alternative way of estimating system response is based
on double edge responses (DER) which consist of rising and falling edge responses [6]. As shown in this paper,
this approach works in terms of edge transitions and it overcomes the symmetric assumption used in the SBR
based method. Recently, DER has been also used to formulate the calculation of the ISI probability
distribution for statistical simulators, broadening the applications of these simulators to even single-ended
signaling systems [7].
The biggest bottleneck of these superposition approaches based on SBR and DER is that they cannot
accurately model nonlinear drivers. To overcome this limitation, this paper uses the superposition of multiple
edge responses (MER). Similar to the DER based approach, the presented method is also applicable to systems
with asymmetric rising and falling edge responses. In the next section, we will first briefly review the existing
SBR and DER methods; then, the MER method will be introduced in detail. It will be shown that the simplest
form of the MER method uses both SBR and DER. In the following section, both differential and single-ended
signaling systems are considered as numerical examples to demonstrate the accuracy of SBR, DER, and MER
methods.

II. FAST SYSTEM SIMULATION BASED ON THE SUPERPOSITION OF BIT OR EDGE RESPONSES
A. Single Bit Response (SBR)
Let us first review the SBR approach using an example case. The goal is to find the system response of
an arbitrary input data pattern using only the single bit response which originates from either simulation or
measurement. We will consider the rather short data pattern 0111001010 as our example case. In practice, we
would like to compute the response of much longer data pattern. Any arbitrary data pattern can be represented
as a linear sum of the shifted version of a single bit response. For instance, 0111001010 = 0100000000 +
0010000000 + 0001000000 + 0000001000 + 0000000010. Special care is needed during the discretization of
the original single bit response to avoid numerical error due to the misalignment of the shifted bit responses.
This misalignment can be avoided by using a very small time step or the time step which is an integral division
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of the signal bit time. The misalignment issue also exists for other DER and MER methods. It is important to
note that the original single bit response is generated using an overall channel including any nonlinear drivers,
and it is not the same as the pulse response of the passive channel which is purely linear and does not contain
any nonlinear driver behavior. The length of the input single bit response can be kept very short compared to
the overall simulation time and it is often limited by the dynamics of the pulse response of the passive channel.
As we focus on the first three terms of the previous superposition, it is apparent that the falling and
rising edges must be symmetric in order to avoid spurious glitches between consecutive ones. Due to this
inherent assumption of the SBR method, it may not be applied to most of single-ended signaling systems
where rising and falling edges are often asymmetric due to either the intrinsic asymmetric I/O driver
architecture or parasitic mismatch between pull-up and pull-down drivers. To handle more general cases with
asymmetric rising and falling edges, we can formulate the problem in terms of edge transitions instead of bit
responses. In the following subsection, the double edge responses (DER) consisting of rising and falling edge
responses is reviewed.
B. Double Edge Responses (DER)
The DER method decomposes the input data pattern in terms of rising and falling edge transitions. The
target system response is calculated by superimposing the shifted version of rising and falling edge responses.
For instance, 0111001010 0111111111 + 1111000000 + 0000001111 + 1111111000 + 0000000011 +
1111111110 + dc adjustment. Implementation of DER is slightly more complicated than SBR as proper dc
level adjustment has to be performed whenever either rising or falling edge responses are added. Similar to the
SBR case, it is also important to note that the original rising and falling edge responses are generated using an
overall channel including any nonlinear drivers, and it is not the same as the step response of the passive
channel.
C. Multiple Edge Responses (MER)
Both SBR and DER approaches can account for some of the nonlinear driver effect during the current bit
time as the original response is generated using actual nonlinear drivers. However, they cannot completely
capture the nonlinear effect for the rest of the responses as the driver switching activity is not considered
during the rest of responses. To illustrate this point, let us consider an artificial nonlinear driver with three
different driver impedances at three different voltage levels: x, y, and z for the low, transition, and high levels,
respectively, as shown in Fig. 1. Let us tag the rising and falling edge responses of DER with driver impedance
settings: RISE(x,y,z,z,z) and FALL(z,y,x,x,x). The single bit response can be also denoted as SBR(x,y,z,y,x).
According to Fig. 1, the singe bit response can be decomposed to the superposition of rising and falling edges
as follows:
SBR(x, y, z, y, x) RISE(x, y, z, y, x) + FALL(z, z,z,y, x) RISE(x, y, z, z, z) + FALL(z,z, y, x)
z, (1)
As shown in this equation, due to the following falling edge transition, the rising edge in the SBR response
goes through different impedance conditions (x,y,z,y,x) compared to the original rising edge without any
following edge transitions (x,y,z,z,z). Therefore, we can no longer accurately construct the single bit response
using the original rising and falling edge responses. Similarly, we can also show that SBR cannot be used to
accurately compute any two or more consecutive ones. To overcome this difficulty, we can have multiple
rising and falling edges depending on the previous bit patterns. For instance, if we had an additional rising
edge response of RISE(x,y,z,y,x), we could have reproduced an accurate single bit response. Unfortunately, this
approach does not work because, in order to determine the proper rising edge for this case, we need the
information of a following falling edge which is not available at the current time. Instead, we propose to create
new falling edges depending on the status of the previous rising edge as follows (see Fig. 2):
fall(O) fall,
fall(l) bit(up,I) rise + Vhigh, (2)
fall(2) bit(up,2) rise + Vhigh.^
where bit(up,i) denotes the up-bit (010) response with consecutive i Is. Similarly, we can derive multiple
rising edge responses as follows:
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rise(0) rise,
rise(l) bit(down,l) - rise + V10o, (3)
rise(2) bit(down,2) - rise + Vi0,w
where bit(down,i) denotes the down-bit response (101) with consecutive i zeroes. This formulation naturally
reduces to DER if we have only one rising and falling edges. For many applications, a simple version of MER
based on rising and falling edges and single-bit up and down responses is sufficient. This simple version is
used in our numerical examples. For other applications, we can use a more general form of MER which
derives multiple edges based on all possible combinations of previous bit patterns. The depth of the previous
bit pattern to be tracked depends on the channel response time and is not a function of simulation length.
IV. NUMERICAL EXAMPLES
Let us first consider a simple differential signaling system using a current source as shown in Fig. 3. The
single bit response and rising and falling edge responses form HSPICE simulation are shown in Fig. 4. The
system response of 0111001010 data pattern is approximated using SBR, DER, and MER and the resulting
data are compared in Fig. 5. An excellent match is found for all cases. The error plot is shown in Fig. 6. All
three approaches result in similar errors for this case.
For the second example, an RDRAM memory channel [8] is considered. The overall system consists of
an RDRAM controller with two 16-device memory modules as shown in Figure 7. The simulation is
performed for the write transaction from a controller to dram. The input waveforms for this single-ended
signaling system are shown in Fig. 8. Figure 9 shows the calculated waveforms for the previous data pattern
and Figure 10 shows the error plot. As you can see from these figures, the response calculated from SBR
shows spurious ripples during a long period of Is.
V. SUMMARY
In this paper, a fast and accurate way to calculate the system response has been introduced. The method
is based on the responses of multiple edges which are derived from various bit switching patterns. The method
is compared with the traditional approaches based on single bit response and double edge responses. Although
we have demonstrated our method using a single line system, the method can be easily extended for coupled
line systems. Furthermore, the worst-case search algorithm described in [1] and [6] can be also developed
based on MER.
REFERENCES
[1] H.-J. Liaw, X. Yuan, and M. A. Horowitz, "Technique for determining performance characteristics of
electronic devices and systems," US Patent 6920402, Mar. 7, 2001.
[2] B. Ahmad, "Performance Specification of interconnect", DesignCon February 2003.
[3] B.K. Casper et al, "An accurate and efficient analysis method for multi-Gb/s chip-to-chip signaling
schemes," IEEE Symposium on VLSI Circuits, June 2002, pp. 54-57.
[4] V. Stojanovic and M. Horowitz, "Modeling and analysis of High-speed links", IEEE Custom Integrated
Circuits Conference, September 2003
[5] A. Sanders, M. Resso, and J. D'Ambrosia, "Channel compliance testing utilizing novel statistical eye
methodology," DesignCon February 2004.
[6] F. Lambrecht, C.-C. Huang, and M. Fox, "Technique for determining performance characteristics of
electronic systems, " U.S. Patent 6775809, Mar. 14, 2002
[7] D. Oh, "Method for computing statistical system performance of high-speed links with the rising and
falling edge responses," in preparation.
[8] C.-C. Huang, D. Nguyen, D. Oh, W.-Y. Yip, and D. Secker, "RDRAM channel design with 32-bit 4.8GB/s
memory modules," Proc. IEEE 11th Topical Meeting on Electrical Performance of Electronic Packaging,
EPEP'02, pp. 19-22, Oct. 21-23, 2002.
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0.02

0.01
-- -
DE
DER
Single Bit x .y. z
o0.00

Rising Edge x . Z .y x .02 2

O 0
.0
3r0 1 p5/4 4 .5

Figure 1. Various responses of an artificial nonlinear driver with

three different driver impedances: x, y, and z. -0.02
Time (nsec)
Figure 6. Error compared to HSPICE case for the differential
signaling system.

Figure 7. Example single-ended signaling system: RDRAM driver

Figure 2. Illustration figures for the MER based on rising and falling with two 16-device memory modules.
edge responses and bit responses with multiple durations.
2.0
1.8
5 1.6 ,
I RISE
Probing Point "-, 1.4 - -A - - - - FALL
Package I:\ - - - - SBR (Up)
m 1.2
SBR (Down)
0

Differential: 1.0 --
. Current-Mode :
Driver 3,, 0.8
*. . . .. . . . .. . . .

0.6
Figure 3. Example I/0 channel with a differential current driver. 2.0 7.0 12.0
Time (nsec)
Figure 8. Single bit, rising and falling edge responses of the single-
ended signaling system in Fig. 7.
0.4
2.0
0.3
0.2 1.8
0.1 5 1.6 HSPICE
a,
0.0 "-, 1.4 - -SBR
- - - - DER
-O0. 1 "e m
0
1.2
0
MER
-0.2 g 1.0 ;,

-0.3 0.8
-0.4 0.6
Time (nsec)
2.0 7.0 12.0
Figure 4. Single bit, rising and falling edge responses of the Time (nsec)
differential signaling system in Fig. 3. Figure 9. 0111001010 responses of the single-ended signaling
system using SBR, DER, MER, and HSPICE.
0.05
0.4
0.00
0.2
c~ X / ~~HSPICE 5-0.05
X / ~- - - -SBR l
0.0 X X ~-
g1 ,0 Z5
- - - DER
MER 4. 45
2 -0.10
-0.2 -0.15
-0.20
-0.4 Time (nsec)
Time (nsec)
Figure 5. 0111001010 responses of the differential signaling system Figure 10. Error compared to HSPICE case for the single-ended
using SBR, DER, MER, and HSPICE. signaling system.
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