Arithmetic Building Blocks
Datapath elements
Adder design
Static adder
Dynamic adder
Multiplier design
Array multipliers
Shifters, Parity circuits
ECE 261
James Morizio
Input-Output
A Generic Digital Processor
MEMORY
CONTROL
DATAPATH
ECE 261
James Morizio
Building Blocks for Digital Architectures
Arithmetic unit
- Bit-sliced datapath (adder, multiplier,
shifter, comparator, etc.)
Memory
- RAM, ROM, Buffers, Shift registers
Control
- Finite state machine (PLA, random logic.)
- Counters
Interconnect
- Switches
- Arbiters
- Bus
ECE 261
James Morizio
Bit-Sliced Design
Metal 2
(control)
Signals
Data
Control
Control
Metal 1
(data)
Bit 2
Bit 1
Bit 0
Data-out
Multiplier
Shifter
Adder
Register
Data-in
Bit 3
Tile identical processing elements
ECE 261
James Morizio
Single-Bit Addition
Half Adder
S = A B
Cout
Cout = AgB
A
0
0
1
1
ECE 261
B
0
1
0
1
Cout
0
0
0
1
Full Adder
S = A B C
Cout
Cout = MAJ ( A, B, C )
S
A
0
0
0
0
1
1
1
1
S
0
1
1
0
James Morizio
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
Cout
0
0
0
1
0
1
1
1
S
0
1
1
0
1
0
0
1
5
Full-Adder
A
Full
Cin adder
Cout
Sum
ECE 261
James Morizio
The Binary Adder
A
Cin
Full
adde r
Cout
S um
Sum = A B C
= ABCi + ABCi + ABCi + ABCi
Co = AB + BCi + ACi
ECE 261
James Morizio
Sum and Carry as a functions
of P, G
Define 3 new variable which ONLY depend on A, B
Gen erate (G) = AB
Prop agate (P) = A +B
ECE 261
James Morizio
The Ripple-Carry Adder
A0
Ci,0
A1
B0
Co,0
FA
FA
A2
B1
A3
B2
Co,2
Co,1
FA
FA
S2
S3
B3
Co,3
(= C i,1 )
S0
S1
Wo rs t ca s e d e la y lin ea r with th e n u m b e r o f b its
td = O(N)
td = (N-1)tcarry + tsum
Goa l: Ma ke the fas te s t pos s ible carry pa th circuit
ECE 261
James Morizio
Complimentary Static CMOS Full
Adder
VDD
VDD
Ci
A
Note:
1) S = ABCi + Co(A + B + Ci)
2) Placement of Ci
3) Two inverter stages for
each Co
B
A
B
Ci
A
VDD
X
Ci
Ci
S
Ci
VDD
A
Ci
Co
O(N) delay
28 Transistors
ECE 261
James Morizio
10
Inversion Property
Inverting all inputs results in inverted outputs
A
Ci
FA
Co
Ci
ECE 261
FA
Co
James Morizio
11
Minimize Critical Path by Reducing
Inverting Stages
Even Cell
A1 B1
A0 B0
Ci,0
FA
S0
Co,0
FA
S1
A3 B3
A2 B2
Co,1
FA
Odd Cell
Co,2
S2
Co,3
FA
S3
Exploit Inversion Property
Need two different types of cells, FA: no inverter in carry path
ECE 261
James Morizio
12
A better structure: the Mirror
Adder
VDD
VDD
A
VDD
A
Ci
A
B
Kill
"0"-Propagate
Ci
Co
Ci
S
Ci
"1"-Propagate
Generate
A
Ci
A
B
24 transistors
ECE 261
James Morizio
13
The Mirror Adder
Symmetrical NMOS and PMOS chains
identical rising and falling transitions if the NMOS and PMOS devices are
properly sized.
Maximum of two series transistors in the carry-generation circuitry.
Critical issue: minimization of the capacitance at Co.
Reduction of the diffusion capacitances important.
The capacitance at Co composed of four diffusion capacitances, two
internal gate capacitances, and six gate capacitances in the connecting
adder cell .
Transistors connected to Ci placed closest to output.
Only the transistors in carry stage have to be optimized for
speed. All transistors in the sum stage can be minimal size.
ECE 261
James Morizio
14
NP-CMOS Adder
VDD
VDD
VDD
VDD
S1
Ci1
A1
17 transistors,
ignoring extra
inverters for inputs
and outputs
B1
B1
A1
A1
B1
VD D
VDD
A0
B0
B0
B0
Ci1
A0
B0
A1
B1
Ci2
VDD
A0
Ci1
Ci0
A0
Ci0
S0
Ci0
Carry Path
ECE 261
James Morizio
15
Manchester Carry Chain
VDD
Ci,0
P0
P1
P2
P3
P4
G0
G1
G2
G3
G4
Co,4
Only nMOS transmission gates used. Why?
Delay of long series of pass gates: add buffers
ECE 261
James Morizio
16
Carry-Bypass Adder
P0
G1
Ci,0
P0
G1
Co,0
P0
FA
P2
FA
G2
Co,1
FA
G3
Co,3
FA
G1
Co,0
P3
Co,2
FA
P0 G1
G2
Co,1
FA
Ci,0
P2
P3
G3
BP=P oP1 P2 P3
Co,2
FA
FA
Co,3
Idea: If (P 0 and P 1 and P 2 and P3 = 1)
then Co3 = C 0 , else kill or generate.
ECE 261
James Morizio
17
Manchester-Carry Implementation
P0
P1
P2
P3
BP
Co,3
Ci,0
G0
G1
G2
G3
BP
ECE 261
James Morizio
18
Carry-Bypass Adder (cont.)
Bit 0-3
C i,0
Bit 4-7
Bit 8-11
Bit 12-15
S e tu p
S e tu p
S e tu p
S e tu p
C arry
C arry
C arry
C arry
Propagati on
Sum
Pro pagati on
Propagati on
S um
Sum
Propagati on
Sum
Design N-bit adder using N/M equal length stages
e.g. N = 16, M = 4
What is the critical path?
tp = tsetup + Mtcarry + (N/M-1)tbypass + Mtcarry + tsum , i.e. O(N)
ECE 261
James Morizio
19
Carry Ripple versus Carry Bypass
tp
ripple adder
bypass adder
4..8
ECE 261
N
James Morizio
20
Carry-Select Adder
Generate carry out for both 0 and 1 incoming carries
Setup
P,G
Co,k-1
"0"
"0" Carry Propagation
"1"
"1" Carry Propagation
Multiplexer
4-bit block for bits
k, k+1, k+2, k+3
Co,k+3
Carry Vector
Sum Generation
ECE 261
James Morizio
21
Carry Select Adder: Critical Path
Bit 0-3
Bit 4-7
Setup
"0"
"0" Carry
Setup
"0"
"1" Carry
"1"
"0" Carry
"0"
S0-3
ECE 261
Setup
"1"
Multiplexer
Co,3
Sum Generation
Setup
"0"
"1" Carry
"1"
Ci,0
Bit 12-15
"0" Carry
"1" Carry
Multiplexer
Bit 8-11
"0" Carry
"1" Carry
"1"
Multiplexer
Co,7
Multiplexer
Co,11
Co,15
Sum Generation
Sum Generation
Sum Generation
S4-7
S8-11
S12-15
James Morizio
22
Carry-Select Adder: Linear Configuration
Bit 0-3
Bit 4-7
Setup
Setup
Bit 8-11
Bit 12-15
Setup
Setup
(1)
"0"
"0" Carry
"0"
"0" Carry
"0"
"0" Carry
"0"
"0" Carry
(1)
"1" Carry
"1" Carry
"1"
"1" Carry
"1"
(5)
(5)
Multiplexer
Ci,0
(6)
"1"
(5)
(5)
(7)
Multiplexer
Co,3
Sum Generation
S0-3
"1" Carry
"1"
Multiplexer
Co,7
(8)
(5)
Multiplexer
Co,11
Co,15
Sum Generation
Sum Generation
Sum Generation
S4-7
S8-11
S12-15
Are equal-sized blocks best?
ECE 261
James Morizio
23
Linear Carry Select
Bit 0-3
Bit 4-7
Setup
"0"
"0" Carry
Setup
"0"
"1" Carry
"1"
"0" Carry
"0"
"1" Carry
Ci,0
S0-3
ECE 261
Setup
Setup
"0" Carry
"1"
Multiplexer
"0"
Co,7
Sum Generation
"0" Carry
"1" Carry
"1"
Multiplexer
Co,3
Sum Generation
Bit 12-15
"1" Carry
"1"
Multiplexer
Bit 8-11
Multiplexer
Co,11
Co,15
Sum Generation
Sum Generation
S8-11
S12-15
S4-7
James Morizio
24
Square Root Carry Select
Bit 0-1
Bit 2-4
Bit 5-8
Setup
Setup
Setup
Bit 9-13
Setup
(1)
"0"
"0" Carry
"0"
"0" Carry
"0"
"0" Carry
"0"
"0" Carry
(1)
"1" Carry
"1"
"1" Carry
"1" Carry
"1"
(3)
(3)
Multiplexer
Ci,0
(4)
"1"
(5)
(5)
Co,3
Sum Generation
"1"
(4)
Multiplexer
Multiplexer
Co,7
Sum Generation
"1" Carry
(6)
(6)
Multiplexer
Co,11
Sum Generation
Co,15
Sum Generation
i.e., O(N)
ECE 261
James Morizio
25
Adder Delays - Comparison
50.0
ripple adder
40.0
tp
30.0
linear select
20.0
10.0
0.0
square root select
0.0
20.0
40.0
60.0
ECE 261
James Morizio
26
Carry Look-Ahead - Basic Idea
A0 ,B 0
Ci,0
A1 ,B 1
P0
Ci,1
AN-1 ,BN-1
...
P1
Ci,N-1
PN-1
...
S0
SN-1
S1
Delay independent of the number of bits
ECE 261
James Morizio
27
Carry-Lookahead Adders
High fanin for large N
Implement as CLA slices, or use 2nd level lookahead
generator
4
16-bit CLA based on 4-bit
slices and ripple carry
Faster
implementation
CLA generator
ECE 261
James Morizio
28
Look-Ahead: Topology
VDD
G3
G2
G1
G0
Ci,0
Co,3
P0
P1
P2
P3
Gnd
ECE 261
James Morizio
29
