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Understanding Inverter Threshold Voltage

The document provides an overview of VLSI technology, focusing on the characteristics and functioning of nMOS and CMOS inverters. It explains the inverter threshold voltage (Vth), input-output relationships, and noise margins, emphasizing the importance of noise immunity in digital circuits. Various types of inverters, including resistive load and enhancement/depletion type nMOS inverters, are discussed.

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Dev Nagar
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266 views16 pages

Understanding Inverter Threshold Voltage

The document provides an overview of VLSI technology, focusing on the characteristics and functioning of nMOS and CMOS inverters. It explains the inverter threshold voltage (Vth), input-output relationships, and noise margins, emphasizing the importance of noise immunity in digital circuits. Various types of inverters, including resistive load and enhancement/depletion type nMOS inverters, are discussed.

Uploaded by

Dev Nagar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

VLSI Technology

Prepared by :
Jayesh Diwan
EC Department
VGEC
Introduction

 Using positive logic system , logic ‘1’ represents high voltage and logic ‘0’
represents low voltage.
 The voltage Vth is known as the inverter threshold voltage.

Prepared By : Jayesh Diwan


Introduction

 The voltage Vth is known as the inverter threshold voltage.


 For any input voltage between 0 and Vth = VDD/2, the output voltage is equal to
VDD (logic “1”).
 When input voltage is equal to Vth , the output switches from VDD to 0.
 For any input voltage between Vth and VDD, the output voltage is equal to 0 (logic
‘0’).
 The DC characteristics of actual inverter circuits will differ in various degree from
the ideal characteristics

Prepared By : Jayesh Diwan


nMOS Inverter

Prepared By : Jayesh Diwan


nMOS Inverter
 The input voltage (Vin) of the inverter circuit is gate-to-source voltage (VGS) of
the nMOS transistor.
 The output voltage (Vout) of the circuits is equal to the drain-to-source voltage
(VDS).
 The source and substrate terminals of the nMOS transistor are connected to ground
potential. Hence the source to substrate voltage is VSB = 0.
 In this generalized representation, the load device is represented as a two terminal
circuit element with terminal current IL and terminal Voltage VL.
 One terminal of the load is connected to the drain of the n- channel MOSFET.,
while the other terminal is connected to VDD.
 The characteristics of the inverter circuit depend upon the type and the
characteristics of the load device.
 The output terminal of the inverter shown in figure is connected to the input of
another MOS inverter.
 The next circuit seen by the output node can be represented as a lumped
capacitance, Cout.
 Since the DC gate current of an MOS transistor is negligible, there will be no
current flow into or out of the input and output terminals of the inverter in DC
steady state.

Prepared By : Jayesh Diwan


nMOS Inverter : VTC

Prepared By : Jayesh Diwan


Noise Margin and Noise Immunity

 NMH= VOH – VIH


 NML = VIL - VOL
 The noise Immunity of a digital circuit is defined as ability of a circuit to
reject the noise. The noise immunity of the circuit increases with Noise
Margin.

Prepared By : Jayesh Diwan


Resistive Load Inverter

Prepared By : Jayesh Diwan


Resistive Load Inverter

Prepared By : Jayesh Diwan


Resistive Load Inverter

Prepared By : Jayesh Diwan


nMOS Load Inverter (Enhancement Type)

Prepared By : Jayesh Diwan


nMOS Load Inverter (Depletion Type)

Prepared By : Jayesh Diwan


CMOS Inverter

Prepared By : Jayesh Diwan


CMOS Inverter

Prepared By : Jayesh Diwan


CMOS Inverter

Prepared By : Jayesh Diwan

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