EC 6412 - Linear Integrated Circuits Lab II yr/IV sem

LINEAR INTEGRATED CIRCUITS LABORATORY

BREAD BOARDING TECHNIQUES
1. Do all the wiring with power switched off.
2. Keep wiring and component lead as short as possible.
3. Wire the +V (positive voltage) and V (negative voltage) supply leads to the opamp first.
4. Follow color coding for power supply connections
a. Red

+15V

b. Black

-15V

c. Green

Ground

5. Tie all the grounds to a common point, the power supply ground.
6. Recheck all the wiring before switching on.
7. Connect signal voltage only after power is switched on.
8. Take all measurements with reference to power supply ground.
9. Disconnect signal voltage before switching off power.

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EC 6412 - Linear Integrated Circuits Lab II yr/IV sem

THE FOLLOWING GENERAL PURPOSE LINEAR ICs WILL BE USED IN THE
INTEGRATED CIRCUITS LABORATORY
IC 741
PIN CONFIGURATION

CHARACTERISTICS OF 741 C:
Supply voltage

15 V to 18V

Power dissipation

500mw

Differential input voltage

30V

Normally used supply voltage:

15V

Operating temperature

0 to 70 degree C

Offset voltage

2mV to 6mV

Offset current

20nA to 200nA

Input bias current

80nA to 500nA

Output Voltage swing

14V

Large signal voltage gain

200

Power supply rejection ratio :

10V / V to 150V /V

Common mode rejection ratio:

70 90 dB

Power consumption

50mW to 85mW

Slew rate

0.5 to 0.8 V/V

Unity gain band width

1 MHz

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EC 6412 - Linear Integrated Circuits Lab II yr/IV sem

IC 555 TIMER

CHARACTERISTICS OF NE 555:
Supply voltage

+5V to 16V

Power dissipation

600mW

Operating temperature

0 to 70 oC

Normally used supply voltage

+5V

Control voltage level

+9V to +11V for +15 V supply

+2.6V to +4V for +5V supply

Threshold voltage level

+8.8 V to 11.2V for +15V supply

+2.4 V to +4.2V for +5V supply

Trigger voltage

+4.5V to 5.6V for +15V supply

+1.1V to +2.2V for +5V supply

IC NE 565 PHASE LOCKED LOOP

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EC 6412 - Linear Integrated Circuits Lab II yr/IV sem

-V

No connection

Input

No connection

Input

NE 565

VCO output

No connection
No connection
V+

Phase Comparator VCO output

Reference output

EXTERNAL CAPACITOR FOR VCO

Demodulated output

EXTERNAL RESISTOR FOR VCO

CHARACTERISTICS OF NE 565:
Supply Voltage

6V to 26V

Power dissipation

300mW

Operating temperature

0 to 70 oC

Normally used supply voltage:

6V to 12V
IC 723 VOLTAGE REGULATOR

No connection

No Connection

Current Limit
Current Sense
Inverting Input

Frequency Compensation

723

V+
VC
V OUT

Phase Comparator VCO Input

VZ

1. DESIGN OF INVERTING AND NON INVERTING AMPLIFIER USING IC 741

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EC 6412 - Linear Integrated Circuits Lab II yr/IV sem

AIM:
To design and study the working of inverting and non-inverting amplifier using IC 741.
APPARATUSREQUIRED:
Signal Generator, IC 741, CRO, CRO probes, resistors and connecting wires
CIRCUIT DIAGRAM:

DESIGN EQUATIONS:
Inverting Amplifier: Gain = -Rf/ Ri
Non inverting amplifier: Gain = 1 + Rf/ Ri
DESIGN:
INV-AMP:
GIVEN DATA:GAIN = 10, Ri = 1K
GAIN = -Rf/Ri=>Rf= 10x1K =>Rf= 10K
NON-INV AMP:
GIVEN DATA:GAIN = 11, Ri = 1K
GAIN = 1+Rf/Ri =>11= 1+Rf/1k=>Rf= 10K

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EC 6412 - Linear Integrated Circuits Lab II yr/IV sem

THEORY:
INVERTING AMPLIFIER
The output of an amplifier is inverted as compared to the input signal. The inverted output
means having a phase shift of 1800 as compared to the input signal. The voltage gain depends on the
ratio of two resistances Rf and Ri. If Rf>Ri the gain is greater than 1 and if Rf<Rithe gain will be less
than 1.
NON-INVERTING AMPLIFIER
An amplifier which amplifies the input without producing any phase shift between input and
output is called non-inverting amplifier. The voltage gain is always greater than 1. It can be used as a
buffer for impedance matching.
PROCEDURE:
1. Connect the circuit as per the circuit diagram.
2. Apply an ac signal of amplitude 1V peak to peak at 1 KHz as the input
3. Observe the output wave form. Note the amplitude and frequency of the output waveform.
4. Calculate the theoretical and practical gain and tabulate the results.
5. Repeat the experiment for different values of Rf and Ri.
6. Repeat the entire procedure for non inverting amplifier.
TABULATIONS:
Inverting amplifier:
Vin = 1V p-p
Rf()

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Ri()

Vin (V)

Vout (V)

Theoretical Gain

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Practical
Gain

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EC 6412 - Linear Integrated Circuits Lab II yr/IV sem

Non-inverting amplifier:
Vin = 1V p-p
Rf()

Ri()

Vin (V)

Vout (V)

Theoretical Gain

Practical
Gain

MODEL GRAPH:

VIVA QUESTIONS:
1. What is an Op-amp? Draw
the pin diagram of IC 741.
2. What are the applications
of an op-amp?
3. Define inverting, Noninverting and differential
amplifier.
4. Difference between
inverting and non-inverting amplifier.
5. If the ratio of Rf and Ri is K(constant)in inverting amplifier then the circuit is called as------RESULT:
Thus inverting and non-inverting amplifier was designed and studied and the graph was
obtained.

2. DESIGN OF AN INTEGRATOR AND DIFFERENTIATOR USING IC 741

AIM:
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EC 6412 - Linear Integrated Circuits Lab II yr/IV sem

To design and study an integrator and differentiator using IC 741
APPARATUSREQUIRED:
Signal Generator, IC 741, CRO, CRO probes, resistors, capacitorsand connecting wires
CIRCUIT DIAGRAM:

DESIGN EQUATIONS
fa =1/ 2RfCi
fb = 1/ 2RiCi
fb = 10fa , RiCi = RfCf
DESIGN:
GIVENDATA:fa = 100 Hz , Ci=0.1F
From fa =1/ 2RfCi
100= 1/2Rf x0.1x10-6
=>Rf= 1/2x500 x0.1x10-6= 15.9 K
fb = 10fa= 1KHz
From fb = 1/ 2RiCi
=>Ri = 1/ 2x1x103 x0.1x10-6
=1.59 K
Rcomp=RixRf/ (Ri+Rf) =
1.5K
FromRiCi = RfCf
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EC 6412 - Linear Integrated Circuits Lab II yr/IV sem

Cf =RiCi/Rf
Cf = 1.59x103 x0.1x10-6/ 15.9x103 = 0.01f
THEORY:
INTEGRATOR
A simple low pass RC circuit can also work as an integrator when time constant is very large.
This requires very large values of R and [Link] components R and C cannot be made infinitely large
because of practical limitations. However in the op-amp integrator by MILLERs theorem, the effective
input capacitance becomes Cf (1-Av), where Av is the gain of the op-amp. The gain Av is infinite for an
ideal op-amp, so the effective time constant of the opamp integrator becomes very large which results in
perfect integration.
DIFFERENTIATOR
The circuit performs the mathematical operation of differentiation i.e. the output waveform is the
derivative of the input waveform. The input signal is given to the inverting terminal through a capacitor.
When it is used at high frequencies it may become unstable and break into oscillation because as the
frequency increases gain also increases and the circuit looses stability. In order to overcome this
difficulty practical differentiator are used.
PROCEDURE:
1. Differentiator:
a. Connect the circuit as per the circuit diagram with the designed values
b. Observe the output for various input wave forms ( Sinusoidal and square waveforms for
desired frequencies)
2. Integrator:
a. Connect the circuit as per the circuit diagram with the designed values
b. Observe the output for various input wave forms ( Sinusoidal and square waveforms for
desired frequencies)

TABULATIONS:
INTEGRATOR
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EC 6412 - Linear Integrated Circuits Lab II yr/IV sem

Square Wave
Input
Amplitude
Time (s)
(V)

Sine wave

Output
Amplitude
Time (s)
(V)

Input
Amplitude
Time (s)

Output
Amplitude
Time (s)

(V)

(V)

DIFFERENTIATOR
Square Wave
Input
Amplitude
Time (s)
(V)

Sine wave

Output
Amplitude
Time (s)
(V)

Input
Amplitude
Time (s)

Output
Amplitude
Time (s)

(V)

(V)

MODEL GRAPHS:
Integrator:

Differentiator:

Viva questions:

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EC 6412 - Linear Integrated Circuits Lab II yr/IV sem

1. Define integrator and differentiator.
2. List the types of integrator.
3. Write the applications of integrator and differentiator.
4. What are the disadvantages of differentiator?
RESULT:
Thus integrator and differentiator was designed and the corresponding graph was drawn.

[Link] OF DIFFERENTIAL AND INSTRUMENTAION AMPLIFIER

AIM:
To design an differential and instrumentation amplifier and to study its operation
APPPARATUS:
CRO, potentiometer, resistors and capacitors, IC 741, CRO probes and connecting wires
CIRCUIT DIAGRAM
DIFFERENTIAL AMPLIFIER

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EC 6412 - Linear Integrated Circuits Lab II yr/IV sem

INSTRUMENTATION AMPLIFIER

DESIGN EQUATIONS:
Instrumentation amplifier A = Vout / e2 e1 = ( R4 / R3 ) ( 1 + 2 R2 / R1 )
Differential amplifier Vo = R2/R1 (V2 V1)
DESIGN:
Differential amplifier:
Given data : v1 = 20mv, v2 = 25mv, R1= 1k, R2 = 3.6 k
Vo = R2/R1 (V2 V1) = 3.6 k/1k ( 25x10-3 20x10-3)
= 18mv
Instrumentation amplifier : R1 = 2k, R2 = R3 = 10k, R4 = 22k, e1 = 20mv, e2 = 25mv
Given data : R1 = 2k, R2 = R3 = 10k, R4 = 22k, e1 = 20mv, e2 = 25mv
A = ( R 4 / R3 ) ( 1 + 2 R 2 / R1 )
= (22k/10k)(1+ 20k/2k)
= 24.2
THEORY:
They are used to amplify the low level differential signals very precisely in presence of the large
common mode noise and interference signals. It has finite accurate and stable gain, high input
impedance, low output impedance, high CMRR, high slew rate and low power consumption. The
commonly used instrumentation amplifier is one using 3 op amps. In this circuit a non-inverting
amplifier is added to each of the basic differential amplifier inputs.
Differential amplifier is to amplify the difference between the inputs and the gain is depend on
resistor R2 and R1.
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EC 6412 - Linear Integrated Circuits Lab II yr/IV sem

PROCEDURE: Instrumentation amplifier
1. Connect the circuit as per the circuit diagram
2. Set the inputs e1 and e2 at different values but at the same frequency
3. Calculate the theoretical gain from the given formula and verify with the practical values
PROCEDURE: Differential amplifier
1. Connect the circuit as per the circuit diagram
2. Set the inputs v1 and v2 at different values but at the same frequency
3. Calculate the theoretical gain from the given formula and verify with the practical values

TABULATION:
E1 (V)

E2 (V)

Theoretical gain

Practical gain

v1 (V)

v2 (V)

Theoretical gain

Practical gain

Model Graph:
Differential amplifier

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EC 6412 - Linear Integrated Circuits Lab II yr/IV sem

Vo(volts)

Instrumentation
amplifier

Vo(volts)

Viva questions:
1. What is an

2.
3.
4.
5.

instrumentation amplifier
Give the other name of instrumentation amplifier
Write the requirements of good instrumentation amplifier.
List the applications of instrumentation amplifier.
Specify some application of differential amplifier

RESULT :
Thus instrumentation amplifier and differential amplifierwas designed and studied.
4. ACTIVE LOWPASS, HIGH PASS AND BAND PASS FILTER USING IC 741C
AIM:
To design a first order active low pass, high pass and band pass filter using IC 741
APPARATUSREQUIRED:
Signal Generator, IC 741, CRO, CRO probes, resistors, capacitors and connecting wires
CIRCUIT DIAGRAM:

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EC 6412 - Linear Integrated Circuits Lab II yr/IV sem

HIGH PASS FILTER

DESIGN EQUATIONS:
Low pass filter:
fh= 1 / 2RiC
High pass filter: fl
= 1 / 2 R2C2, Rf = Ri
Band pass filter: Rf = Ri
fh = 1 / 2 R1C1
fl = 1 / 2 R2C2

Design:
LPF:
Given data : Fh = 9Khz, C= 0.01 F
9x103 = 1/2xx Rix 0.01x10-6
Ri = 1.7k
HPF:
Given data : Fl = 1Khz ,C= 0.1 F, Ri = 10k
1 x103= 1/2xx R2x 0.1x10-6
R2 =15.9 K
BPF:Fh = 9Khz, Fl = 1KHz ,C= 0.01 F, Rf=Ri = 10k
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EC 6412 - Linear Integrated Circuits Lab II yr/IV sem

using

fh = 1 / 2 R1C1

9x103 = 1/2xx Rix 0.01x10-6

R1 = 1.7k
Using fl = 1 / 2 R2C2
1 x103= 1/2xx R2x 0.1x10-6
R2 =15.9 K
THEORY:
Afilter is a circuit that is designed to pass a specified band of frequencies. The low pass filter
have a constant gain from a lower cut off frequencies to higher cutoff frequency f h. Hence the
bandwidth of the filter is fh. The circuit allows the range of frequency from 0 to f h, this range is known
as pass band. The range of frequency beyondf his completely attenuated and called as stop
[Link] gain of the filter decreases as the frequency increases and at f= f h the gain is down by
3db.
PROCEDURE:
1. Connect the circuit as per the designed values
2. Give a sinusoidal input of say 1V p-p
3. Vary the input frequency at regular intervals and note down the output response from CRO
4. Plot the frequency response on a semi log sheet
5. Verify the practical and theoretical cut-off frequency
6. Repeat the above procedure for the high and band pass filter.

Tabulations:
Low-pass filter
Vin =1Vp-p
F(Hz)

Vo (V)

A (dB)

Vo (V)

A (dB)

High-pass filter
Vin =1Vp-p
F (Hz)
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EC 6412 - Linear Integrated Circuits Lab II yr/IV sem

Band-pass filter
Vin = 1Vp-p
F (Hz)

Vo (V)

A (dB)

Model graph:
Low Pass Filter

High Pass Filter

Gain
(dB)

Band Pass Filter

Hz

Gain
(dB)

Viva questions:

1. Define filters.
2. Define active
and passive
filters.
3. List the
advantages of
active filters
4. Write the
different types
of filters
5. Draw the ideal and practical characteristics of filter
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Hz

EC 6412 - Linear Integrated Circuits Lab II yr/IV sem

RESULT:
Thus Low pass, High pass and Band pass Filter was designed and corresponding graph was
drawn.
[Link] MULTIVIBRATOR USING IC 741C
AIM:
To design and study an astable multivibrator using IC 741
APPARATUSREQUIRED:
IC 741, CRO, CRO probes, resistors, capacitors and connecting wires
CIRCUIT DIAGRAM:

DESIGN
EQUATIONS:
Total time
period =
2RCln[(1+) /
( 1-)]
= R 2 / R1 + R 2
R1 = 1.16
R2
Design:
Given data :F= 1K, R2 = 10K, C = 0.05 f
R1= 1.16x10k = 11.6k
= R 2 / R1 + R 2
= 10/21.6= 0.46
T=1/f
1/ 1x103=2xRx 0.05x10-6x ln( 1.46/0.54)
R = 10k
THEORY:
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EC 6412 - Linear Integrated Circuits Lab II yr/IV sem

A simple op-amp square wave generator is also called as free running oscillator. The principle
of generation of square wave output is to force an op-amp to operate in the saturation region. A fraction
=R2/(R1+R2) of the output is fed back to the (+) input terminal. The output is also fed to the (-)
terminal after integrating by means of a low pass RC combination in astablemultivibrator. Both the
states are quasistable state. The frequency is determined by the time taken by the capacitor to charge
from- Vsat to+Vsat and vice-versa.
PROCEDURE:
1. Make the connections as per the circuit diagram
2. Observe the output waveform at pin 6 and note the frequency of the waveform
3. Compare the theoretical and practical frequencies
4. Plot the waveforms at pins 6 and 2 (across the capacitor)

Tabulations:
Parameter
Square Wave

Amplitude (V)

Time (s)

Charging and discharging

MODEL GRAPH
Viva questions:
1. Define
multivibrators.
2. Difference
between
Monostable and
Astable
Multivibrators
3. Give the other name of astable multivibrators.
RESULT:
Thus the Astable Multivibrator using IC 741 was designed and the output waveform was
obtained.

6. MONOSTABLE MULTIVIBRATOR USING IC 741

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EC 6412 - Linear Integrated Circuits Lab II yr/IV sem

AIM:
To design and study a monostablemultivibrator using IC 741
APPARATUSREQUIRED:
Signal Generator, IC 741, CRO, CRO probes, resistors, capacitors, IN 4001 diode and
connecting wires

CIRCUIT DIAGRAM:

DESIGN

EQUATIONS:
T = 0.693 Rf C
R1 = 10 R2
DESIGN:
Given data: F = 500 Hz, R2 = 10k, C= 0.01 f
R1 = 100k
T =1/f
Rf= 1/(0.693x500x0.01x10-6)
=289k

THEORY
The diode D1 is clamping the capacitor voltage to 0.7v when the output is at +vsat. The circuit
produces a single pulse of specified duration in response to each external trigger signal. For such a
circuit only one stable state exists. When an external trigger is applied the output changes its stable
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EC 6412 - Linear Integrated Circuits Lab II yr/IV sem

state. The circuit remains in this state for a fixed interval of time. Usually the charging and discharging
of the capacitor provides this internal trigger signal.
PROCEDURE:
1. Connect the circuit as per the circuit diagram
2. Give negative trigger pulse at the input
3. Observe output waveform (one stable state) at pin 6
4. Plot the input and output waveforms.
5. Also plot the waveform across the capacitorC that connected with Rf.

Tabulations:
Parameter
Input

Amplitude (V)

Time (s)

Output at Pin 2
Output at Pin 6
MODEL GRAPH:
RESULT :
Thus the
operation
of
monostable

multivibrator was studied and the graph was drawn.

Viva Questions:
1. Define time constant
2. What is the condition for a multivibrator to operate in monostable mode?
3. What are the applications of Monostable Multivibrator?

7. SCHMITT TRIGGER USING IC741

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EC 6412 - Linear Integrated Circuits Lab II yr/IV sem

AIM:
To study the characteristics of a Schmitt trigger using IC 741
APPARATUSREQUIRED:
Signal Generator, IC 741, CRO, CRO probes, resistors and connecting wires

CIRCUIT DIAGRAM:

DESIGN
EQUATIONS:
Vsat =
12V
VUTP = VLTP =
R1 (Vsat / R1 + R2 )
Design:
Given data : VUTP = 0.5 v , R1 = 1K
FromVUTP= R1 (Vsat / R1 + R2 )
0.5 = 1x103(12/103+R2)
=> R2 =23k
R= R1xR2/(R1+R2)
R = 1k
THEORY:
Schmitt trigger is useful in squaring of slowly varying i/p waveforms. Vin is applied to inverting
terminal of op-amp. Feedback voltage is applied to the non-inverting terminal. LTP (low threshold
point)is the point at which output changes from high level to low level .This is highly useful in
triangular waveform generation, wave shape pulse generator, A/D convertor etc.

PROCEDURE:
[Link] the circuit as per the circuit diagram
[Link] input signal, say, 1V, 1KHz using signal generator
[Link] the input and output waveform.
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EC 6412 - Linear Integrated Circuits Lab II yr/IV sem

[Link] with the theoretical value of LTP and UTP.

Tabulation:
Parameter
Input

Amplitude (V)

Time (s)

Output
MODEL GRAPH:

Viva questions:
1. Define Schmitt
trigger
2. Write the
applications of Schmitt
trigger.
3. Write the type of
Feedback used in
Schmitt trigger(opamp).
RESULT:
Thus the characteristics of Schmitt trigger was studied and the graph was plotted.

[Link] OF AN RC PHASE SHIFT OSCILLATOR USING IC 741

AIM:
To design an RC phase shift oscillator using IC 741.
APPARATUSREQUIRED:
IC 741, CRO, CRO probes, resistors, capacitors and connecting wires
CIRCUIT DIAGRAM:

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EC 6412 - Linear Integrated Circuits Lab II yr/IV sem

DESIGN

EQUATIONS:
fo = 1 / 6 (2 R C )
Rf= 29 Ri, Ri =10 R
DESIGN:
Given data :Fo = 650 Hz, C = 0.1f
From fo = 1 / 6 (2 R C )
650 = 1/ 6 ( 2xxRx 0.1x10-6)
R = 1k
Ri = 10k
Rf = 290 k

THEORY:
Positive feedback of a fraction of output voltage of a amplifier fed to the input in the same
phase, will generate sine wave. The op-amp provides a phase shift of 180 0 degree as it is used in the
inverting mode. An additional phase shift of 180 degree is provided by the feedback RC network. The
frequency of the oscillator fo is given by
fo = 1 / 6 (2 R C )
Also the gain of the inverting op-amp should be atleast 29orRf 29 R1
PROCEDURE:
1. Connect the circuit as per the circuit diagram in the figure
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EC 6412 - Linear Integrated Circuits Lab II yr/IV sem

2. Observe the sinusoidal waveform at the output
3. Verify the frequency of the obtained waveform with the theoretical value
4. Plot the output waveform.

Tabulation:
Parameter

Amplitude (V)

Time (s)

Sine wave
MODEL GRAPH
Vo(volts)

VIVA
QUESTIONS:

1) What are the

two
conditions
necessary for
the
generation of
oscillations?
2) What are the
two types of
RC
oscillators.
3) Give the equation for frequency of oscillation in an op-amp sine wave oscillators
RESULT
Thus the RC phase shift oscillator was designed using IC 741

9. DESIGN OF A WEIN BRIDGE OSCILLATOR USING IC 741

AIM:
To design a wein bridge oscillator for the desired frequency using IC 741
APPARATUSREQUIRED:
IC 741, CRO, CRO probes, resistors, capacitors and connecting wires

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EC 6412 - Linear Integrated Circuits Lab II yr/IV sem

CIRCUIT DIAGRAM:
DESIGN EQUATIONS:
Fo=1/2RC
Rf = 2Rc, Rc = 10R
Design:
Given data : F = 1Khz , C = 0.1f
From Fo=1/2RC
1x103= 1/2xxRx0.1x10-6
R = 1.59 k
Rc = 10*1.59k = 15.9k
Rf = 2*15.9k=31.9k=32k

THEORY
In wein bridge oscillator, wein bridge circuit is connected between the amplifier input and output
terminals. The bridge has series RC network in one arm and parallel RC network in the adjoining arm.
In the remaining two arms of the bridge Rc and Rf are connected. To maintain oscillations total phase
shift around the circuit must be zero and loop gain is unity. The condition of zero phase shift condition
occurs only when the bridge is balanced.
PROCEDURE:
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EC 6412 - Linear Integrated Circuits Lab II yr/IV sem

1.
Connect the circuit as per the circuit diagram
2.

Observe the sinusoidal waveform at the output

3.

Verify the frequency of the obtained waveform with the theoretical value

4.

Plot the output waveform.

Tabulation:
Parameter

Amplitude (V)

Time (s)

Sine wave

MODEL GRAPH

VIVA
QUESTIONS:
1) What is
meant by
oscillator?
2) What is the
use
increasing
the value of
Rf in
oscillatory
circuit?
3) Wein bridge
oscillators not used for high frequency applications why?
RESULT:
Thus the wein bridge oscillator was designed and the corresponding graph was drawn

10. DESIGN OF AN ASTBALE MULTIVIBRATOR USING NE 555 TIMER

AIM:
To design an Astablemultivibrator using NE 555 timer
APPARATUSREQUIRED:
NE 555, CRO, CRO probes, resistors, capacitors and connecting wires

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EC 6412 - Linear Integrated Circuits Lab II yr/IV sem

CIRCUIT DIAGRAM:
DESIGN
84

EQUATIONS:
TOFF= 0.69RB C
TON= 0.69(RB+RA)C
T = TOFF+TON
Design:
Given data: T = 1ms , TON = 0.7 ms, C = 0.1 f
From T = TOFF+TON
TOFF = 1ms-0.7ms
TOFF =0.3ms
From TOFF= 0.69RB C
RB = 0.3x10-3 / 0.69x 0.1x10-6
RB= 4.34K

From TON= 0.69(RB+RA)C

RA+RB = TON/ 0.69xC
RA =(0.7x10-3/0.69x 0.1x10-6)- 4.34x103
RA = 5.84K
THEORY:
The IC555 timer is a 8 pin IC that can be connected with external components for astable
operation. The timing resistor split into two sections RA and RB . Pin 7 of discharging capacitor
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EC 6412 - Linear Integrated Circuits Lab II yr/IV sem

connected at the junction of timing resistors. When Vcc supplied , the capacitor C charge towards Vcc
and output is set high. When the voltage at C equals to 2/3 Vcc upper comparator turn ON and so
output is low. The capacitor starts discharging and when the value equals to 1/3 of Vcc, lower
comparator turn ON and hence capacitor stars charging and output is kept high.
PROCEDURE:
1.

Connect the circuit as per the circuit diagram

2.

Observe the output waveforms at pins 2 and 3

3.

Calculate the duty cycle and frequency of the observed waveform and compare with the
theoretical values.

Tabulation:
Parameter
Square Wave

Amplitude (V)

Time (s)

Charging and discharging

MODEL GRAPH:

VIVA QUESTIONS
1. What are the
applications of astablemultivibrator?
2. Mention the applications of 555 timer
3. Draw the pin diagram of 555 timer.
4. What is the time delay provided by the 555 timer?
5. Define duty cycle?

RESULT:
Thus the astable multivibrator was designed and the required graph was drawn

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EC 6412 - Linear Integrated Circuits Lab II yr/IV sem

[Link] OF A MONOSTABLE MULTIVIBRATOR USING NE 555 TIMER

AIM:
To design a monostable multivibrator using NE 555 timer.
APPARATUSREQUIRED:
NE 555, CRO, CRO probes, resistors, capacitors, IN 4001 diode and connecting wires
CIRCUIT DIAGRAM:

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EC 6412 - Linear Integrated Circuits Lab II yr/IV sem

DESIGN EQUATION:
T = 1.096RC
Design
Given data : C = 1f , T = 1 ms
FromT = 1.096RC
R = 1x10-3/1.096x 1x10-6
R = 1k

THEORY:
In the stand by state flip flop holds transistor Q1 on, thus clamping the external timing circuit C
to ground. The output remains at ground potential low. As the trigger passes through V cc/3, the flip flop
is set. The output goes high. The voltage at C rises exponentially through R towards Vcc with a time
constant RC. As the capacitor reaches voltage that greater the 2/3 Vcc, output turns to stand by mode
that is low state.
PROCEDURE:
1.
Connect the circuit as per the circuit diagram
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EC 6412 - Linear Integrated Circuits Lab II yr/IV sem

2.
Give negative trigger pulse at the input
3.
Observe output waveform ( one stable state) at pins 3 and 6
4.
Plot the input and output waveforms.

Tabulation:
Output pin

Amplitude (V)

Time (s)
Ton

Toff

Pin 3
Pin 6
MODEL GRAPHS:

VIVA QUESTIONS
1.
2.
3.
4.

What is monostable multivibrator?

Mention the applications in monostable mode.
What for the diodes are used in monostable multivibrator?
Define the parameters that decides the time delay

RESULT:
Thus a monostable multivibrator is designed using 555 timer

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EC 6412 - Linear Integrated Circuits Lab II yr/IV sem

12. CHARACTERISTICS OF PHASE LOCKED LOOP NE 565 IC

AIM:
To study the characteristics of IC NE565 PLL and find its lock range and capture range
APPARATUS REQUIRED:
Signal Generator, NE 565, CRO, CRO probes, resistors, capacitors and connecting wires

CIRCUIT DIAGRAM:

10

7
2
6
+6V
3 IC 565 4
9
1 5
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EC 6412 - Linear Integrated Circuits Lab II yr/IV sem

RT

6.8 K

C = 1 F

0.01 F
Demodulated O/p
Reference O/p
VCO O/p (fO)
Function
Generator
(Square
Wave)
Vi= 1v

CT=0.01 f
-6 V

Design Equation:
Free running frequency, f0 = 0.25 / RT CT
Lock range = 7.8 fo/ 12
Capture range = (fL/ 2*3.6*103*C)

Design :
Given data :RT = 6.8 K, CT = 0.01f
From f0= 0.25 / RT CT
= 0.25/ 6.8x103x0.01x10-6
f0 = 3.67kHz
From Lock range = 7.8 fo/ 12
fL = +2.38Khz
From Capture range = (fL/ 2*3.6*103*C)
fc = 105.2Khz
THEORY:
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EC 6412 - Linear Integrated Circuits Lab II yr/IV sem

The PLL consists of 1) phase detector 2) LPF 3) Error amplifier 4) VCO. The phase detector
compares the input frequency fs with the feedback frequency fo and generates an output signal which is
a function of the difference between the phases of the two input signals. The output signal of a phase
detector is a DC voltage. The output of phase detector is applied to the LPF to remove high frequency
white noise. It is the control voltage for VCO when the control voltage is zero VCO is in free running
mode.
PROCEDURE:
1.

Connect the circuit as per the circuit diagram

2.

Measure the free running frequency of IC 565 at pin 4 using CRO without the input
signal from the signal generator or shorting pin2 to ground

3.

Set the input signal, say, 1V, 1KHz to pin2 using signal generator and observe the
waveform on the CRO

4.

Increase the frequency till PLL locked to the input frequency. This frequency is
the lower end of the capture range

5.

Increase frequency further till frequency locks release and this is the
upper end of the lock range

6.

Decrease the frequency till PLL locked to the input frequency. This frequency is
the upper end of the capture range

7.

Decrease frequency further till frequency locks release and this is the
upper end of the lock range
Lock range, fL= f2 f4
capture range, fC= f3 f1
Compare the calculated values with the theoretical values.

Tabulation
Amplitude (V)

Time Period (s)

Parameter
Capture range
Lock range

Frequency (Hz)

VIVA QUESTIONS:
1. What is PLL?
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2. Draw the block diagram of PLL.
3. What are the applications of PLL
4. What is meant by lock range?
5. What is meant by capture range?
RESULT:
Thus the characteristics of PLL was studied and the capture and lock range was identified.

[Link] MULTIPLIER USING PLL 565IC

AIM:
To construct a frequency multiplier using 565 IC
APPARATUS:
Dc power supply, function generator, CRO, potentiometer,
IC 565, IC7490, 2N2222, resistors and capacitors
CIRCUIT DIAGRAM:

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EC 6412 - Linear Integrated Circuits Lab II yr/IV sem

+6v

20kohm C
2kohm 10f
0.001f

RT

C1

vin

8
7

Fo=5fin
VCO Output

565
3

+6v

5
9

0.01f

1
RT
117490
4.7kohm
1
(%5)
2 3 6 7 10
1 10kohm
2N2222
RT
2

10
2

-6v
Design:
Fin = 1 Khz, Vin = 1 v p-p
THEORY
In this technique a divider network is inserted between the VCO output and the phase
comparator input. Since the output of the divider is locked to the input frequency the VCO is actually
running at a multiple of the input frequency. Here a divide by 5 network is used and hence the output
frequency is obtained by frequency multiplication.

PROCEDURE:
1. Make the connections as per the circuit diagram
2. Set the input signal at 1V p-p square wave at 500Hz
3. Vary the frequency by adjusting the 20K potentiometer till the PLL is locked, Measure the
output frequency. Verify the output frequency to be 5 times the input frequency.
4. Repeat the steps 2 and 3 for input frequency of 1 KHz and 1.5KHz.
MODEL GRAPH:

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EC 6412 - Linear Integrated Circuits Lab II yr/IV sem

VIVA QUESTIONS
1. Draw

the

pin

diagram of 565
IC.
2. What is the output
frequency

of

VCO?
3. What is the use of
LPF?
RESULT:
Thus a frequency multiplier was designed and the corresponding graph was drawn.

[Link] REGULATOR USING LM723 & LM317

AIM:
To Design and Construct a low voltage IC regulator (Using IC 723)
APPARATUS REQUIRED:

Dept Of ECE

[Link]
1

Item
IC 723

Specification

2
3
3
4
5

Resistors
Capacitors
R. P. S
Rheostat
Bread Board and
Connecting Wires

100 F / 25 V
(0- 30) V, 1 mA
(0-350 ), 1.5 A

Quantity
2
1
2
1
1

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EC 6412 - Linear Integrated Circuits Lab II yr/IV sem

CIRCUIT DIAGRAM:
VOLTAGE REGULATOR USING LM723

Design: Rsc =
33 , R1 = R2 =
1k , Vin = 1v p-p,
Cref = 0.1f
R3= R1R2/
R1+R2

VOLTAGE
REGULATOR
USING LM317

THEORY:
The input voltage is connected to a transformer. The transformer steps down the ac voltage down
to the level required for the dc output. The rectifier converts ac voltage to dc voltage. The filter circuit is
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EC 6412 - Linear Integrated Circuits Lab II yr/IV sem

used after rectifier to reduce the ripple content in the dc to make it smoother. A regulator is a circuit
used after the filter which not only makes the dc voltage smooth and also keeps the dc output voltage
constant. It keeps the output voltage level constant under varying load conditions. Thus input to a
regulator is a un regulated dc voltage while the output of a regulator is a regulated dc voltage to which
load is connected.

PROCEDURE:
1. Connect the circuit as per the diagram
2. To determine line regulation, measure and record VL for Vin = 10V, 15V, . upto 35V in 5V
increments and readings are tabulated.
TABULATION:
[Link]

Input voltage

Output voltage

VIVA QUESTIONS:
1. What is the function of voltage regulator
2. What are the types of voltage regulator?
3. Draw the pin diagram of 723 IC.
4. Mention the applications of voltage regulator.
RESULT:
Thus the study of voltage regulator was made using 723 IC.

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EC 6412 - Linear Integrated Circuits Lab II yr/IV sem

[Link] OF SMPS

AIM:
To study the control of SMPS.
THEORY:
The switching regulator is also called as switched mode regulator. In this case, the pass
transistor
is used as a controlled switch and is operated at either cutoff or saturated state. Hence the power
transmitted
across the pass device is in discrete pulses rather than as a steady current flow. Greater efficiency is
achieved
since the pass device is operated as a low impedance switch. When the pass device is at cutoff, there is
no
current and dissipated power. Again when the pass device is in saturation, a negligible voltage drop
appears
across it and thus dissipates only a small amount of average power, providing maximum current to the
load. The
efficiency is switched mode power supply is in the range of 70-90%.
A switching power supply is shown in figure. The bridge rectifier and capacitor filters
are connected directly to the ac line to give unregulated dc input. The reference regulator is a series pass
regulator. Its output serves as a power supply voltage for all other circuits. The transistors Q1, Q2 are
alternatively switched on &; off, these transistors are either fully on or cut-off, so they dissipate very
little power. These transistors drive the primary of the main transformer. The secondary is centre tapped
and full wave rectification is achieved by diodes D1 and D2. This unidirectional square wave is next
filtered through a two stage LC filter to produce output voltage Vo.

SG 3524:
FUNCTION:
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EC 6412 - Linear Integrated Circuits Lab II yr/IV sem

Switched Mode Power Supply Control Circuit
FEATURES:
Complete PWM Power Controlled circuitry.
Single ended or push-pull outputs.
Line and Load regulation of 0.2%.
1% maximum temperature variation.
Total Supply current is less than 10mA
Operation beyond 100KHz

RESULT:
Thus the control of SMPS IC SG3524 had been studied.

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EC 6412 - Linear Integrated Circuits Lab II yr/IV sem

LIST OF EXPERIMENTS USING PSPICE:

1. Instrumentation amplifier
2. Low pass and band pass filters
3. Astable multivibrator
4. Monostable multivibrator
5. Schmitt trigger
6. Design of RC phase shift oscillator
7. Design of Wein bridge oscillator
8. Design of an astable multivibrator
9. Design of a monostable multivibrator

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EC 6412 - Linear Integrated Circuits Lab II yr/IV sem

[Link] EXPERIMENTS
AIM:
To design and simulation of the following experiments using PSPICE
1. Instrumentation Amplifier using op-amp
2. Active Lowpass, Highpass and Bandpass Filters using op-amp
3. Astable and Monostable Multivibrators and Schmitt Trigger using p-amp
4. RC Phase Shift and Wein Bridge Oscillators using op-amp
5. Analog multiplier.
6. CMOS inverter, NAND and NOR gate
INTRODUCTION:
It stands for stimulation program with integrated circuit emphasis. It is a general purpose ckt. Program
that stimulate electronic circuits. The various operating points of transistors, time domain response, a
small signal frequency response etc. it contains models of common circuit elements, active as well as
passive and is Capac able of stimulating most electronic circuits.
Modes :
The location of an element is identified by the mode numbers. Each element is connected
between 2 modes. Initially mode numbers are assigned to the circuit. Mode is predefined as ground.
All modes must be connected to at least 2 elts and should therefore appear atleast twice. Node numbers
must be integers from 0 to 9999, but need not be sequential. The node numbers to which an element is
connected are specified after the name of the element.
Symbols of circuit elements:
I diode
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EC 6412 - Linear Integrated Circuits Lab II yr/IV sem

J junction field effect transistor
K transformer (Mutual inductance)
L Inductance.
M Mosfet.
Q Biopolar junction transistor
R resistor.
Example:

R2 2 5 800. It states that the resistor R2 is connected between 2 & 5 and has value 800.

Format of a circuit file:

1. The first line is the title and is may contain and type of text.
2. The last line must be END command
3. The order of remaining lines is not important and does not affect the stimulation effect.
4. A command line may be included any where proceeded by and asterisk*
5. Piecewise statements or commands can be either in uppercase or lowercase (but is adverbials to
type)
6. In spice, symbols are represented without subscripts for example Vs, Is, R 3 are represented as
VC, IS, R3 respective.

PROGRAM:
INSTRUMENTATION AMPLIFIER:

.LIB [Link]
VCC1 4
0
VEE1 0
5
VCC2 9
0
VEE2 0
10
VCC3 14 0
VEE3 0
15
V1 7
0
V2 1
0
R1 3
2
R2 8
6
R3 2
6
oR4 3
11
R5 8
12
RF 11
13
R6 12
0
X1 1
2
Dept Of ECE

DC 15
DC 15
DC 15
DC 15
DC 15
DC 15
SIN(0 5V 100)
SIN(0 3V 100)
1K
1K
1K
1K
1K
1K
1K
4
5
3

UA741

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EC 6412 - Linear Integrated Circuits Lab II yr/IV sem

X2 7
6
X3 12
11
.TRAN 0 20MS
.OP
.PROBE
.END

9
14

10
15

8
13

UA741
UA741

LOWPASS FILTER:

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EC 6412 - Linear Integrated Circuits Lab II yr/IV sem

LOWPASS FILTER:

.LIB [Link]
VCC 5
0
DC
VEE 0
6
DC
VIN 2
0
AC
R1
1
0
22K
R2
1
4
22K
R3
2
3
1.5K
RL
4
0
10K
C1
3
0
0.1U
X1
3
1
5
.AC DEC 10 10 1MEG
.OP
.PROBE
.END

15
15
4

UA741

HIGHPASS FILTER:

.LIB [Link]
VCC 5
0
VEE 0
6
VIN 2
0
R1
1
0
R2
1
4
C1
2
3
RL
4
0
R3
3
0
Dept Of ECE

DC 15
DC 15
AC 4
22K
22K
0.1U
10K
1.5K
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EC 6412 - Linear Integrated Circuits Lab II yr/IV sem

X1
3
1
5
.AC DEC 10 10 100K
.OP
.PROBE
.END

UA741

ACTIVE BANDPASS FILTER:

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EC 6412 - Linear Integrated Circuits Lab II yr/IV sem

BANDPASS FILTER:

.LIB [Link]
VCC 5
0
DC 15
VEE 0
6
DC 15
VCC1 10 0
DC 15
VEE1 0
11
DC 15
VIN 2
0
AC 4
R1
1
0
22K
R2
1
4
22K
R3
3
0
1.5K
R4
4
7
1.5K
R5
8
0
22K
R6
8
9
22K
RL
9
0
10K
C1
2
3
0.1U
C2
7
0
0.01U
X1
3
1
5
6
X2
7
8
10
11
.AC DEC 10 10 10MEG
.OP
.PROBE
.END

4
9

UA741
UA741

ASTABLE MULTIVIBRATOR:

.LIB [Link]
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EC 6412 - Linear Integrated Circuits Lab II yr/IV sem

VCC 4
0
DC 15
VEE 0
5
DC 15
R1
2
0
10K
R2
2
3
11.6K
R3
1
3
50K
C1
1
0
0.01U
X1
2
1
4
5
.TRAN 0 5MS UIC
.OP
.PROBE
.END

UA741

MONOSTABLE MULTIVIBRATOR:

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EC 6412 - Linear Integrated Circuits Lab II yr/IV sem

MONOSTABLE MULTIVIBRATOR:

.LIB [Link]
VCC 6
0
VEE 0
7
VIN 4
0
R1
5
2
R2
2
0
R3
1
5
R4
3
0
C1
4
3
C2
0
1
D1
1
0
D2
2
3
X1
2
1
.TRAN 0 20MS
.OP
.PROBE
.END

DC 15
DC 15
PULSE(4 0 0MS 0.001MS 0.001MS 1MS 2MS)
10K
10K
50K
100
0.1U
0.01U
D1N4148
D1N4148
6
7
5
UA741

SCHMITT TRIGGER:

.[Link]
VCC 5
0
VEE 0
6
VIN 1
0
Dept Of ECE

DC 15
DC 15
SIN(0 4 100)
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EC 6412 - Linear Integrated Circuits Lab II yr/IV sem

R1
3
0
R2
3
4
R3
1
2
RL
4
0
X1
3
2
.TRAN 0 30MS
.OP
.PROBE
.END

10K
100K
10K
10K
5
6

UA741

RC PHASE SHIFT OSCILLATOR:

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EC 6412 - Linear Integrated Circuits Lab II yr/IV sem

RC PHASE SHIFT OSCILLATOR:

.LIB [Link]
VCC 7
0
VEE 0
8
IS
3
0
50US 0MA
R1 1
2
R2 2
4
R3 5
0
R4 6
0
R5 1
0
R6 3
0
C1 5
4
C2 6
5
C3 1
6
X1 3
2
.TRAN 0 1
.OP
.PROBE
.END

DC 15
DC 15
PWL(0US 0MA 10US 0.1MA 40US 0.1MA
10MS 0MA)
33K
1.03MEG
3.3K
3.3K
3.3K
33K
0.1U
0.1U
0.1U
7
8
4
UA741

WEIN BRIDGE OSCILLATOR:

.LIB [Link]
VCC 5
0
Dept Of ECE

DC

15
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EC 6412 - Linear Integrated Circuits Lab II yr/IV sem

VEE 0
6
IS
2
0
50US 0MA
R1 1
0
R2 1
4
R3 2
3
R4 2
0
C1 3
4
C2 2
0
X1 2
1
.TRAN 0 1
.OP
.PROBE
.END

DC 15
PWL(0US 0MA 10US 0.1MA 40US 0.1MA
10MS 0MA)
15K
30.2K
1.5K
1.5K
0.1U
0.1U
5
6
4
UA741

NAND GATE:
PROGRAM:
.LIB [Link]
VDD 5 0 DC 5V
VIN1 2 0 DC 5V PULSE(0 5V 0 1NS 1NS 20US 40US)
VIN2 1 0 DC 5V PULSE(0 5V 0 1NS 1NS 20US 40US)
M1 5 2 3 3 M2SJ143
M2 5 1 3 3 M2SJ143
M3 3 2 4 4 M2SK821
M4 4 1 0 0 M2SK821

.MODEL M2SJ143 PMOS(LEVEL=3 GAMMA=0 DELTA=0 ETA=0 THETA=0 KAPPA=0.2

VMAX=0 XJ=0
+

TOX=2U UO=300 PHI=.6 KP=507.9N W=19 L=2U RS=20M VTO=-1.547

RD=64.85M RDS=6MEG CGSO=4P CGDO=1P CBD=2.168N MJ=.5197 PB=1.199

FC=.5 RG=140.7 IS=1F N=1 RB=10M)

.MODEL M2SK821 NMOS(LEVEL=3 GAMMA=0 DELTA=0 ETA=0 THETA=0 KAPPA=0.2

VMAX=0 XJ=0
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EC 6412 - Linear Integrated Circuits Lab II yr/IV sem

+
TOX=2U UO=600 PHI=.6 KP=1.046U W=5 L=2U RS=20M VTO=3.309
+

RD=.1057 RDS=2.5MEG CGSO=4P CGDO=1P CBD=1.552N MJ=.6463 PB=3

FC=.5 RG=139.3 IS=1F N=1 RB=10M)

.TRAN 0US 1MS UIC

.DC VIN1 0V 5V 1V
.PROBE
.OP
.END

NOR:
PROGRAM:
.LIB [Link]
VDD 1 0 DC 5V
VIN1 2 0 DC 5V PULSE(0 5V 0 1NS 1NS 20US 40US)
VIN2 3 0 DC 5V PULSE(0 5V 0 1NS 1NS
20US 40US) M1 1 2 4 4 M2SJ143
M2 4 3 5 5 M2SJ143
M3 5 2 0 0 M2SK821
M4 5 3 0 0 M2SK821
.MODEL M2SJ143 PMOS(LEVEL=3 GAMMA=0 DELTA=0 ETA=0 THETA=0 KAPPA=0.2
VMAX=0 XJ=0
+

TOX=2U UO=300 PHI=.6 KP=507.9N W=19 L=2U RS=20M VTO=-1.547

RD=64.85M RDS=6MEG CGSO=4P CGDO=1P CBD=2.168N MJ=.5197 PB=1.199

FC=.5 RG=140.7 IS=1F N=1 RB=10M)

.MODEL M2SK821 NMOS(LEVEL=3 GAMMA=0 DELTA=0 ETA=0 THETA=0 KAPPA=0.2

VMAX=0 XJ=0
+

TOX=2U UO=600 PHI=.6 KP=1.046U W=5 L=2U RS=20M VTO=3.309

RD=.1057 RDS=2.5MEG CGSO=4P CGDO=1P CBD=1.552N MJ=.6463 PB=3

FC=.5 RG=139.3 IS=1F N=1 RB=10M)

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EC 6412 - Linear Integrated Circuits Lab II yr/IV sem

.TRAN 0US 1MS UIC

.DC VIN1 0V 5V 1V
.PROBE
.OP
.END

CMOS INVERTER:
PROGRAM:
.LIB [Link]
VDD 2 0 DC 5V
VIN 1 0 DC 5V PULSE(0 5V 0 1NS 1NS 20US 40US)
RL 3 0 100K
M1 2 1 3 3 M2SJ143
LIC LAB MANUAL
.MODEL M2SJ143 PMOS(LEVEL=3 GAMMA=0 DELTA=0 ETA=0 THETA=0 KAPPA=0.2
VMAX=0
XJ=0
+

TOX=2U UO=300 PHI=.6 KP=507.9N W=19 L=2U RS=20M VTO=-1.547

RD=64.85M RDS=6MEG CGSO=4P CGDO=1P CBD=2.168N MJ=.5197 PB=1.199

FC=.5 RG=140.7 IS=1F N=1 RB=10M)

M2 3 1 0 0 M2SK821
.MODEL M2SK821 NMOS(LEVEL=3 GAMMA=0 DELTA=0 ETA=0 THETA=0 KAPPA=0.2
VMAX=0
XJ=0
+

TOX=2U UO=600 PHI=.6 KP=1.046U W=5 L=2U RS=20M VTO=3.309

RD=.1057 RDS=2.5MEG CGSO=4P CGDO=1P CBD=1.552N MJ=.6463 PB=3

FC=.5 RG=139.3 IS=1F N=1 RB=10M)

.DC VIN 0V 5V 1V
.PROBE
Dept Of ECE

EASWARI ENGINEERING COLLEGE

Page 56

EC 6412 - Linear Integrated Circuits Lab II yr/IV sem

.OP
.END

RESULT
Thus the program can be executed by using PSPICE software.

Dept Of ECE

EASWARI ENGINEERING COLLEGE

Page 57