SOC Testing
SOC Test Problems/requirements
IEEE P1500 Standard
SOC Test Methodology
Testable SOC Design Flow
Conclusions
SOC testing.1
SOC Test Problems
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Deeply embedded cores
More, higher-performance core pins than SOC pins
External ATE inefficiency
Mixing technologies: logic, processor, memory,
analog components
Multiple hardware description levels for cores
Different core providers and SOC test developers
Core/test reuse
Hierarchical core reuse
IP protection
SOC testing.2
SOC Test Requirements
! Deeply embedded cores
Need Test Access Mechanism
! More, higher-performance core pins than SOC pins
Need on-chip, at-speed testing
! External ATE inefficiency
Need on-chip ATE
! Mixing technologies: logic, processor, memory,
analog components
Need various DFT/BIST/ techniques
SOC testing.3
SOC Test Requirements (cont.)
! Multiple hardware description level for cores
Need to insert DFT/BIST at various levels
! Different core providers and SOC test developers
Need standard for test integration
! Core/test reuse
Need plug-and-play test mechanism
! Hierarchical core reuse
Need hierarchical test management
! IP protection
Need core test standard/document
SOC testing.4
Core Test Techniques
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Single scan
Multiple scan
Broadcast scan
Enabled ATPG Scan insertion
Reusable ATPG Access & isolation
Test point insertion
Shadow register
Enabled BIST Scan, test points
Embedded BIST Serial or parallel, local
controller, TPG and SA
! Boundary scan (BS)
SOC testing.5
Component test
! DSP/CPU cores: BS supporting BIST, Scan, test
point, shadow register.
! ASIC cores: BIST, Scan, shadow register, w/wo
BS.
! Memory: Embedded BIST
! Analog: Test points, DSP, BIST, ad hoc
SOC testing.6
IEEE P1500
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Goals
Task Force
Basic Principles
Overall Architecture
Core Test Requirement / Architecture
Wrapper Register Function / Configuration
Wrapper Cells
SOC testing.7
Goals of IEEE P1500
Standardize a Core Test Architecture which:
! Defines a core test interface between an
embedded core and the system chip.
! Facilitate test reuse for embedded cores through
core access and isolation mechanisms
! Provide testability for system chip interconnect
and logic.
! Facilitates core test interoperability, with plugand-play protocols, to improve the efficiency of
test .
SOC testing.8
Active Task Force for P1500
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Advantest
ASC
[Link]
HP
IBM
Intellitech
LogicVision
Mentor Graphics
Motorola
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Nortel
Palmchip
Philips
Sisco Systems
Sonic
Synopsys
TI
Veritable
SOC testing.9
Basic Principles
! Embedded core test requires the following
hardware components:
A Wrapper (around the core)
A Source/Sink for test patterns (on or off-chip)
An on-chip Test Access Mechanism (TAM) to connect
the Wrapper to the Source/Sink.
! Faciliate test reuse for "non-merged cores.
! Define the behavior of a standard Wrapper per
core and its interface with a Test Access
Mechanism (TAM).
SOC testing.10
Current Proposed P1500 Overall
Architecture
fro m S o u rc e
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po
pi
P 1 5 0 0 W ra p p e r
fu n c t.
in p u t
to S in k
U se r-D e fin e d P a ra lle l TA M
C o re 1
P 1 5 0 0 W ra p p e r
fu n c t.
o u tp u t
W IR
fu n c t.
in p u t
...
so
si
po
...
C o re N
si
fu n c t.
o u tp u t
so
W IR
wc
s e ria l TA M
U se r-D e fin e d
Te s t C on tro lle r
s e ria l TA M
S y s te m C h ip
SOC testing.11
Basic Principles (cont.)
! Core test wrapper modes:
Core Normal Mode
Core Test Mode (internal)
Core Interconnect Test Mode (external)
Core Isolation Mode
! The standard Wrapper behavior may be:
Implemented and provided by core vendors
Added to the core during a subsequent design stage. It
is assumed that EDA vendors will:
! offer tools to implement the standard Wrappers
! check for compliance
! provide system-chip level optimization.
SOC testing.12
Basic Principles (cont.)
! Should standardize the interface between the
Wrapper and Test Access Mechanism, but not the
Test Access Mechanism itself of the system-chip.
! Will define how both 1149.1 & non-1149.1 cores
can co-operate during test.
! Should specify the standard Wrapper and the
interface to the Test Access Mechanism using the
P1500 Core Test Language (CTL).
! Should be applicable to hierarchical cores.
SOC testing.13
A P1500-wrapped Core
C ore
SOC testing.14
P1500 Architecture Components
TAM-In TAM-Out
Wrapper
Wrapper
Cells
Core
Wrapper
Instruction
Registr
Wrapper
Bypass
Register
Serial
Output
Serial
Input
Serial Control
" A P1500 wrapper contains the following:
A wrapper Instruction Register for providing wrapper mode control
Wrapper Cells to provide test functions at the core terminals
An optional Bypass register for a single bit scan bypass through
the wrapper
A serial interface for providing initialization and communication to
the Wrapper Instruction Register,Wrapper Cells,and Bypass
register
SOC testing.15
Required Modes for Embedded Core Test
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Core Normal Mode
Wrapper is transparent, core functions normally
Core Test Access Mode
Core wrapper provides for controlling core inputs and
observing core outputs during core test application.
Test Access Mechanisms (e.g., Test Bus, Test Rail, ...Other)
configured during System Chip integration.
Interconnect & UDL Test Access Mode
Core wrapper provides test observation at core inputs and
control at core outputs.
Test Isolation Mode
Not always required for every core or in every application
Can be achieved by constraining core inputs/outputs
Protects core and system chip from damage
Useful for reducing power consumption, and for Iddq testing
SOC testing.16
Test Function at Core Terminals
! Input test functions
Input observation: for observation of external
signal
Input control: for applying test to core input
Input constraint: to fix logic at core input
! Output test functions
Output observation: for observation of internal
core
Output control: for interconnect test
Output constraint: to fix logic at non-tristate output
Output disable: for tristate driver
SOC testing.17
Serial
Control
Selected
Wrapper
Register
Shift
Serial
Output
Update
Serial
Input
Capture
Scan Protocol Behavior of Wrapper Registers
Standard P1500 protocol for Wrapper Register will provide for:
Parallel capture of input data into the selected register
Serial shift of the register from serial input to serial output
Update scan-in data of register to a parallel update stage
SOC testing.18
Standard Serial Scan Path Configuration
Serial
Input
WIR
DR
MUX
Bypass
MUX
Wrapper Cell Register
Serial
Output
Serial Control
" Serial control lines enable & perform scan , and select between:
Wrapper instruction register (WIR)
Or other data registers (DRs), e.g. Wrapper cell
register,bypass,etc.
" Updated WIR then selects between DRs
" Core test 1-N instructions permit TAM connection & configuration
of Wrapper DRs,or internal core registers,to be user defined!
SOC testing.19
P1500 Wrapper Connection
P1500 Wrapper
JTAG Wrapper
Wrapper Cell
Register
Bypass
Serial
Input
Wrapper Cell
Register
m
u
x
Bypass
m
u
x
WIR
m
u
x
WIR
m
u
x
Serial
Output
TAP
P1500 Control Protocol
JTAG Protocol
Wrapper Control Interface
Wrapper Control Interface is configured by system chip integrator
P1500 & JTAG inter-operate at wrapper & serial data interfaces
SOC testing.20
Wrapper Cell Example--Dedicated Output
Cell with Update Stage & TAM-Out
SO
Core
Output
Terminal
TAM-Out
Cell Input Wrapper Cell Output
Output
Cell
Instruction &
Serial Controls
Wrapper
Output
Terminal
SI
Cell behavior for Wrapper Scan Protocol
" Captures data at cell input
" Shifts data from scan input (SI) to scan
output (SO)
" Updates shift stage data to update stage
SOC testing.21
P1500 Wrapper Cell Example -Dedicated Output Cell with Update Stage & TAM-In
TAM-In
SO
Wrapper
Core
Wrapper
Cell
Input
Input
Input
Input
Terminal
Cell Cell Output Terminal
Instruction &
Serial Controls
SI
Cell behavior for Wrapper Scan Protocol
" Captures data at cell input
" Shifts data from scan input (SI) to scan output
(SO)
" Updates shift stage data to update stage
SOC testing.22
TAM Connection Example-Core with Parallel Internal Scan
Wrapper
Wrapper
Cells
Core
Logic
TAM-Out
TAM-In
Serial Input
WIR
Serial
Output
Serial
Control
! Core internal scan path & Wrapper Cell Register are
connected in parallel to TAM by a Core Test instruction
! Many other TAM connections and configurations are possible!
SOC testing.23
SOC Test Methodology
! Study functions and architectures in each
module of a general SOC
! Design each module
! Apply proper testing methods to each module
! Add wrapper to each core (module)
! Integrate the IP testing using a P-1500 like
structures
SOC testing.24
Development of Testable SOC
# Testing for digital components
# Testing for analog components
# Testing for memory components
# Wrapper for each core
# Define Test Access Mechanism
# Test integration
# Testable design flow
SOC testing.25
SOC Testable Design Flow
D e s ig n R e q u ire m e n t/
T e s t R e q u ire m e n t
P 1 5 0 0 R e a d y C o re ?
S ys te m A rc h ite c tu re
P 1 5 0 0 C o m p lia n c e C h e c k e r/
A d d W ra p p e r
S ys te m P a rtitio n a n d IP
S u rve y
UDL
B e h a vio r / R T L / G a te L e ve l
S O C T e s ta b le D e s ig n R u le s
U D L D F T In s e rtio n
T e s t R e q u ire m e n t
S ys te m In te g ra tio n
T e s t In te g ra tio n
S ys te m S p e c ific a tio n
V e rific a tio n
T e s t A c c e s s m e c h a n is m
S yn th e s is
T e s t C o n tro lle r S yn th e s is
T e s t B e n c h In te g ra tio n
T e s t B e n c h V e rific a tio n /
Ille g a l T e s t P a tte rn C h e c k e r
SOC testing.26
Conclusions
! SOC testing is a must
! Standard not defined yet
! Even standard is defined, many details need to be
implemented
! Component testing needs to consider test reuse
! Automation of wrapper generation & system chip
interface must be done
! Tools for linking design flow
! Test access mechanism is to be user-defined,
hence test engineer will not lost job
! Mixed-mode testing in SOC is urgent
SOC testing.27
