Common Power Format

Tutorial

December 6, 2007

Qi Wang
Cadence Design Systems, Inc.
LPC Architect, LPC, Si2

Innovation Through Collaboration

Outline
Where Was It Started?
CPF Basics
Digest CPF Using A Simple Example
CPF Based Low Power Design Flow
Where Is CPF Headed?

Innovation Through Collaboration Low Power Coalition

Low Power Design Without A Power Format

Domains
Level shifters
Isolation
SRPG

Domains

Command file
Domains
Level shifters
Isolation
SRPG

Constraint
Generation
Synthesis

Design for Test

SVP

Iterate

RTL
Coding

Constraints
Command file

Simulation

Acceleration
& Emulation

Netlist

Chip Integration
Prototyping

Sign-off

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GDSII

ATPG

Routing

Command file
Analysis

Physical Synthesis

DFT

Domains
Level shifters
Isolation
SRPG

Equivalence LVS/DRC/Ext
checking

Which one of
these is golden? Command file

Formal
Analysis

Physical Implementation
Constraint Validation

Domains
Level shifters
Isolation
SRPG

How do you verify

power functionality
without changing RTL?

Verification

Iterate

Constraint Validation

Command file

Design Creation
Equivalence Checking

Domains
Level shifters
Isolation
SRPG

?
Verification Coverage

Command file

MSV
SRPG
PSO
DVFS

Specification
Function, timing, power

Testbench Automation

Command file

Domains
Modes for ATPG

Does the power

shutoff really going to
work?
3

What Was the Problem?

Logic is Connected

Power is Not Connected

Formal
Analysis

Simulation

Hardware

Formal
Analysis

Simulation

Hardware

Parser

Parser

Parser

Parser

Parser

Parser

Synthesis

Management

Synthesis

Parser

Parser

Parser

Parser

Equivalence
Checking

(Verilog)

Parser

P+R

IP

SVP

Power
Power
Information
Information

(CPF)
(no consistency)

Parser
Test

Libraries

Can be Automated
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Equivalence
Checking
Parser

Parser

Parser

Parser

Logic
Information

Parser

SVP

Parser

Management

P+R

IP

Test

Libraries

Very Difficult to Automate

4

Common Power Format (CPF)

Single file format to automate low power holistically
Power is Connected
Formal
Analysis

Simulation

Hardware

Parser

Parser

Parser

Management

Synthesis

Parser

Parser

Parser

SVP

Power
Information
(CPF)

Parser

Parser

Parser

Equivalence
Checking

P+R

IP

Test

Libraries

Is Automated
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Rallying Industry Support

System
Semi

A new method of
capturing design
and constraint
information

IP
De

n
io
t
a
c
i
f
ri
e
V

n
sig

CPF

Libs

EDA

Facilitates holistic
methodology across
design, verification,
and implementation

Implementation
Mfg

Equip

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Enables automation and

what-if exploration
6

Common Power Format Progress

2005

Q22006

CPF
V 0.8

CPF
V 0.5

CPF
V 0.0

300
Man
Years

Q32006

> 400 Inputs

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Q42006
CPF
V 1.0

~ 100 Inputs

Si2 CPF Standardization

Dec 4, 2006

Cadence contributed CPF v1.0 to Si2

January 12, 2007

LPC members unanimously voted and

approved CPF v1.0 as Si2 Specification for
low power standard

January 17, 2007

Cadence contributed CPF v1.0 parser source

code to Si2

March 5, 2007

CPF 1.0 available to everyone at no cost as a

Si2 standard

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Outline
Where Was It Started?
CPF Basics
Digest CPF Using A Simple Example
CPF Based Low Power Design Flow
Where Is CPF Headed?

Innovation Through Collaboration Low Power Coalition

Common Power File

ASCII file to capture
Design intent and constraints

Power domain

Logical: instances as domain members

Physical: power/ground nets and connectivity

Analysis view: timing library sets for power domains

Power Logic

Level Shifter Logic

Isolation Logic

State-Retention logic

Switch Logic & Control Signals

Power mode

Mode definitions

Mode transition definitions

Technology information

Level Shifter Cells, Isolation Cells, State-Retention Cells, Switch Cells, Always On Cells

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CPF Language
CPF is TCL-based.
CPF Language = TCL commands + CPF objects + Design objects

Power domain

Analysis view

Delay corner

Library set

Operating condition

Design objects: objects that already exist in the RTL/gate netlist

Module, Instance, Net, Pin, Port

Commands 42 commands

set_* commands [version, scope, and general commands]

define_*_cell commands

[library cell description]

create_*_rule commands

[design intent]

update_*_rules commands

[implementation directives]

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Minimal Command Set For Different Design Stages

create_power_domain
create_nominal_condition
create_power_mode
create_state_retention_rule

Specify power intents

verification and simulation
design exploration
early power estimation

create_isolation_rule
create_level_shifter_rule
define_library_set
update_nominal_condition
update_power_mode

More implementation details

synthesis
formal verification
DFT, ATPG,
gate level power estimation

create_ground_nets
create_power_nets
update_power_domain
create_power_switch_rule
create_analysis_view
create_operating_corner

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Complete physical implementation

details
silicon virtual prototyping
power planning
physical synthesis
structural verification
sign-off power analysis
12

Outline
Where Was It Started?
CPF Basics
Digest CPF Using A Simple Example
CPF Based Low Power Design Flow
Where Is CPF Headed?

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13

Nano CPU
32 bit RISC processor

5 power domains with 4 independent switchable domains

2 supply voltages: simple DVFS

Clock
Control
Address

CPU Control Bus

I/O
controller

Program Counter

Address register

State
Sequencer

Address Bus

Power
Control
Unit

Always ON power
domain

ALU
Instruction register

Data IN

Data-in register

Arithmetic Unit

Register
file

Logical Unit
Power
Control Bus

Data OUT

Data-out register

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Switched power domains

Data Bus

14

Set Up Power Domains

create_power_domain -name PDcore -default

create_power_domain -name PDau -instances alu_inst/aui \
-shutoff_condition pcu_inst/pau[2]
create_power_domain -name PDlu -instances alu_inst/lui \
-shutoff_condition pcu_inst/plu[2]
create_power_domain -name PDalu -instances alu_inst \
-shutoff_condition pcu_inst/palu[2]
create_power_domain -name PDrf -instances rf_inst \
-shutoff_condition pcu_inst/prf[2]
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Complete create_power_domain Command

create_power_domain
-name power_domain
{ -default [-instances instance_list] [-boundary_ports pin_list]
| -instances instance_list [-boundary_ports pin_list]
| -boundary_ports pin_list }
[ -shutoff_condition expression ]
[ -default_restore_edge expression ] [ -default_save_edge expression ]
[ -power_up_states {high|low|random} ]
Power domain definition
Pure abstract model of a power domain at RTL
Power domain inheritance and precedence
Default power domain concept
Wildcard characters are allowed for design objects

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Specify Power Logic: Retention Strategy

create_state_retention_rule name sr_rule domain PDrf \

-restore_edge { !pcu_inst/prf[1] }

Single control for state retention

pcr_inst/prf[1] going high starts the retention mode

pcr_inst/prf[1] going low ends the retention mode with
saved data restored to the flop output

All registers and only registers in power domain PDrf are

modeled as retention registers

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Complete create_state_retention_rule Command

create_state_retention_rule -name string
{ -domain power_domain | -instances instance_list }
[-restore_edge expression [ -save_edge expression ]]

For RTL verification tools, the command models a retention cell behavior at RTL

The register need to have save signal come before its parent power domain is switched off
The register will restore the saved value after the parent domain is switched on again when there
restore signal comes

For Implementation tools, the command specifies a list of registers to be mapped into

retention cells.
The option instances takes a list of RTL register names

There are other commands to specify the format of mapping RTL register names into gate level
flops names so the same CPF file can be used by both RTL and post RTL tools

Wildcard characters are allowed for design objects

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Specify Power Logic: Isolation Strategy

create_isolation_rule -name iso_rule1 -from PDau \

-isolation_condition {!pcu_inst/pau[0]} -isolation_output low
create_isolation_rule -name iso_rule2 -from PDlu \
-isolation_condition {!pcu_inst/plu[0]} -isolation_output high
create_isolation_rule -name iso_rule3 -from PDalu \
-isolation_condition {!pcu_inst/palu[0]} -isolation_output low
create_isolation_rule -name iso_rule4 -from PDrf \
-isolation_condition {!pcu_inst/prf[0]} -isolation_output low

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Complete create_isolation_rule Command

create_isolation_rule -name string -isolation_condition expression
{-pins pin_list | -from power_domain_list | -to power_domain_list}...
[-isolation_target {from|to}] [-isolation_output {high|low|hold}]
[-exclude pin_list]
It specifies a list of signals require isolation when the driving or receiving power domains of

these signals are switched off

-pins/-from/-to/-exclude are filters for selecting the signals

-isolation_condition specifies under what condition the isolation rule is activated

For RTL verification tool, this is the condition when the behavior specified by isolation_output
should be imposed to the normal functional behavior
For implementation tool, isolation condition should be synthesized to drive the enable pin of the
special isolation cell

In most cases, isolation is needed when the driver of a signal is switched off but the

receivers of the signal are still on. In some cases, isolation may be required when the
driver signal is on but the receivers of the signal are off.

-isolation_target specifies which power domain is switched off when this rule is activated

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Power Modes

PDcore

PDau

PDlu

PDalu

PDrf

PM1

1.2v

1.2v

1.2v

1.2v

1.2v

PM2

0.8v

off

1.2v

1.2v

1.2v

PM3

0.8v

off

off

off

1.2

PM4

0.8v

1.2v

1.2v

1.2v

off

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Specify Power Modes

PDcore

PDau

PDlu

PDalu

PDrf

PM1

1.2v

1.2v

1.2v

1.2v

1.2v

PM2

0.8v

off

1.2v

1.2v

1.2v

PM3

0.8v

off

off

off

1.2

PM4

0.8v

1.2v

1.2v

1.2v

off

create_nominal_condition -name high -voltage 1.20

create_nominal_condition -name low -voltage 0.8
create_power_mode -name PM1 default \
-domain_conditions {PDcore@high PDau@high PDlu@high PDalu@high PDrf@high}
create_power_mode -name PM2 \
-domain_conditions {PDcore@low

PDlu@high PDalu@high PDrf@high}

create_power_mode -name PM3 \

-domain_conditions {PDcore@low

PDrf@high}

create_power_mode -name PM4 \

-domain_conditions {PDcore@low PDau@high PDlu@high PDalu@high

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Complete create_power_mode Command

create_nominal_condition name string voltage float
create_power_mode

-name string [-default]

-domain_conditions domain_condition_list

The create_power_mode commands specify a list of valid operating modes for a design
Each mode include the operating conditions for each power domain

off or on

if on at what voltage

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Specify Power Mode Transitions

PM2
PDcore

PDau

PDlu

PDalu

PDrf

PM1

1.2v

1.2v

1.2v

1.2v

1.2v

PM2

0.8v

off

1.2v

1.2v

1.2v

PM3

0.8v

off

off

off

1.2

PM4

0.8v

1.2v

1.2v

1.2v

off

PM1

PM3
PM4

create_mode_transition -name PM1toPM2 from_mode PM1 to_mode PM2 \

-start_condition { pcu_inst/ctrl[0] & pcu_inst/ctrl[1] }
-clock_pin { pcu_inst/clk } cycles 100
create_mode_transition -name PM2toPM3 from_mode PM2 to_mode PM3 \
-start_condition { pcu_inst/ctrl[0] & !pcu_inst/ctrl[1] }
-clock_pin { pcu_inst/clk } cycles 1000
create_mode_transition -name PM3toPM4 from_mode PM2 to_mode PM3 \
-start_condition { !pcu_inst/ctrl[0] & pcu_inst/ctrl[1] }
-clock_pin { pcu_inst/clk } cycles 1000
create_mode_transition -name PM4toPM1 from_mode PM2 to_mode PM3 \
-start_condition { !pcu_inst/ctrl[0] & !pcu_inst/ctrl[1] }
-clock_pin { pcu_inst/clk } cycles 200
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Complete create_mode_transition Command

create_mode_transition -name string
-from_mode power_mode -to_mode power_mode
-start_condition expression [-end_condition expression]
[-clock_pin clock_pin [-cycles number | -latency float]]
Specify a single mode transition
Each mode transition involves a series of power domain changes
The start condition and end condition can be used by verification tools to trace the mode

transition and record coverage on modes and mode transitions

The transition time can be used to simulate the latency of each mode transition

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Put Everything Together For Design Specification

set_design nano_cpu
create_power_domain -name PDcore -default
create_power_domain -name PDau -instances alu_inst/aui -shutoff_condition pcu_inst/pau[2]
create_power_domain -name PDlu -instances alu_inst/lui -shutoff_condition pcu_inst/plu[2]
create_power_domain -name PDalu -instances alu_inst -shutoff_condition pcu_inst/palu[2]
create_power_domain -name PDrf -instances rf_inst -shutoff_condition pcu_inst/prf[2]
create_state_retention_rule name sr_rule domain PDrf -restore_edge { ! pcu_inst/prf[1] }
create_isolation_rule -name iso_rule1 -from PDau -isolation_condition {!pcu_inst/pau[0]} -isolation_output low
create_isolation_rule -name iso_rule2 -from PDlu -isolation_condition {!pcu_inst/plu[0]} -isolation_output low
create_isolation_rule -name iso_rule3 -from PDalu -isolation_condition {!pcu_inst/palu[0]} -isolation_output low
create_isolation_rule -name iso_rule4 -from PDrf -isolation_condition {!pcu_inst/prf[0]} -isolation_output low
create_nominal_condition -name high -voltage 1.20
create_nominal_condition -name low -voltage 0.8
create_power_mode -name PM1 \
default -domain_conditions {PDcore@high PDau@high PDlu@high PDalu@high PDrf@high}
create_power_mode -name PM2 -domain_conditions {PDcore@low PDlu@high PDalu@high PDrf@high}
create_power_mode -name PM3 -domain_conditions {PDcore@low PDrf@high}
create_power_mode -name PM4 -domain_conditions {PDcore@low PDau@high PDlu@high PDalu@high }
end_design

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26

Low Power Design Verification Using CPF

No need to specify power or ground nets at RTL stage
No need to specify implementation related constraints at this stage such

as library, timing constraints etc

Minimal set of CPF commands for front-end designers to use

Simulation tools

to simulation power domain on and off

to simulate power mode transitions for DVFS

Coverage tools

to check power mode coverage

to check power mode transition coverage

Assertion tools

to generate power domain and mode aware assertions

Verification tools

to check for the correctness and completeness of CPF

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What About Implementation?

For synthesis

Need to specify the libraries

Need to link the libraries to each power domain in each power mode

Need to associate timing constraints for each power mode to perform DVFS synthesis

For physical implementation and verification

Need to specify power and ground net work

Need to specify how power switch network should be implemented

Additional CPF commands are needed

update_nominal_condition

update_power_domain

update_power_mode

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Specify Technology Libraries And Special Low Power Cells

#Libraries for implementation, file name tech.cpf
set libdir ../../../libs
set 08v_list "$libdir/130e_sp_tt_0p8v_25c.lib "
set 120v_list "$libdir/13sp_tt_0p8v_1p2v_25c.lib "
define_library_set -name 08v -libraries $08v_list
define_library_set -name 120v -libraries $120v_list
define_level_shifter_cell -cells LVLHLEHX* -input_voltage_range 1.2 \
-output_voltage_range 0.8 -direction down valid_location to
define_level_shifter_cell -cells LVLHLX* -input_voltage_range 1.2 \
-output_voltage_range 0.8 -direction down valid_location to
define_level_shifter_cell -cells LVLLHEHX* -input_voltage_range 0.8 \
-output_voltage_range 1.2 -direction up valid_location to
define_level_shifter_cell -cells LVLLHX* -input_voltage_range 0.8 \
-output_voltage_range 1.2 -direction up valid_location to
define_isolation_cell -cells ISOLN* -enable EN -valid_location from
define_isolation_cell -cells "LVLHLEHX* LVLLHEHX* LVLHLELX*" -enable EN
define_always_on_cell -cells "BUFGX2M BUFGX8M INVGX2M INVGX8M"
define_state_retention_cell -cells *DRFF* -restore_function RETN
define_power_switch_cell -cells "HEAD8DM HEAD16DM HEAD32DM HEAD64DM ground VSS \
-power_switchable VDD -power VDDG stage_1_enable SLEEP stage_1_out SLEEPOUT type header

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Link Technology Libraries And Timing Constraints

PDcore

PDau

PDlu

PDalu

PDrf

PM1

1.2v

1.2v

1.2v

1.2v

1.2v

PM2

0.8v

off

1.2v

1.2v

1.2v

PM3

0.8v

off

off

off

1.2

PM4

0.8v

1.2v

1.2v

1.2v

off

#file name syn.cpf

update_nominal_condition -name high -library_set 120v
update_nominal_condition -name low -library_set 08v
update_power_mode name PM1 sdc_files ../../../sdc/PM1.sdc
update_power_mode name PM4 sdc_files ../../../sdc/PM4.sdc
The synthesis libraries are automatically linked to each power domain for

each power domain

Associate timing constraints to each power mode for DVFS synthesis

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Complete Command Syntax

update_nominal_condition -name nominal_condition -library_set library_set
update_power_mode -name mode
{ -activity_file file -activity_file_weight weight
| -sdc_files sdc_file_list
| -peak_ir_drop_limit domain_voltage_list
| -average_ir_drop_limit domain_voltage_list
| -leakage_power_limit float
| -dynamic_power_limit float}...

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Put Everything Together For Logic Implementation

include tech.cpf
set_design nano_cpu
create_power_domain -name PDcore -default
create_power_domain -name PDau -instances alu_inst/aui -shutoff_condition pcu_inst/pau[2]
create_power_domain -name PDlu -instances alu_inst/lui -shutoff_condition pcu_inst/plu[2]
create_power_domain -name PDalu -instances alu_inst -shutoff_condition pcu_inst/palu[2]
create_power_domain -name PDrf -instances rf_inst -shutoff_condition pcu_inst/prf[2]
create_state_retention_rule name sr_rule domain PDrf -restore_edge { ! pcu_inst/prf[1] }
create_isolation_rule -name iso_rule1 -from PDau -isolation_condition {!pcu_inst/pau[0]} -isolation_output low
create_isolation_rule -name iso_rule2 -from PDlu -isolation_condition {!pcu_inst/plu[0]} -isolation_output low
create_isolation_rule -name iso_rule3 -from PDalu -isolation_condition {!pcu_inst/palu[0]} -isolation_output low
create_isolation_rule -name iso_rule4 -from PDrf -isolation_condition {!pcu_inst/prf[0]} -isolation_output low
create_nominal_condition -name high -voltage 1.20
create_nominal_condition -name low -voltage 0.8
create_power_mode -name PM1 \
default -domain_conditions {PDcore@high PDau@high PDlu@high PDalu@high PDrf@high}
create_power_mode -name PM2 -domain_conditions {PDcore@low PDlu@high PDalu@high PDrf@high}
create_power_mode -name PM3 -domain_conditions {PDcore@low PDrf@high}
create_power_mode -name PM4 -domain_conditions {PDcore@low PDau@high PDlu@high PDalu@high }
source syn.cpf
end_design

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Low Power Logic Implementation and Verification Using CPF

Still, no need to specify power or ground nets at this design stage

Minimal set of CPF commands for designers to use

Logic synthesis tools

to synthesize isolation, level shifter and state retention logic

to perform power domain aware logic synthesis

to perform power mode aware (DVFS) synthesis

Test synthesis tools

to perform power domain and power mode aware DFT synthesis

to generate power domain aware test control logic

Formal Verification tools

to check the correctness of low power structural implemented by synthesis tools

to perform low power equivalency checking (RTL+CPF vs Netlist)

Simulation tools

to perform power aware gate level simulation

to generate additional assertions for gate level simulation

Analysis tools

to perform power domain aware and power mode aware power analysis

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Specify Power/Ground Nets for Physical Implementation

#file name phy_pg.cpf
#power/ground net specification
create_power_nets nets VDD1 voltage 1.2
create_power_nets nets VDD2 voltage 0.8
create_power_nets nets { VDD_core VDD1_au_sw VDD1_lu_sw VDD1_alu_sw VDD1_rf_sw} internal
create_ground_nets nets VSS
update_power_domain name PDcore internal_power_net VDD_core internal_ground_net VSS
update_power_domain name PDau internal_power_net VDD1_au_sw internal_ground_net VSS
update_power_domain name PDlu internal_power_net VDD1_lu_sw internal_ground_net VSS
update_power_domain name PDalu internal_power_net VDD1_alu_sw internal_ground_net VSS
update_power_domain name PDrf internal_power_net VDD1_rf_sw internal_ground_net VSS
#power switch specification for power shutoff
create_power_switch_rule name PDau_sw domain PDau external_power_net VDD1
create_power_switch_rule name PDlu_sw domain PDlu external_power_net VDD1
create_power_switch_rule name PDalu_sw domain PDalu external_power_net VDD1
create_power_switch_rule name PDrf_sw domain PDrf external_power_net VDD1
#power switch specification for DVFS control
create_power_switch_rule name PDcore_1 domain PDcore external_power_net VDD1
update_power_switch_rule name PDcore_1 enable_condition_1 {pcu_inst/pcore[2]}
create_power_switch_rule name PDcore_2 domain PDcore external_power_net VDD2
update_power_switch_rule name PDcore_2 enable_condition_1 {!pcu_inst/pcore[2]}
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Complete Command Syntax for Power/Ground Nets Specification

create_power_nets -nets net_list [-voltage string]

[-external_shutoff_condition expression | -internal] [-user_attributes string_list]
[-peak_ir_drop_limit float] [-average_ir_drop_limit float]
create_ground_nets -nets net_list [-voltage string]
[-internal] [-user_attributes string_list]
[-peak_ir_drop_limit float] [-average_ir_drop_limit float]
update_power_domain -name domain
{ -internal_power_net net | -internal_ground_net net
| -min_power_up_time float | -max_power_up_time float
| -pmos_bias_net net | -nmos_bias_net net | -user_attributes string_list
| -rail_mapping rail_mapping_list -library_set library_set} ...

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Complete Command Syntax for Power Switch Specification

create_power_switch_rule -name string

-domain power_domain {-external_power_net net | -external_ground_net net}

update_power_switch_rule -name string

{ -enable_condition_1 expression [-enable_condition_2 expression]
| -acknowledge_receiver pin
| -cells cell_list -library_set library_set
| -prefix string
| -peak_ir_drop_limit float
| -average_ir_drop_limit float }...

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Specify MMMC Constraints for Physical Timing Closure & Analysis

PDcore

PDau

PDlu

PDalu

PDrf

PM1

1.2v

1.2v

1.2v

1.2v

1.2v

PM2

0.8v

off

1.2v

1.2v

1.2v

PM3

0.8v

off

off

off

1.2

PM4

0.8v

1.2v

1.2v

1.2v

off

Need to analysis 2 corners for

this mode, fast and slow
Need to analysis 2 corners for
this mode, fast and slow

#file name phy_mmmc.cpf to setup Multi-Mode-Multi-Corner (MMMC) timing closure constraints

create_operating_corner name 120v_fast voltage 1.3 library_set 120v
create_operating_corner name 120v_slow voltage library_set 120v
create_operating_corner name 08v_fast voltage 0.9 library_set 08v
create_operating_corner name 08v_slow voltage 0.7 library_set 07v
create_analysis_view name view1 mode PM1 domain_corners \
{ PDcore@120v_fast PDau@120v_fast PDlu@120v_fast PDalu@120v_fast PDrf@120v_fast}
create_analysis_view name view2 mode PM1 domain_corners \
{ PDcore@120v_slow PDau@120v_slow PDlu@120v_slow PDalu@120v_slow PDrf@120v_slow}
create_analysis_view name view3 mode PM4 domain_corners \
{ PDcore@08v_fast PDau@120v_fast PDlu@120v_fast PDalu@120v_fast
}
create_analysis_view name view4 mode PM4 domain_corners \
{ PDcore@080v_slow PDau@120v_slow PDlu@120v_slow PDalu@120v_slow
}

Innovation Through Collaboration Low Power Coalition

37

Command Syntax for MMMC Setup

create_operating_corner -name string -voltage float

[-process float] [-temperature float] -library_set library_set

create_analysis_view -name string -mode mode

-domain_corners domain_corner_list

Innovation Through Collaboration Low Power Coalition

38

Overview of CPF Support for DVFS & MMMC

create_analysis_view
-name <string>
MMMC
-mode <mode_name>
-domain_corners
{ list_of_operating_corners_by_domain }
create_power_mode
-name <string>
DVFS
-domain_conditions
{ list_of_nominal_condition_by_domains }
update_power_mode
-name <mode_name>
[ -activity_file file -activity_file_weight weight ]
[ -sdc_files sdc_file_list ]
create_nominal_condition
-name <string>
-voltage <float>
update_nominal_condition
-name <nominal_condition>
-library_set <name>

Innovation Through Collaboration Low Power Coalition

create_operating_corner
-name
<string>
-voltage
<float>
[-process
<float>]
[-temperature
<float>]
-library_set
<name>
define_library_set
-name <library_set>
-timing <library_list>

create_power_domain
-name <string>
{-default [-instances instance_list]
[-boundary_ports pin_list]
| -instances instance_list
[-boundary_ports pin_lust]
[-boundary_ports pin_list }
[-shoutoff_condition expression]
39

Put Everything Together For Physical Implementation

include tech.cpf
set_design nano_cpu
create_power_domain -name PDcore -default
create_power_domain -name PDau -instances alu_inst/aui -shutoff_condition pcu_inst/pau[2]
create_power_domain -name PDlu -instances alu_inst/lui -shutoff_condition pcu_inst/plu[2]
create_power_domain -name PDalu -instances alu_inst -shutoff_condition pcu_inst/palu[2]
create_power_domain -name PDrf -instances rf_inst -shutoff_condition pcu_inst/prf[2]
create_state_retention_rule name sr_rule domain PDrf -restore_edge { ! pcu_inst/prf[1] }
create_isolation_rule -name iso_rule1 -from PDau -isolation_condition {!pcu_inst/pau[0]} -isolation_output low
create_isolation_rule -name iso_rule2 -from PDlu -isolation_condition {!pcu_inst/plu[0]} -isolation_output low
create_isolation_rule -name iso_rule3 -from PDalu -isolation_condition {!pcu_inst/palu[0]} -isolation_output low
create_isolation_rule -name iso_rule4 -from PDrf -isolation_condition {!pcu_inst/prf[0]} -isolation_output low
create_nominal_condition -name high -voltage 1.20
create_nominal_condition -name low -voltage 0.8
create_power_mode -name PM1 \
default -domain_conditions {PDcore@high PDau@high PDlu@high PDalu@high PDrf@high}
create_power_mode -name PM2 -domain_conditions {PDcore@low PDlu@high PDalu@high PDrf@high}
create_power_mode -name PM3 -domain_conditions {PDcore@low PDrf@high}
create_power_mode -name PM4 -domain_conditions {PDcore@low PDau@high PDlu@high PDalu@high }
source syn.cpf
source phy_pg.cpf
source phy_mmmc.cpf
end_design
Innovation Through Collaboration Low Power Coalition

40

Low Power Physical Implementation and Verification Using CPF

At this stage

The power and ground nets for each power domain are fully specified

The power switch logic is specified for each domain

Complete set of CPF commands for back-end designers to use

Physical implementation tools

to perform power domain aware placement and routing

to insert and optimize power switch network

to connect the power and ground nets

to insert additional low power logic due to netlist change if needed

to perform Multi-Mode-Multi-Corner timing and power optimization and analysis

Verification tools

to check the correctness of low power physical structural

Analysis tools

to perform dynamic analysis power switch network

to perform sign-off power and timing analysis

Innovation Through Collaboration Low Power Coalition

41

Other Implementation related commands

Optional implementation constraints to provide designers more flexibility in logical
and physical implementation
update_isolation_rules -names rule_list { -location {from | to}
| -cells cell_list -library_set library_set
| -prefix string | -combine_level_shifting
| -open_source_pins_only}...
update_level_shifter_rules -names rule_list
{ -location {from | to} | -cells cell_list -library_set library_set
| -prefix string }...
update_state_retention_rules -names rule_list
{-cell_type string | -cell libcell -library_set library_set}

Innovation Through Collaboration Low Power Coalition

42

Other Commands
Hierarchical Flow
set_instance [hier_instance [-merge_default_domains]
[-port_mapping port_mapping_list]]
set_hierarchy_separator string
RTL to Netlist Name Mapping
set_register_naming_style
set_array_naming_style
General Commands
set_cpf_version
set_power_target
set_power_unit
set_switching_activity
set_time_unit

Innovation Through Collaboration Low Power Coalition

43

Outline
Where Was It Started?
CPF Basics
Digest CPF Using A Simple Example
CPF Based Low Power Design Flow
Where Is CPF Headed?

Innovation Through Collaboration Low Power Coalition

44

CPF Enabled Low Power Design Flow

Design for Test

SVP

Coding

Constraints

Sign-off

Innovation Through Collaboration Low Power Coalition

GDSII

ATPG

Routing

Analysis

Physical Synthesis

Structural &
Funct. Checks
Simulation
Acceleration
& Emulation

Functionally verify
advanced power
implementation
techniques

Hand off to drive physical

implementation

Chip Integration
Prototyping
DFT

Equivalence LVS/DRC/Ext
checking

Single power
specification used from
specification to GDSII

Netlist

Physical Implementation
Constraint Validation

Golden
specification
eliminates
assumptions and
miscommunications

CPF

Formal
Analysis

Testbench Automation

Synthesis

Verification

Iterate RTLRTL
+ CPF Iterate

Constraint Validation

Equivalence Checking

Design Creation
b
Constraint
Generation

Quick architectural exploration

Verification Coverage

Instantiate single
RTL with different
power profiles

Specification
Function, timing, power

Re-use preverified IP

Automatic partitioning of
power domains
Automatic scheduling of
test modes

45

Continued Industry Wide Adoption of CPF

1Q2007

2Q2007
Reference
Flow 8.0
PRIDE Flow

2H2007
EnergyPro
Technology
Joins PFI
Joins PFI

CPF becomes
Si2 standard
Cadence Low
Power Solution
production
released V 1.0

Common
Platform
Flow
Joins PFI
PowerPro CG

DDR PHY
Innovation Through Collaboration Low Power Coalition

Joins PFI
> 100 customer adopting
CPF-based advanced low
power solution
~ 50 tapeouts
Freescale, Fujitsu, NEC, NXP..
46

Ecosystem Support for CPF Based Low Power Solution

Early
Adopters

Foundry

IP Vendor

ASIC /
Design
Service

EDA
www.powerforward.org
Innovation Through Collaboration Low Power Coalition

47

TSMC 8.0 Low Power Reference Flow

CPF
CPF Quality
Quality Check
Check
Conformal
Low
Conformal Low Power
Power
CPF-Enabled
CPF-Enabled Functional
Functional simulation
simulation
Incisive
Design
Team
Simulator
Incisive Design Team Simulator
Incisive
Incisive Design
Design Team
Team Manager
Manager
CPF-Enabled
CPF-Enabled Logic
Logic Synthesis
Synthesis &
& DFT
DFT
Encounter
RTL
Compiler
Encounter RTL Compiler
CPF-Enabled
CPF-Enabled LEC
LEC ++ Power
Power Checks
Checks
Conformal
Conformal Low
Low Power
Power

CPF

CPF-Enabled
CPF-Enabled Logic
Logic simulation
simulation
Incisive
Design
Team
Incisive Design Team Simulator
Simulator
CPF-Enabled
CPF-Enabled Physical
Physical implementation
implementation
SoC
Encounter
SoC Encounter
CPF-Enabled
CPF-Enabled LEC
LEC ++ Power
Power Checks
Checks
Conformal
Low
Power
Conformal Low Power
CPF-Enabled
CPF-Enabled ATPG
ATPG
Encounter
Test
Encounter Test
CPF-Enabled
CPF-Enabled Timing
Timing &
& SI
SI signoff
signoff
Encounter
Timing
System
Encounter Timing System
CPF-Enabled
CPF-Enabled Leakage
Leakage &
& Thermal
Thermal Analysis
Analysis
Encounter
Timing
System
Encounter Timing System
CPF-Enabled
CPF-Enabled IR
IR drop
drop &
& Power
Power signoff
signoff
VoltageStorm-DG
VoltageStorm-DG

48

Innovation Through Collaboration Low Power Coalition

www.tsmc.com
48

ARC Proof Point Project Using CPF Based Low Power Solution

ARC700 with SIMD Co-Processor

SIMD SDM
I$ ARC700
D$ SCQ SCQ SCM
I$

problems that you will not

otherwise identify
CPF aids communication of power
intent across team boundaries,
ensuring accurate implementation
at all flow stages
Significant power savings results
using these techniques

49

Innovation Through Collaboration Low Power Coalition

SCQ
SCQ SCM
SCQ

SDM

Always On

Power Forward
low-power implementation &
verification project results
Simulation with CPF identifies

D$

Functional Blocks

Power Domains

Clock Gating Domains

For high bit-rate data streams, both

the ARC and the SIMD run flat out
For lower bit-rate data stream, the
subsystem can be run at a lower
frequency
For generic processing, the SIMD
can be inactive
49

Fujitsu Proof Point Project Using CPF Based Low Power Solution

90nm
940K instances
11 Power Domains
19 Power Modes
DVFS

Verified with test design

PSO functional verification with simulation

Low power structural and physical check

(Shifters/Isolators/Power switches)

Domain aware place and route

Conclusion

Functional verification is necessary for

complex PSO design for design bugs

Structural check with CPF could verify LP

design

Fujitsu will support CPF-based ASIC flow for

their customers

50

Innovation Through Collaboration Low Power Coalition

CPU1

Power Switch

peripherals

CPU2

Power
Domains

Silicon
SiliconProven
Proven September
September07
07
50

NEC Proof Point Project Using CPF Based Low Power Solution

65nm
6 Power Domains
5 Power Modes
2 Supply Voltage

NEC Electronics
Corporation

PD0: 1.2V
(Default,
Always On)

Driver

PD1:1.2V

PD4:0.74V

PD2:1.2V

PSOcntl

Validated CPF and CPF-based flow

for major low power methodologies
in NEC Electronics
9
9
9
9
9
9
9

386 checkpoints evaluated successfully

CPF describe-ability
Multi-Supply-Voltage (MSV)
Power Shut Off (PSO)
State Retention Logic (SRL)
Variable Voltage Library (VVL)
Clock Tree Gating (CTG)

CPF based flow will be in use from Q3/2007

51

PD3:0.74V

PSGcntl
PD5:0.74V

ISOcntl
Power
Mode

Power Domain
PD0

PD1

PD2

PD3

PD4

PD5

PM1

1.2V

1.2V

1.2V

0.74V

0.74V

0.74V

PM2

1.2V

PSO

1.2V

0.74V

0.74V

0.74V

PM3

1.2V

1.2V

PSO

0.74V

0.74V

0.74V

PM4

1.2V

1.2V

1.2V

PSO

0.74V

0.74V

PM5

1.2V

PSO

PSO

PSO

0.74V

PSO

Innovation Through Collaboration Low Power Coalition

51

NXP Proof Point Project Using CPF Based Low Power Solution

Power Forward low-power

platform SoC results
CPF-based functional

verification (using simulation)

catches system level power
issues early in the flow
Use of CPF ensured what

implementation built was what

was verified

52

Innovation Through Collaboration Low Power Coalition

SoC consists of 11 islands

3 major power consumers -RISC
CPU, VLIW DSP & L2 System
Cache are controlled using DVFS
High bandwidth expansion ports
enable extension, with graphics
or cellular modem subsystems
52

Outline
Where Was It Started?
CPF Basics
Digest CPF Using A Simple Example
CPF Based Low Power Design Flow
Where Is CPF Headed?

Innovation Through Collaboration Low Power Coalition

53

Si2 LPC Progress

Three Working Groups

Data API

Design Flow

Common Glossary
Low Power Design Flow Document

Format Requirement

Format Requirement Working Group

Clarification on CPF 1.0 semantics

Collect new requirements for format
improvements

Custom macro modeling

More flexibility on IP reuse

Complete hierarchical flow

Innovation Through Collaboration Low Power Coalition

54

CPF Related Information

CPF 1.0 Documents & Parser

http://www.si2.org/openeda.si2.org/projects/si2cpf/
Si2 LPC

http://www.si2.org

Power Forward Initiative

http://www.powerforward.org

Power Format Comparison

http://www.si2.org/?page=866

Innovation Through Collaboration Low Power Coalition

55