Scribd
Upload
107 views5 pages

Design For Testability (DFT) Flow For Digital Designs: Testability Course Final Project

This document outlines the phases and objectives of a final testability project for a digital design course. The project involves [1] verilog modeling and synthesis of sequential circuits, [2] inserting scan chains using Synopsys DFT compiler, and [3] generating test patterns using Tetramax to evaluate fault coverage with and without scan chains. Students are to complete the phases in groups of two by selecting circuits, synthesizing, inserting scans, and reporting results.

Uploaded by

apalaniswamy_2
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
107 views5 pages

Design For Testability (DFT) Flow For Digital Designs: Testability Course Final Project

This document outlines the phases and objectives of a final testability project for a digital design course. The project involves [1] verilog modeling and synthesis of sequential circuits, [2] inserting scan chains using Synopsys DFT compiler, and [3] generating test patterns using Tetramax to evaluate fault coverage with and without scan chains. Students are to complete the phases in groups of two by selecting circuits, synthesizing, inserting scans, and reporting results.

Uploaded by

apalaniswamy_2
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Thisisthehtmlversionofthefile[Link] 1/resources/root/Project/Testability_FinalProject_new.pdf. Google automaticallygenerateshtmlversionsofdocumentsaswecrawltheweb.

Page1

SharifUniversityofTechnology DepartmentofComputerEngineering

TestabilityCourse FinalProject

DesignforTestability(DFT)FlowforDigital Designs

Instructor:ShaahinHessabi Assistant:HajarFalahati December2012

Page2

TestabilityFinalProject
Objectives:
Verilogmodelingofsequentialcircuits. SynthesisofanRTLdesignusingSynopsysDesignCompiler(DC). UsingTetramaxtogeneratetestpatternsforCombinationalLogic InsertscanchainintoadesignusingSynopsysDFTcompiler UsingTetramaxtogeneratetestpatternsforscaninserteddesign

Tools:
Simulation:Modelsim/VCS/NCVerilog/IcarusVerilog

DesignCompiler(Synopsys) Synthesis: Scanchaininsertion: DFTCompiler(embeddedinDC) Automatictestpatterngeneration(ATPG):Tetramax

Page3

TestabilityFinalProject
Phase0:Introduction
[Link]! Pleasebenotice,eachteamwillconsistoftwostudents. [Link](Complicatedenough!!)circuitsfrom [Link] implementedbyVerilogcode.

[Link] [Link] [Link]. hfalahai@[Link]:[Test][FinalProject][Team] [Link],23:55. [Link]

Phase1:SynthesizingSequentialCircuits
[Link]. [Link],includingtheir waveforms! hfalahai@[Link]:[Test][FinalProject][Phase1] [Link],23:55. [Link],23:55.

Phase2:InsertScanChain
[Link]! [Link]! III.Insertasinglescanchainineachofthesynthesizeddesignsobtainedfromphse1, usingtheDFTCompiler(embeddedinDesignCompiler). IV. Savethenetlistsafterinsertingthescanchains. V. Reportarea,timing,andpowerofthescaninsertednetlists,alsoabriefReview onDFTCompiler! VI. Completethefollowingtableforarea,timing,power: CircuitName Area/timing/power withoutscaninsertion Area/timing/power withscaninsertion

[Link],23:55. [Link],23:55.

Page4

TestabilityFinalProject Phase3:GenerateTestPatterns
[Link]! [Link]! III.Generatetestpatternsforeachofthenetlistsofphase1usingTetramax,and observethefaultcoverageforsinglestuckatfaults. IV.Generatetestpatternsforeachofthenetlistsofphase2usingTetramax,and observethefaultcoverageforsinglestuckatfaults. [Link]: CircuitName Faultcoveragewithout scaninsertion Faultcoveragewith scaninsertion

[Link],23:55. [Link],23:55.

You might also like