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FSM and ROM Design Patterns

The document provides illustrative examples of Moore and Mealy finite state machines (FSM), read-only memory (ROM) implementations, and variable waveform generators using ROM. Example 1 and 2 show Moore and Mealy FSM designs. Example 3 defines a ROM package and entity. Example 4 demonstrates a ROM implementation of a 5x8 ROM. Example 5 and 6 define waveform generators using ROM to store step values. Example 7 extends the waveform generator to use variable step durations stored in a ROM table.

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100 views3 pages

FSM and ROM Design Patterns

The document provides illustrative examples of Moore and Mealy finite state machines (FSM), read-only memory (ROM) implementations, and variable waveform generators using ROM. Example 1 and 2 show Moore and Mealy FSM designs. Example 3 defines a ROM package and entity. Example 4 demonstrates a ROM implementation of a 5x8 ROM. Example 5 and 6 define waveform generators using ROM to store step values. Example 7 extends the waveform generator to use variable step durations stored in a ROM table.

Uploaded by

praful_kohale6642
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd

Illustrative examples

Moore Machine A.1


COMBIN: process(CURRENT_STATE, X) begin case CURRENT_STATE is when S0 => Z <= 0; if X = 0 then NEXT_STATE <= S0; else NEXT_STATE <= S2; end if; when S1 => Z <= 1; if X = 0 then NEXT_STATE <= S0; else NEXT_STATE <= S2; end if; when S2 => Z <= 1; if X = 0 then NEXT_STATE <= S2; else NEXT_STATE <= S3; end if; when S3 => Z <= 0; if X = 0 then NEXT_STATE <= S3; else NEXT_STATE <= S1; end if; end case; end process COMBIN; SYNCH: process begin wait until CLOCKevent and CLOCK = 1; CURRENT_STATE <= NEXT_STATE; Z_out <= Z; -- register the output end process SYNCH; A2 2

Mealy FSM A3
COMBIN: process(CURRENT_STATE, X) begin case CURRENT_STATE is when S0 => if X = 0 then Z <= 0; NEXT_STATE <= S0; else Z <= 1; NEXT_STATE <= S2; end if; when S1 => if X = 0 then Z <= 0; NEXT_STATE <= S0; else Z <= 0; NEXT_STATE <= S2; end if; when S2 => if X = 0 then Z <= 1; NEXT_STATE <= S2; else Z <= 0; NEXT_STATE <= S3; end if; when S3 => if X = 0 then Z <= 0; NEXT_STATE <= S3; else Z <= 1; NEXT_STATE <= S1; end if; end case; end process COMBIN; SYNCH: process begin wait until CLOCKevent and CLOCK = 1; CURRENT_STATE <= NEXT_STATE; end process SYNCH; A4
3

ROM
package ROMS is constant ROM_WIDTH: INTEGER := 5; subtype ROM_WORD is BIT_VECTOR (1 to ROM_WIDTH); subtype ROM_RANGE is INTEGER range 0 to 7; type ROM_TABLE is array (0 to 7) of ROM_WORD; constant ROM: ROM_TABLE := ROM_TABLE( ROM_WORD(10101), ROM_WORD(10000), ROM_WORD(11111), ROM_WORD(11111), ROM_WORD(10000), ROM_WORD(10101), ROM_WORD(11111), ROM_WORD(11111)); end ROMS; use [Link]; -- Entity that uses ROM entity ROM_5x8 is port(ADDR: in ROM_RANGE; DATA: out ROM_WORD); end ROM_5x8; architecture BEHAVIOR of ROM_5x8 is Begin DATA <= ROM(ADDR); end BEHAVIOR; A5
4

Waveform generator A6
constant ROM_WIDTH: INTEGER := 4; subtype ROM_WORD is BIT_VECTOR (1 to ROM_WIDTH); subtype ROM_RANGE is INTEGER range 0 to 12; type ROM_TABLE is array (0 to 12) of ROM_WORD; constant ROM: ROM_TABLE := ROM_TABLE( 1100, -- time step 0 1100, -- time step 1 process 0100, -- time step 2 begin 0000, -- time step 3 wait until CLOCKevent and CLOCK = 1; 0110, -- time step 4 if RESET then STEP <= ROM_RANGElow; 0101, -- time step 5 elsif STEP = ROM_RANGEhigh then 0111, -- time step 6 1100, -- time step 7 STEP <= ROM_RANGEhigh; 0100, -- time step 8 else 0000, -- time step 9 STEP <= STEP + 1; 0110, -- time step 10 end if; 0101, -- time step 11 end process; 0111); -- time step 12 WAVES <= ROM(STEP); A7
5

Variable duration WFG A8


subtype D_ROM_WORD is INTEGER range 0 to 100; subtype D_ROM_RANGE is INTEGER range 0 to 12; type D_ROM_TABLE is array (0 to 12) of D_ROM_WORD; constant D_ROM: D_ROM_TABLE := D_ROM_TABLE(1,80,5,1,1,1,1,20,5,1,1,1,1); NEXT_STEP <= W_ROM_RANGEhigh when STEP =W_ROM_RANGEhigh else STEP + 1; process begin wait until CLOCKevent and CLOCK = 1; if RESET then STEP <= 0; elsif DELAY = 1 then STEP <= NEXT_STEP; else null; end if; end process; process begin wait until CLOCKevent and CLOCK = 1; if RESET then DELAY <= D_ROM(0); elsif DELAY = 1 then DELAY <= D_ROM(NEXT_STEP); else DELAY <= DELAY - 1; end if; end process;

WAVES <= W_ROM(STEP);


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