TD FSM 2023

PROBLEM 1
▪ Complete the timing diagram of the following circuit. 𝐺 = 𝐺3 𝐺2 𝐺1 𝐺0 = 1011, 𝑄 = 𝑄3 𝑄2 𝑄1 𝑄0
Q0 Q1 Q2 Q3

resetn
x
D Q D Q D Q D Q
E E E E E

clk

G0 G1 G2 G3

clk

resetn

Q 0000

PROBLEM 2
▪ Design a counter using a Finite State Machine (FSM):
Counter features: resetn
✓ Count: 000, 001, 011, 101, 111, 010, 100, 110, 000, 001, 011, 101, … 3
E E Q
✓ Input E: Synchronous input that increases the count when it is set to ‘1’.
✓ Output z: It becomes ‘1’ when the count is 110. COUNTER
✓ resetn: Asynchronous active-low input signal. It initializes the count to 000 . clock z

▪ Provide the State Diagram (any representation), State Table, and the Excitation Table of this circuit.
▪ Provide the excitation equations (simplify your circuit using K-maps or the Quine-McCluskey algorithm)
▪ Sketch the circuit. Is this a Mealy or a Moore machine? Why?

PROBLEM 3
▪ Sequence detector: The machine generates 𝑧 = 1 when it detects the sequence 00110101. Once the sequence is detected,
the circuit looks for a new sequence.
resetn

x
z x 0 1 0 0 1 1 0 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 0 1 1 0 1 0 1
FINITE STATE
MACHINE
z
clock

✓ Draw the State Diagram (any representation) of this circuit with input 𝑥 and output 𝑧. ✓
Complete the State Table and the Excitation Table. ()
✓ Which type is this FSM? (Mealy) (Moore) Why? _________________

1
▪ Given the following FSM circuit. (𝑤: input, 𝑧: resetn
output, 𝑄1 𝑄0: state) clk
✓ Provide the Excitation Table, State Table, and
the State Diagram (any representation).
✓ Get the excitation equations and the Boolean
equation for z.
D Q Q1
✓ Which type is this FSM? w
(Mealy) (Moore)
z

D Q Q0

PROBLEM 4
▪ Provide the state diagram (in ASM form) of the FSM whose VHDL description is shown below. Is it a Mealy or a Moore FSM?
▪ Complete the Timing Diagram.
library ieee; architecture behavioral of myfsm is
use ieee.std_logic_1164.all; type state is (S1, S2, S3);
signal y: state;
entity myfsm is begin
port ( clk, resetn: in std_logic; Transitions: process (resetn, clk, a, b)
a, b: in std_logic; begin
x,w,z: out std_logic); if resetn = '0' then y <= S1;
end myfsm; elsif (clk'event and clk = '1') then
case y is
when S1 =>
if a = '1' then
if b = ‘1’ then y <= S3; else y <= S1; end if;
else
y <= S2;
end if;

when S2 =>
if a = '1' then y <= S3; else y <= S2; end if;

when S3 =>
if b = ‘1’ then y <= S3; else y <= S1; end if;
end case;
end if;
end process;

Outputs: process (y, a, b)

begin
x <= ‘0’; w <= ‘0’; z <= ‘0’;
case y is
when S1 => if a = ‘1’ then x <= ‘1’; end if;
when S2 => if b = ‘1’ then w <= ‘1’; end if;
when S3 => z <= ‘1’;
end case;
end process;
end behavioral;

clk

resetn

state

w
PROBLEM 5
▪ Complete the timing diagram of the following digital system that includes an FSM (in ASM form) and a datapath circuit.
Generic components: counter, parallel access shift registers, register. –
s DA DB resetn=0
6 4 S1
sclrR  1, ER 1
EC 1, sclrC 1
s_L LEFT SHIFT E
E w REGISTER
REGISTER 0
s
LAB

EA

A 4 B 1
0
EC
5 '0'&B LAB, EA  1
E Q 3 Y
sclrC

R3R2R1R0a5
sclr S2
zC cout
ER  1, EA  1
cout
counter
cout + cin 1

0 to 5 5 T4T3T2T1T0 1
cout LR  1
4 T3T2T1T0 0

resetn sclrR sclr

FSM LR s_L LEFT SHIFT a5 C=5?
ER w 0
clock E REGISTER zC EC  1

5 4 1
zC 4 S3
DATAPATH
a5 R3R2R1R0 done  1
CIRCUIT
6 4
0 1
Q s
done R

clock

resetn

DA 000000 011011 000000 010100

DB 0000 1001 0000 0111

Q=A 000000

R 0000

T 00000

EA

EC

QC 000

zC

cout

LR

ER
state S1

done