Micro Programmed Control
Micro programmed control
organization
External Input Control Word
Next Address Control Control
Control data
generator Address memory
register
(sequencer) register (ROM)
Next Address
Information
Address Sequencing
Instruction Code
Mapping Logic
Branch
Logic Multiplexes
SBR
Clock CAR
Incrementer
Select Control Memory
Status Bit
Branch Address Micro operations
Micro Program Example (HW configuration)
MUX
Main Memory
10 0 ( 2048 X 16)
AR
10 0 MUX
PC
15 0
DR
6 0 6 0
SBR CAR A L & Shift Unit
15 0
Control Memory AC
( 128 X 20 )
Machine Instruction format:
15 14 11 10 0
I opcode Address
FOUR COMPUTER INSTRUCTION
Symbol Opcode Description
ADD 0000 AC AC + M[ EA ]
BRANCH 0001 If ( AC < 0 ) ( PC EA )
STORE 0010 M [ EA ] AC
EXCHANGE 0011 AC M [ EA ], M [EA] AC
Micro Instruction format:
3 3 3 2 2 7
F1 F2 F3 CD BR AD
F1, F2, F3 Micro operation field
CD Condition for branching
BR Branch Field
AD Address field
F1 Micro Instructions
F1 Micro Operation Symbol
000 None NOP
001 ACAC+DR ADD
010 AC0 CLRAC
011 ACAC+1 INCAC
100 ACDR DRTAC
101 ARDR(0-10) DRTAR
110 ARPC PCTAR
111 M[AR]DR WRITE
F2 Micro Instruction
F2 Micro operation Symbol
000 None NOP
001 ACAC-DR SUB
010 ACAC v DR OR
011 ACAC ^ DR AND
100 DRM[AR] READ
101 DRAC ACTDR
110 DRDR+1 INCDR
111 DR(0 – 10 ) PC PCTDR
F3 Micro Instruction
F3 Micro operation Symbol
000 None NOP
001 ACAC DR XOR
010 ACAC COM
011 AC shl AC SHL
100 AC shr AC SHR
101 PCPC+1 INCPC
110 PCAR ARTPC
111 Reserved
CD Micro Instruction
CD Condition Symbol Comments
00 Always = 1 U Unconditional Branch
01 DR ( 15 ) I Indirect Address Bit
10 AC ( 15 ) S Sign Bit of AC
11 AC = 0 Z Zero Value in AC
BR Micro Instruction
BR Symbol Function
00 JMP CAR AD if condition = 1
CAR CAR + 1 if condition = 0
01 CALL CAR AD, SBR CAR + 1 if condition = 1
Car CAR + 1 if condition = 0
10 RET CAR SBR (return from sun routine)
11 MAP CAR ( 2-5) DR (11 – 14), CAR (0, 1, 6) 0
Symbolic Micro program
Label Micro CD BR AD
operation
ORG 0
ADD: NOP I CALL INDRCT
READ U JMP NEXT
ADD U JMP FETCH
ORG 64
FETCH: PCTAR U JMP NEXT
READ, INCPC U JMP NEXT
DRTAR U MAP
INDRCT: READ U JMP NEXT
DRTAR U RET
Design of control unit
F1 F2 F3
3 X 8 Decoder 3 X 8 Decoder 3 X 8 decoder
AND
ADD
DRTAC Arithmetic logic
shift unit
From PC From DR (0 – 10)
Load
Multiplexer AC
Select
Load CLK
AR