MICRO

PROGRAMMED
CONTROL
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 CONTROL UNIT
 Control unit generates timing and control signals for the
operations of the computer.
(groups of bits that select the paths in multiplexers, decoders,
and arithmetic logic units)

 It’s the part of the CPU that initiates sequences of

microoperations.

 It tells the computer’s memory, arithmetic & logic unit and

input/output devices how to respond to a program’s
instructions.
 METHODS TO IMPLEMENT
CONTROL UNIT

HARDWIRED CONTROL MICROPROGRAMMED

UNIT CONTROL UNIT

uses fixes the logic of the control

instructions, unit is specified by
combinational logic microprograms (consists
units of AND/OR (logic of a sequence of
gates), encoders, instructions that specify
decoders, etc. microoperations)
IMPORTANT
TERMS
CONTROL WORD

• The control variables at any

time are represented by 1’s
IMPORTANT
and 0’s, known as Control
Word.
TERMS
• Control words can be
programmed to perform
various operations.
 CONTROL WORD
MICROPROGRAMMED
CONTROL UNIT
• The control variables at any
time are represented by 1’s
IMPORTANT
and 0’s, known as Control
• A control unit whose binary control
Word.
TERMS
variables are stored in the memory is
called MICROPROGRAMMED CONTROL
• Control words can be
UNIT.
programmed to perform
various operations.
 CONTROL WORD
MICROINSTRUCTIONS
MICROPROGRAMMED
CONTROL UNIT
• The control variables at any
• Each word in are
time the represented
control memory
by 1’s
containsand
microinstructions.
IMPORTANT
0’s, known as Control
• A control unit whose binary control
Word.
variablesone
• It specifies TERMS
are stored
or more in the memory is
called MICROPROGRAMMED
microoperations for the CONTROL
system.
• Control words can be
UNIT.
programmed to perform
various operations.
 MICROPROGRAM CONTROL WORD
MICROINSTRUCTIONS
MICROPROGRAMMED
• Sequence of microinstructions
CONTROL
constitutes •a The UNIT
control variables at any
microprogram.
• Each word in are
the represented
control memory
Dynamic microprogramming : Control Memoryby
time 1’s
=>RAM
containsandmicroinstructions.
• RAM can
• A be used for
control unit IMPORTANT
0’s, known as Control
writing
whose (to binary
change control
a
Word.
writable control memory)
variables
• It specifies
• Microprogram one
is loaded or TERMS
are stored
more
initially
in the memory is
from an
called
auxiliary memoryMICROPROGRAMMED
microoperations such asfor the system.
a magnetic CONTROL
disk
• Control words can be
UNIT.
programmed to perform
Static microprogramming : Control Memory =>ROM
various operations.
• Control words in ROM are made permanent
during the hardware production.
MICROPROGRAMMED CONTROL
ORGANIZATION
Control
External word
input
Next-address
Control address Control memory Control data
generator
register (ROM) register
(sequencer)

Next-address information
 Sequencer
• Determine the address sequence that is read from control
memory.
1.• Incrementing
Next addressthe
of the nextregister
control microinstruction
2. Loadingcanan be specified
address fromseveral
control
way depending
memory ontothe sequencer
CAR. input.
3. Loading an initial address

Functions:
1. Incrementing the control register
2. Loading an address from control memory to CAR.
3. Loading an initial address
Control Address Register
Specify the address of the microinstruction
 Control memory
(ROM)

• A memory is part of a control unit :

• Computer Memory (employs a microprogrammed control unit)
• Main Memory : for storing user program (Machine instruction/data)
• Control Memory : for storing microprogram (Microinstruction)
 Control data register
• Hold the present microinstruction while the next address is
computed & read from control memory.
1. Incrementing the control register 2. Loading an address from control
• Allows the execution
memory of the
to CAR. 3.microoperations specified
Loading an initial addressby the
control word simultaneously with the generation of the next
microinstruction. This requires two phase clock, with one clock
applied to add. Register and other to data register.
SELECTION OF
ADDRESS FOR
CONTROL MEMORY
MULTIPLEXERS

CAR INCREMENT

JMP/CALL

MAPPING

SUBROUTINE
RETURN
 CONTROL
ADDRESS
REGISTER
 CAR Receive The Address
from 4 Different Paths
Incrementer

Branch address from

control memory

Mapping Logic

SBR : Subroutine Register

 SUBROUTINE
REGISTER
(SBR)
• Return Address Can Not Be
Stored In ROM.
• Return Address For A
Subroutine Is Stored In SBR
CONDITIONAL
BRANCHING
If Condition is true,
then Branch (address from the next address field of the
current microinstruction)
else
Fall through

Conditions to test: O(overflow), N(negative),

Z(zero), C(carry) etc.

UNCONDITIONAL BRANCH

Fixing the value of one status bit at the input of the

multiplexer to 1.
MAPPING OF Machine
OP-code

1 0 1 1 Address
INSTRUCTION Instruction

Mapping bits 0 x x x x 0 0

Mapping from the OP-code of Microinstruction 0 1 0 1 1 0 0

an instruction to the address of address
the Microinstruction which is the
starting microinstruction of its  4 bit opcode = specify up to 16 distinct
execution microprogram instruction
 Mapping process : converts the 4-bit
opcode to a 7-bit control memory address
1) Place a “0” in the most significant bit of the
address.
2) Transfer 4-bit Operation code bits
3) Clear the two least significant bits of the
CAR
 Address
OP-codes of 0000 ADD Routine
Instructions
ADD 0000 AND Routine
0001
AND 0001 0010 LDA Routine
.
LDA 0010 . 0011 STA Routine
STA 0011 . 0100 BUN Routine
BUN 0100
Control
Mapping Function :
 Implemented by Mapping ROM or PLD. Storage
 A PLD is similar to ROM except that it uses AND and OR gates
with internal electronic fuses.
 The interconnection between AND, OR and outputs can be
programmed as in ROM

DIRECT MAPPING
MICROPROGRAM
EXAMPLE
COMPUTER CONFIGURATION

Two memory units:

Main memory, control memory.

CONTROL MEMORY :
• 4 registers are associated with
processor unit (PC,AR,DR,AC)
• 2 registers are associated with
the control unit (CAR,SBR)
MICROINSTRUCTION FORMAT
SYMBOLS BINARY FORMAT
SYMBOLS BINARY FORMAT
  Each line of the assembly language
microprogram defines a symbolic
microinstruction.
 Each symbolic microinstruction is divided
into five fields:

Labels
• The label field may be
empty or it may specify
SYMBOLIC a symbolic address.
• A label is terminated
MICRO- with a colon (:).

INSTRUCTIONS
  Each line of the assembly language
microprogram defines a symbolic
microinstruction.
 Each symbolic microinstruction is divided
into five fields:

Labels

Micro-ops • Consists of one, two or

three symbols
SYMBOLIC separated by comas

MICRO-
INSTRUCTIONS
  Each line of the assembly language
microprogram defines a symbolic
microinstruction.
 Each symbolic microinstruction is divided
into five fields:

Labels

Micro-ops
• Consists of one of the letters
U, I, S, Z
SYMBOLIC CD
Where U: Unconditional Branch
MICRO- I : Indirect address bit
S: Sign of AC
INSTRUCTIONS Z: Zero value in AC
  Each line of the assembly language
microprogram defines a symbolic
microinstruction.
 Each symbolic microinstruction is divided
intoLabels
five fields:

Micro-ops

CD

SYMBOLIC
BR • One of JMP, CALL, RET, MAP
MICRO-
INSTRUCTIONS
  Each line of the assembly language
microprogram defines a symbolic
microinstruction.
 Each symbolic microinstruction is divided
intoLabels
five fields:
Micro-ops

CD

SYMBOLIC BR

• One of Symbolic address,

MICRO- AD
NEXT,
empty
INSTRUCTIONS
The Fetch Routine
During FETCH, read an instruction from memory and decode the instruction and
update PC.

Microinstructions needed for the fetch routine: Symbolic Microprogram for fetch routine:

AR <- PC ORG 64
DR <-M[AR], PC <- PC + 1 PCTAR U JMP NEXT
AR <- DR(0-10), CAR(2-5) <- DR(l l-14), CAR(0, 1,6) <- READ,INCPC U JMP NEXT
0 DRTAR U MAP

Binary
Equivalents
Translated by an
Assembler
INDIRECT SUBROUTINE
SYMBOLIC
MICROPROGRAM
BINARY MICROPROGRAM
DESIGN OF
CONTROL UNIT
 The bits of microinstruction are
usually divided into fi elds, with each
fi eld defi ning a distinct, separate
function.
 The various fi elds available in the
instruction format provide control
bits to initiate the microoperation.

Decoding of Microinstruction Fields :

• F1, F2, and F3 of Microinstruction are decoded

with a 3 x 8 decoder
• Output of decoder must be connected to the
proper circuit to initiate the corresponding
microoperation
F1 = 101 (5) : DRTAR (The next clock pulse transition transfer the
content of DR(0 -10) to AR)
F1 = 110 (6) : PCTAR

• Output 5 and 6 of decoder F1 are connected to the load input of AR (two

input of OR gate)
• Multiplexer select the data from DR when output 5 is active
• Multiplexer select the data from AC when output 5 is inactive

Arithmetic Logic Shift Unit:

Instead of using the gates to generate the control signal marked by

AND, ADD, and DR Control signal will be now come from the output
of the decoders associated with the AND, ADD, and DRTAC
respectively.
PROGRAM
SEQUENCER
Microprogram sequencer select
the next address for control
memory
MUX 1 :
Selects an address from one of the four sources
and route to CAR
CAR + 1
JMP/CALL
Mapping
Subroutine Return

MUX 2:
• Test a status bit and the result of the test is
applied to an input logic circuit
• One of 4 Status bit is selected by Condition
bit (CD)
Input Logic
» Select one of the source address (S0 , S1) for CAR
» Enable the load input(L) in SBR
BR Load
FIELD Input MUX 1 SBR
Input Logic Truth Table:
I1 I0 T S1 S0 L
 Input :
0 0 0 0 0 0 0 0
> I0 , I 1 from Branch bit (BR )
> T from MUX 2 ( T) 0 0 0 0 1 0 1 0
 Output :
0 1 0 1 0 0 0 0
>MUX 1 Select signal ( S 0 , S 1 )
S1 = I 1 I0 ’ + I 1 I0 0 1 0 1 1 0 1 1
= I 1 (I0 ’ + I0)
=I1 1 0 1 0 X 1 0 0
S0 = I 1 ’ I0’T + I 1 ’ I0 T + I 1 I0 CALL
1 1 1 1 X 1 1 0
= I 1’T (I0 ’ + I0 ) + I 1 I0
= I 1 ’T + I 1 I0
>SBR Load signal ( L)
L = I 1’ I0 T
 REFERENCES

• Morris Mano
• SlideShare
THANK YOU