Verilator

Verilator converts synthesizable Verilog HDL modules into SystemC modules. This enables users with Verilog code to have a publicly available co-simulation environment. For all information, see http://www.veripool.com/verilator.html.

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License

Artistic License, GNU General Public License version 2.0 (GPLv2)

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Additional Project Details

Operating Systems

BSD, Linux, Windows

Languages

English

Intended Audience

Developers, End Users/Desktop

Programming Language

C++, Perl

Related Categories

Perl Compilers, Perl Electronic Design Automation (EDA) Software, C++ Compilers, C++ Electronic Design Automation (EDA) Software

Registered

2001-11-20

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