Semiconductor Science and Technology

ISSN: 1361-6641

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Semiconductor Science and Technology is IOP's journal dedicated to semiconductor research. The journal publishes cutting-edge research on the physical properties of semiconductors and their applications.

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Study of p-NiO_X/Ga₂O₃ high-voltage diodes
Jyotiranjan Sahoo et al 2026 Semicond. Sci. Technol. 41 085018
View article, Study of p-NiOX/Ga2O3 high-voltage diodes PDF, Study of p-NiOX/Ga2O3 high-voltage diodes
In a mesa-isolated diode, the aspect ratio plays a significant role in introducing the Trench MOS barrier Schottky (TMBS) effect, thus incorporating the reduced surface field (RESURF) effect. In this work, first, heterojunction diode structures based on Gallium oxide ( $\mathrm{Ga_2O_3}$ ) and p-type nickel oxide ( $\mathrm{NiO_\mathit{X}}$ ) are designed and analyzed using TCAD simulations. Two layers of p-type $\mathrm{NiO_\mathit{X}}$ of different doping concentrations in heterojunction diode design provide better field management and improved device consistency compared to its single-layer counterpart. $\beta-\mathrm{Ga_2O_3}$ based vertical heterojunction diodes are fabricated using sputtered $\mathrm{NiO_\mathit{X}}$ . The designed structure gives a breakdown voltage of 1.32 kV with an ON-resistance ( $R_\mathrm{ON}$ ) of 6 m $\Omega$ cm $^2$ . The fabricated large-area mesa-isolated multi-finger vertical heterojunction diodes exhibit an absolute forward ON-current ( $I_\mathrm{ON}$ ) above 1 A and reverse blocking voltage $\sim$ 850 V. The total anode area is 2 ${\text {mm}^2}$ while the fingers are 2 mm-long.The carrier concentrations in the 14 ${\text{nm}}$ -thick top layer and 7.5 ${\text{nm}}$ -thick bottom layer of $\mathrm{NiO_\mathit{X}}$ are 4–6 $\times 10^{16}$ ${\mathrm{cm}^{-3}}$ and 1.5 $\times 10^{18}$ ${\mathrm{cm}^{-3}}$ , respectively. $I_\mathrm{ON}$ further increases to $\sim$ 1.5 A at a forward bias of 4–6 V for large-area mesa-free heterojunction diodes. Achieving such a high forward current at low voltages is advantageous for reducing power losses and improving efficiency and stability during diode operation.
https://doi.org/10.1088/1361-6641/ae97fd
Improved rhombus weighted structure for spurious-free surface acoustic wave filter using LiNbO₃ thin plate
Peng Zhang and Hongliang Wang 2026 Semicond. Sci. Technol. 41 085017
View article, Improved rhombus weighted structure for spurious-free surface acoustic wave filter using LiNbO3 thin plate PDF, Improved rhombus weighted structure for spurious-free surface acoustic wave filter using LiNbO3 thin plate
The rapid development of mobile communication technology has led to the expansion of frequency spectrum bands and increased device heat generation, thus posing higher requirements on the performance of radio frequency devices. Shear horizontal surface acoustic wave (SAW) resonators exhibit a large bandwidth, but their practical applications are limited due to the influence of spurious modes. Therefore, this work focuses on achieving spurious-free resonators and filters. Firstly, based on the 64° YX-LiNbO₃/SiO₂/Si (64° YX-LN/SiO₂/Si) structure, the temperature compensation schemes and spurious mode suppression methods were investigated theoretically and experimentally. It is concluded that when h_LN/λ is 0.1 and hSiO₂/λ is 0.3, the suppression effect of Rayleigh mode and higher-order modes is relatively good. Subsequently, spurious-free SAW resonators and filters based on the improved rhombus structure were designed and fabricated. The resonators had a good suppression effect on spurious modes and maintained a high quality factor (Q) value. The filter exhibited wide bandwidth, low insertion loss and small temperature coefficient of frequency (TCF), with a nearly flat passband. It showed a center frequency (f_c) of 1215 MHz, 3 dB fractional bandwidth (FBW) of 16.5%, and exhibited TCF ranging from -32.6 ppm °C⁻¹ to -11.1 ppm °C⁻¹. In order to solve the problems of high-performance SAW devices, this work provides a scalable direction.
https://doi.org/10.1088/1361-6641/ae90dd
Physics-based modeling of SOI Schottky barrier FinFETs from room to cryogenic temperatures
Yijie Zhang et al 2026 Semicond. Sci. Technol. 41 085016
View article, Physics-based modeling of SOI Schottky barrier FinFETs from room to cryogenic temperatures PDF, Physics-based modeling of SOI Schottky barrier FinFETs from room to cryogenic temperatures
This work develops a comprehensive physics-based model for SOI Schottky barrier FinFETs, that accurately describes device behavior from room to cryogenic temperature. The model is based on a surface potential equation and integrates three transport mechanisms: thermionic field emission, field emission, and channel drift-diffusion. Furthermore, the model incorporates multiple temperature-dependent key parameters and physical effects, including intrinsic carrier concentration, effective mobility, Fermi level and Fermi potential, flat-band voltage, band-tail state, and interface states. Excellent agreement with experimental data confirms the model’s accuracy, across the linear and saturation regions at various temperatures. Analysis reveals the evolving dominance of different transport mechanisms across different bias and temperature regimes. The model enables the accurate capture of device behavior across temperatures through temperature-dependent parameters, offering a robust tool for cryogenic circuit design.
https://doi.org/10.1088/1361-6641/ae9637
Harnessing next-generation GaN semiconductors for the future of 6G communications: a review
Fayu Wan et al 2026 Semicond. Sci. Technol. 41 083001
View article, Harnessing next-generation GaN semiconductors for the future of 6G communications: a review PDF, Harnessing next-generation GaN semiconductors for the future of 6G communications: a review
Gallium nitride (GaN) is a wide-bandgap semiconductor with a 3.4 eV bandgap, a high critical breakdown field, high electron mobility and high saturation velocity. Those four properties are the physical basis of its high-frequency, high-efficiency behavior, and are the reason GaN is now considered candidate hardware for 6G radio front-ends. GaN high-electron-mobility transistors and monolithic microwave integrated circuits deliver high power at mm-wave and THz frequencies, which are needed for efficient power amplifiers and RF front-ends. Substrate choice sets the practical limits. GaN-on-Si is inexpensive, scalable and compatible with complementary metal-oxide-semiconductor processing; GaN-on-SiC gives the best balance of power, efficiency and reliability at mm-wave; GaN-on-Diamond gives the highest areal power density but is not yet manufacturable in volume. Packaging and thermal management matter as much as the transistor itself. Flip-chip bonding and device-embedded printed circuit board substrates cut parasitic inductance in high-frequency modules, and monolithic integration of power devices with control circuits is the direction of travel for compact GaN integrated circuits. This review follows one chain of reasoning: GaN material properties, then device-level RF metrics, then 6G system requirements. It also sets out what still blocks deployment. The main barriers are efficiency in the THz band, thermal management, heterogeneous integration and the shortage of reliability data under RF stress.
https://doi.org/10.1088/1361-6641/ae97fe
A dual-channel trench SiC MOSFET with a p-PolySi/n-SiC heterojunction tunneling channel realizing low R_on,sp and V_{r_on}
Bo Yi et al 2026 Semicond. Sci. Technol. 41 085015
View article, A dual-channel trench SiC MOSFET with a p-PolySi/n-SiC heterojunction tunneling channel realizing low Ron,sp and Vr_on PDF, A dual-channel trench SiC MOSFET with a p-PolySi/n-SiC heterojunction tunneling channel realizing low Ron,sp and Vr_on
A novel trench 4 H-SiC MOSFET integrating an n⁺-PolySi/p-PolySi/n-SiC sidewall heterojunction tunneling channel , named HTC-MOS, is proposed and investigated by calibrated TCAD simulation. In the proposed HTC-MOS, one channel is realized by n⁺-PolySi/p-PolySi/n-SiC. Under positive gate bias, the p-PolySi interface is inverted into an electron inversion layer and the n-SiC interface accumulates a large amount of electrons, which forms an n⁺-PolySi/n⁺-SiC interface enabling significant tunneling current across the heterojunction. This tunneling-induced current path and the traditional SiC inversion channel form a dual-channel conduction path that lowers the overall channel resistance. In the reverse free-wheeling state, the p-PolySi/n-SiC heterojunction ensures lower reverse on-state voltage drop (V_{R_on}) and reverse recovery charge (Q_rr) owing to unipolar conduction. Simulation results show that the 1.2 kV rated HTC-MOS achieves an R_on,sp of 1.46 mΩ·cm², reduced by 24.0% compared with that of a conventional device (R_on,sp = 1.92 mΩ·cm²). The V_{R_on} is reduced from 2.96 V – 1.82 V, representing a 38.5% reduction. Q_rr is reduced by 25.7%, which contributes to a 7.5% reduction in turn-on power loss.
https://doi.org/10.1088/1361-6641/ae98ab

The following article is Open access
Design of High-Speed Ge/GaAs Avalanche Photodiodes for Next-Generation Photonic Integration
Haifeng Kan et al 2026 Semicond. Sci. Technol.
View article, Design of High-Speed Ge/GaAs Avalanche Photodiodes for Next-Generation Photonic Integration PDF, Design of High-Speed Ge/GaAs Avalanche Photodiodes for Next-Generation Photonic Integration
We present the design and numerical simulation of a top-illuminated Ge/GaAs avalanche photodiode (APD) with a separate absorption, charge, and multiplication (SACM) structure operating at 1550 nm. The design targets a practical balance between high performance and low manufacturing cost for long-wavelength APDs. Leveraging high carrier mobility and the nearly lattice-matched Ge/GaAs interface, Ge/GaAs APDs provide a path to low-cost, monolithic integration of GaAs with silicon photonic platforms while meeting the demand for high-speed, low-noise photodetectors. Simulations indicate that a 10-μm-diameter device achieves >30 GHz 3-dB bandwidth, a ~224 GHz gain–bandwidth product, breakdown voltage of approximately -17 V, and low dark current (1.86 μA). These results highlight the strong potential of the Ge/GaAs platform for next-generation high-speed photodetectors.
https://doi.org/10.1088/1361-6641/ae9ee9
The following article is Open access
First-principles predictions of band alignment in strained Si/Si_1-xGe_x and Ge/Si_1-xGe_x heterostructures
Nathaniel M Vegh et al 2026 Semicond. Sci. Technol. 41 085012
View article, First-principles predictions of band alignment in strained Si/Si1-xGex and Ge/Si1-xGex heterostructures PDF, First-principles predictions of band alignment in strained Si/Si1-xGex and Ge/Si1-xGex heterostructures
Accurate band offsets are essential for predictive continuum modeling of nanostructures such as quantum wells and quantum dots formed in strained Si/Si $_{1-x}$ Ge $_x$ and Ge/Si $_{1-x}$ Ge $_x$ heterostructures. Experimental offset data for these systems remain sparse away from endpoint compositions, which makes composition-dependent design difficult. We use atomistic, first-principles density functional theory to compute valence- and conduction-band offsets across the full range $0\,{\unicode{x2A7D}}\,x\, {\unicode{x2A7D}}\,1$ . Random alloying is treated with special quasirandom structures, interface lineup terms are extracted from macroscopically averaged local Kohn–Sham potentials in thick periodic superlattices, valence-band spin–orbit coupling is included through species-resolved Mulliken weights, and conduction-band edges are refined using the screened hybrid Heyd–Scuseria–Ernzerhof functional. The resulting offsets show pronounced composition nonlinearity beyond the linear models explored in previous works, agree with experimental benchmarks, and reproduce the high-Ge slope change in the relaxed-alloy band gap. Analytic fitting expressions are provided for direct use in simulations, facilitating practical design of modern quantum technology devices.
https://doi.org/10.1088/1361-6641/ae949d
The following article is Open access
Simultaneous derivation of carrier mobility through admittance spectroscopy on MBE grown GaAs/Al_xGa_1−x as based solar cell device
Neslihan Ayarci Kuruoğlu 2026 Semicond. Sci. Technol. 41 085008
View article, Simultaneous derivation of carrier mobility through admittance spectroscopy on MBE grown GaAs/AlxGa1−x as based solar cell device PDF, Simultaneous derivation of carrier mobility through admittance spectroscopy on MBE grown GaAs/AlxGa1−x as based solar cell device
Using admittance spectroscopy, the dispersive transport mobilities of electrons and holes were simultaneously obtained from the distinct carrier transit times (τ_t) in the molecular beam epitaxy-grown GaAs/Al_xGa_1−xAs heterojunction-based solar cell device. The negative capacitance effect was attributed to the delayed response of injected carriers under forward-bias space-charge-limited conditions, where different electron- and hole-related transit times appear in different frequency regions of the C-log f characteristics when V_F exceeds approximately 1.2 V. For V_F < 1.2 V, i.e. below the built-in voltage (V_bi), the activation energy determined from the current density–voltage (J–V) characteristics was attributed to the hole energy barrier associated with the valence-band offset between p⁺–Al₀.₈₂Ga₀.₁₈As and p⁺–GaAs layers. This assignment is consistent with literature-based theoretical band-offset estimates and is also supported by the photoconductivity measurements.
https://doi.org/10.1088/1361-6641/ae9214
The following article is Open access
Self-compensation by silicon DX centers in ultrawide-bandgap nitrides
John L Lyons and Darshana Wickramaratne 2026 Semicond. Sci. Technol. 41 075017
View article, Self-compensation by silicon DX centers in ultrawide-bandgap nitrides PDF, Self-compensation by silicon DX centers in ultrawide-bandgap nitrides
DX behavior limits $n$ -type carrier concentrations in ultrawide-bandgap nitrides such as aluminum nitride (AlN) and cubic boron nitride ( $c$ -BN). Instead of acting as effective-mass donors, DX centers capture two electrons, stabilizing a negative charge state that leads to self compensation. Silicon is the most effective $n$ -type dopant in this class of materials; in AlN, its DX level [i.e. the (+/ $-$ ) transition level] is $\sim$ 270 meV from the conduction-band minimum. This implies that many silicon impurities incorporated into AlN will be negatively charged and compensate the intended $n$ -type doping. By combining density functional theory calculations of temperature-dependent band gaps and Si dopant transition levels, we show here that significant compensation occurs in silicon-doped AlN, even in the absence of any other defects. This compensation strongly limits free electron concentrations which become independent of doping concentration, and donor activation is only significant for light doping scenarios. Higher free carrier concentrations can be achieved in AlGaN alloys or in $c$ -BN, where the DX level sits closer to the conduction-band minimum.
https://doi.org/10.1088/1361-6641/ae8880
The following article is Open access
U-Net deep learning model for rapid identification of defects in SiC
James C Gallagher et al 2026 Semicond. Sci. Technol. 41 075016
View article, U-Net deep learning model for rapid identification of defects in SiC PDF, U-Net deep learning model for rapid identification of defects in SiC
Rapid wafer-scale defect identification and quantification are essential to achieve high yielding and reliable materials for device fabrication. Since defects are microscopic and the measurement scales are macroscopic, a quick, non-destructive automated process is needed to assess wafer quality. Although methods for wafer-scale defect visualization are well established, the appearance of defects can vary in size, shape, intensity, and signal to noise across a single sample. Using a traditional pattern matching technique would require extensive optimization, and if blind spots in the method were observed, corrections may be labor intensive to implement. This paper discusses using machine learning models to detect and classify defects in SiC and demonstrates that an implementation of the U-Net architecture is effective at identifying four types of critical defects in SiC with ultraviolet photoluminescence: stacking faults, polytype inclusions, threading screw/mixed dislocations, and basal plane dislocations. The resulting model can evaluate both 6-inch and 8-inch SiC wafers in minutes.
https://doi.org/10.1088/1361-6641/ae887e
The following article is Open access
Low frequency noise spectroscopy methodology for identifying traps located in the Si film of advanced mosfets
B Cretu et al 2026 Semicond. Sci. Technol. 41 075011
View article, Low frequency noise spectroscopy methodology for identifying traps located in the Si film of advanced mosfets PDF, Low frequency noise spectroscopy methodology for identifying traps located in the Si film of advanced mosfets
The low frequency noise spectroscopy theory for the identification of traps located in the depletion region of a field-effect transistor is reviewed. The hypothesis, which provides the generally accepted expression of the input-referred voltage noise power spectral density related to generation-recombination (GR) phenomena, is questioned. It is evidenced that the GR noise formulation should be revisited in order to be physically consistent and consequently the voltage GR noise plateau should include the impact of the ratio between the dynamic channel resistance and the dynamic total resistance. It is demonstrated that in order to maintain a lower shift of the quasi-Fermi level with the temperature in the strong inversion operation mode it is better to maintain a constant drain current polarization over the temperature range. Considering low frequency noise measurements performed in gate-all-around nano wire FET devices, it is also highlighted that performing only measurements over the temperature at fixed polarization is not enough to be able to properly estimate the identified trap parameters. The measurements for different polarizations at fixed temperature performed for all investigated temperatures are mandatory in order to gain a deeper insight, in particular concerning the ‘trapping’ GR noise phenomenon.
https://doi.org/10.1088/1361-6641/ae7b79
The following article is Open access
1200 V-class vertical GaN-on-GaN $p$ – $i$ – $n$ diodes with two-zone step-etched junction termination extension
Jarosł Tarenko et al 2026 Semicond. Sci. Technol. 41 075008
View article, 1200 V-class vertical GaN-on-GaN – – diodes with two-zone step-etched junction termination extension PDF, 1200 V-class vertical GaN-on-GaN – – diodes with two-zone step-etched junction termination extension
To fully realize the potential of vertical GaN power devices, proper junction termination methods are needed to reduce the electric field at the device periphery, leading obtaining breakdown voltage values as close as possible to the ideal values. Among these methods, the junction termination extension (JTE), fabricated using selective-area doping using ion implantation or by appropriate shaping of epitaxial p-type layers using plasma etching (step-etched JTE), has proven to be especially effective in obtaining high, robust, non-destructive, avalanche breakdown. However, more research is needed to fully demonstrate the effectiveness and usability of step-etched JTE structures for vertical GaN power devices, especially when supported by measurements of a large, statistically significant number of devices. In this work, we present the fabrication and characterization of 1200 V-class vertical GaN $p$ – $i$ – $n$ diodes with two-zone step-etched JTE structures. By varying the JTE thickness, a high breakdown voltage of over 1700 V and up to 1806 V was obtained, with a termination efficiency up to 91% ideal value. Moreover, an analysis of the measurement of a large number of fabricated devices was also presented, showing low statistical dispersion and tight distribution of breakdown voltage values.
https://doi.org/10.1088/1361-6641/ae8291
The following article is Open access
Impact of CMP surface quality and pre-epitaxial H₂ treatment on the surface defect mitigation and electrical characteristics of 6.5 kV SiC MOSFET
Chi-Hsiang Hsieh et al 2026 Semicond. Sci. Technol. 41 075007
View article, Impact of CMP surface quality and pre-epitaxial H2 treatment on the surface defect mitigation and electrical characteristics of 6.5 kV SiC MOSFET PDF, Impact of CMP surface quality and pre-epitaxial H2 treatment on the surface defect mitigation and electrical characteristics of 6.5 kV SiC MOSFET
This study presents a comprehensive investigation into the holistic process integration for manufacturing 6500 V 4 H-SiC power MOSFET, addressing the critical correlation between substrate surface quality, epitaxial growth integrity, and final device performance. We systematically evaluated the impact of Chemical Mechanical Planarization (CMP) slurry selection, demonstrating that optimizing abrasive electrostatics using core-shell particles significantly reduce residual contamination, thereby enhancing optical inspection accuracy. Furthermore, we verified the role of in-situ hydrogen (H₂) etching prior to epitaxy as a vital technological buffer, effectively mitigating CMP-induced scratches and preventing their propagation into the 63 μm thick drift layer required for ultra-high-voltage applications. The research culminated in the fabrication and characterization of 6500 V planar MOSFET on substrates subject to this defect mitigation process. Electrical measurements on devices located in scratch-mitigated regions revealed exceptional performance, achieving a breakdown voltage (V_BD) of 8310 V, substantially exceeding the nominal rating, and a specific on-resistance (R_on,sp) of 106 mΩ•cm2. The device achieved a breakdown voltage of 8310 V, which represents a remarkable 94.1% of the theoretical one-dimensional deep punch-through breakdown limit (8832 V), indicating that the device operates near the material’s physical ceiling. Crucially, the research confirms that the combination of optimized H₂ etching and thick epitaxial growth effectively isolates antecedent substrate defects from the active device region. These findings establish a robust pathway for high-yield SiC manufacturing by validating that finite substrate scratching is tolerable given effective epitaxial surface conditioning.
https://doi.org/10.1088/1361-6641/ae8292
The following article is Open access
Regrown quasi-vertical GaN-based p⁺-n Diode with CF₄-plasma and in-situ TMGa pretreatments
Qi Shu et al 2026 Semicond. Sci. Technol. 41 075006
View article, Regrown quasi-vertical GaN-based p+-n Diode with CF4-plasma and in-situ TMGa pretreatments PDF, Regrown quasi-vertical GaN-based p+-n Diode with CF4-plasma and in-situ TMGa pretreatments
This work reports on CF₄-plasma and in-situ TMGa treatments for the fabrication of etched-and-regrown quasi-vertical GaN p⁺-n diodes. The regrown p⁺-n diodes can suffer from high reverse leakage currents and premature breakdown directly related to electrically active states in the p–n junction region. The CF₄-plasma treatment prior to p-GaN regrowth effectively reduces leakage currents and improves breakdown voltage. However, CF₄-plasma treatment alone parasitically increases device resistance and limits the on-current. An additional in-situ TMGa preflow treatment prior to p-GaN regrowth is applied, restoring the forward characteristic. Using the combined CF₄-plasma and in-situ TMGa treatments prior to p-GaN regrowth, unetched planar-regrown p–n diodes with 2 µm n⁻-GaN drift layer achieve a breakdown voltage of −360 V, corresponding to a critical electric field of 1.9 MV cm⁻¹, close to that of continuously grown reference diodes (2.2 MV cm⁻¹). For etched-and-regrown p⁺-n diodes with a 4 µm n⁻-GaN drift layer, the median breakdown voltage is improved to approximately −450 V, compared with approximately −150 V for the untreated reference.
https://doi.org/10.1088/1361-6641/ae8293
The following article is Open access
Using of Boron-Rich Recycled Microplastics as a Dopant Source for p–n Junction Formation in Silicon
Melih Manir et al 2026 Semicond. Sci. Technol.
View article, Using of Boron-Rich Recycled Microplastics as a Dopant Source for p–n Junction Formation in Silicon PDF, Using of Boron-Rich Recycled Microplastics as a Dopant Source for p–n Junction Formation in Silicon
In this study, microplastic (MP) particles were used in the production of p–n junction devices, marking an important step in the recycling of these particles, which cause environmental pollution. The characteristic features of microplastics formed during the washing of textile materials in the first stage of the device formation were examined. Energy Dispersive Spectrum (EDS) analyses showed that the examined microplastic samples contained a rich Boron (B) content in their structures, originating from cleaning materials. X-ray diffraction (XRD) analysis revealed a mixed-phase structure with both crystalline and amorphous components, supporting the presence of boron-based compounds such as B₂O₃, H₃BO₃, and B₄C within the microplastic matrix. Optical absorption measurements demonstrated three major absorption bands, which support the presence of boron-based phases. The resistivity of the microplastic film on glass was measured by the four-point probe as 9.36105 -cm in the dark and 9.23105 -cm under illumination (100 mW/cm²). A p–n junction device with In-Ga/MP-derived p-Si/n-Si/Al configuration was successfully fabricated using a UV-assisted photoinduced diffusion method, which eliminates high-temperature processing and potential structural damage. The conductivity type of the MP-derived Si surface was investigated by hot-probe and Hall effect measurements, indicating the formation of p-type conductivity after the UV-assisted photoinduced diffusion process. The characteristic parameters of the device were determined from the current (I )– voltage (V) and capacitance (C)–voltage (V) measurements.. Dark I–V measurements showed that the samples illuminated for 30 and 60 min exhibited clear rectifying behavior characteristic of a p–n junction, whereas the control sample without UV illumination did not show rectification. In addition, capacitance–voltage (C–V) measurements revealed relatively high acceptor concentrations on the order of 1017 cm-3, which increased with prolonged UV illumination, suggesting enhanced boron incorporation into the Si surface.
https://doi.org/10.1088/1361-6641/ae7f44

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