[AMD]Clamp Results in Downcasting to FP8E4M3 and FP8E5M2 #7337
Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
antiagainst
requested changes
Jun 27, 2025
antiagainst
reviewed
Jun 27, 2025
antiagainst
approved these changes
Jun 27, 2025
tie-pilot-qxw
pushed a commit
to tie-pilot-qxw/triton
that referenced
this pull request
Aug 30, 2025
…g#7337) There are several conversion ops on the NV side using `satfinite` mode, but on the AMD side, some of those are in non-saturation mode. We need to align AMD ops with NV. For example, fp32 to OCP fp8 on mi350 is lowered to `ROCDL::CvtScaleF32PkFp8F32Op`, and is eventually lowered to `v_cvt_scalef32_pk_fp8_f32`, which, according to ISA, is in non-saturation mode. But on the NV side, it's lowered to `cvt.rn.satfinite.e4m3x2.f32`, which is in saturation mode. Other examples including: | Conversion | ROCDL dialect | Instruction | | ----------------- | ----------------------------- | -------------------------- | | fp32 to fp8e4m3fn | ROCDL::CvtScaleF32PkFp8F32Op | v_cvt_scalef32_pk_fp8_f32 | | fp32 to fp8e5m2 | ROCDL::CvtScaleF32PkBf8F32Op | v_cvt_scalef32_pk_bf8_f32 | | fp16 to fp8e4m3fn | ROCDL::CvtScaleF32PkFp8F16Op | v_cvt_scalef32_pk_fp8_f16 | | fp16 to fp8e5m2 | ROCDL::CvtScaleF32PkBf8F16Op | v_cvt_scalef32_pk_bf8_f16 | | bf16 to fp8e4m3fn | ROCDL::CvtScaleF32PkFp8Bf16Op | v_cvt_scalef32_pk_fp8_bf16 | | bf16 to fp8e5m2 | ROCDL::CvtScaleF32PkBf8Bf16Op | v_cvt_scalef32_pk_bf8_bf16 | This PR fixed this issue by enabling the `FP16_OVFL` flag in the Mode register before these conversion instrs. --------- Co-authored-by: ravil-mobile <ravil.aviva.com@gmail.com>
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
3 participants
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
Resolved https://github.com/ROCm/triton-internal/issues/849 and https://github.com/ROCm/triton-internal/issues/850.
There are several conversion ops on the NV side using
satfinitemode, but on the AMD side, some of those are in non-saturation mode. We need to align AMD ops with NV.For example, fp32 to OCP fp8 on mi350 is lowered to
ROCDL::CvtScaleF32PkFp8F32Op, and is eventually lowered tov_cvt_scalef32_pk_fp8_f32, which, according to ISA, is in non-saturation mode. But on the NV side, it's lowered tocvt.rn.satfinite.e4m3x2.f32, which is in saturation mode.Other examples including:
This PR fixed this issue by enabling the
FP16_OVFLflag in the Mode register before these conversion instrs.Created with @ravil-mobile