Skip to content
View stevej's full-sized avatar

Block or report stevej

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don't include any personal information such as legal names or email addresses. Markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
Showing results

Collateral for an AliExpress XCKU5P dev board

VHDL 10 Updated Apr 22, 2025

A configurable SRAM generator

Rust 56 7 Updated Aug 19, 2025

An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different manufacturers and models through parameter configuration.

Scala 21 3 Updated May 12, 2025

IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively supported.

Shell 736 118 Updated Dec 22, 2025

Opensource DDR3 Controller

Verilog 405 58 Updated Dec 31, 2025
Verilog 28 1 Updated Jan 14, 2025

Information Repository for Plexus Unix computers like the Plexus P/20

C 58 7 Updated Jul 2, 2024

The next generation of OpenLane, rewritten from scratch with a modular architecture

Python 326 72 Updated Dec 2, 2025
Jupyter Notebook 173 30 Updated Jul 24, 2023

Learn, share and collaborate on ASIC design using open tools and technologies

Dockerfile 14 1 Updated Dec 27, 2020

Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe

Python 102 6 Updated May 16, 2023

8 Bit CPU in Verilog created for TinyTapeout09, based on SAP-1 design with added Programmer Module

Python 6 3 Updated Apr 20, 2025

build a toolchain for cross developement. Supports motorola m68k-elf, avr and arm-none-eabi

Shell 30 5 Updated May 21, 2024

Sail RISC-V model

Sail 644 242 Updated Dec 30, 2025

Hardware Description Languages

1,089 103 Updated Jul 14, 2025

Documentation for RTL-with-customcells to GDSII

Verilog 6 1 Updated Oct 25, 2023

RISC-V hypervisor written in Rust

Rust 366 38 Updated Dec 18, 2019

Get detailed, per-pod network metrics for export to prometheus.

Go 1 Updated Mar 14, 2022

XLS: Accelerated HW Synthesis

C++ 1,406 220 Updated Jan 4, 2026

An SVG rendering library.

Rust 3,555 287 Updated Dec 21, 2025

DNS flag day

JavaScript 147 39 Updated Oct 12, 2022
Rust 4 1 Updated Oct 1, 2025

A collection of innocent cubes, to freak out your engine, or not. If not you may receive the "deccer-cubes-approval" role on our discord."

52 6 Updated Jan 19, 2025

Apache DataFusion SQL Query Engine

Rust 8,227 1,864 Updated Jan 4, 2026

Frequency modulation synthesizer plugin (VST2, CLAP). Runs on macOS, Windows and Linux.

Rust 760 21 Updated Jul 3, 2024

EasyNIC: an easy-to-use host interface for network cards

43 Updated May 30, 2018

A self-contained implementation of forward and backward inference for intuitionistic propositional logic

TeX 18 Updated Oct 10, 2017

Free monospaced font with programming ligatures

Clojure 80,841 3,174 Updated Dec 6, 2025

A Rust implementation of encoders and decoders for Protocol Buffers

Rust 7 1 Updated Oct 6, 2019
Next