A Modular Hardware Abstraction Library for Portable ASIC Design

Lambdalib is a modular hardware abstraction library which decouples design from the manufacturing target. The project was inspired by the Lambda concept invented during the 1978 VLSI revolution by Mead and Conway. Unfortunately, the elegant single value Lambda approach no longer applies to modern CMOS manufacturing. Lambdalib solves the scaling tech porting problem by raising the abstraction level to the cell/block level.

• Synchronizers, clock gating cells, and I/O pads are technology-specific
• Memory compilers generate different interfaces per foundry
• Analog blocks require complete redesign for each process
• Design teams waste months re-implementing the same functionality

Lambdalib provides technology-agnostic interfaces for all cells that can't be expressed in pure RTL:

• Write your design once using Lambdalib cells
• Target any supported technology through Lambdapdk
• Automatic porting between process nodes
• Proven in multiple production tapeouts

Lambdalib is organized into specialized sub-libraries, each addressing a specific design domain:

lambdalib/
├── stdlib/     # Standard digital cells (97 cells)
├── auxlib/     # Special-purpose cells (22 cells)
├── ramlib/     # Memory modules (6 modules)
├── iolib/      # I/O pad cells (16 cells)
├── padring/    # Padring generator (3 modules)
├── veclib/     # Vectorized datapath (15 cells)
├── fpgalib/    # FPGA primitives (3 cells)
└── analoglib/  # Analog circuits (2 modules)

Lambdalib cells are implemented for the following open source technologies through Lambdapdk, which provides:

• ASAP7
• FreePDK45
• IHP130
• Skywater130
• GF180MCU

1. One Verilog module per RTL file - Clean separation of concerns
2. One Python class per cell - Encapsulates Verilog and metadata
3. Consistent naming - RTL uses la_ prefix, Python removes it and capitalizes
4. Technology abstraction - Generic interfaces, technology-specific implementations
5. SiliconCompiler native - All cells are Design subclasses

git clone https://github.com/siliconcompiler/lambdalib
cd lambdalib
pip install -e .

Lambdalib cells are SiliconCompiler Design subclasses. Create your own design and add Lambdalib cells as dependencies:

from siliconcompiler import Design
from lambdalib.padring import Padring
from lambdalib.stdlib import Inv, Dffq
from lambdalib.ramlib import Dpram

class MyChip(Design):
    def __init__(self):
        super().__init__('mychip')

        # Set up your design files
        self.set_topmodule('mychip', 'rtl')
        self.add_file('rtl/mychip.v', 'rtl')

        # Add Lambdalib cells as dependencies
        self.add_depfileset(Padring(), depfileset='rtl', fileset='rtl')
        self.add_depfileset(Inv(), depfileset='rtl', fileset='rtl')
        self.add_depfileset(Dffq(), depfileset='rtl', fileset='rtl')
        self.add_depfileset(Dpram(), depfileset='rtl', fileset='rtl')

In your Verilog RTL, instantiate Lambdalib cells using the la_ prefix:

module mychip (
    input  clk,
    input  d,
    output q
);

    // Instantiate a D flip-flop
    la_dffq u_dff (
        .clk(clk),
        .d(d),
        .q(q)
    );

    // Instantiate a dual-port RAM
    la_dpram #(.DW(32), .AW(10)) u_ram (
        .clk(clk),
        // ... port connections
    );

endmodule

Generate a fileset and run synthesis with yosys. (or ideally, you should use the free and open source SiliconCompiler, but you do you;-).

if __name__ == "__main__":
    chip = MyChip()
    chip.write_fileset("mychip.f", fileset="rtl")
    # Run: yosys -f mychip.f

The foundation of digital logic design with optimized implementations for each target technology.

Special-purpose standard cells for clock management, synchronization, and power control.

Parameterizable memory generators with consistent interfaces across technologies.

Complete I/O pad library for chip periphery.

Automated padring generation with pure Verilog output.

Features:

• Pure Verilog parameterizable generator
• Support for all 4 sides (North/East/South/West)
• Differential pair handling
• Power section management
• 40-bit per-cell configuration

Bus-width scalable cells for efficient datapath design.

Building blocks for FPGA architectures.

Analog and mixed-signal building blocks.

We welcome contributions! Please see our GitHub Issues for tracking requests and bugs.

MIT License

Copyright (c) 2023 Zero ASIC Corporation

Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:

The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.