Skip to content
View shahzaibk23's full-sized avatar
💫
WORKING
💫
WORKING

Organizations

@merledu @10x-Engineers @OpenIntern @The-Nova-Project @TheOvalLabs

Block or report shahzaibk23

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don't include any personal information such as legal names or email addresses. Markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
shahzaibk23/README.md

👋 Hey, I'm Shahzaib Kashif

RISC-V Advocate • CPU Design & Verification Engineer • CHISEL Enthusiast

⚡ The Short Version

class ShahzaibKashif:
    def __init__(self):
        self.role = "RISC-V Advocate & CPU Design Engineer"
        self.location = "Karachi, Pakistan"
        pa
        self.interests = [
            "RISC-V ISA", "CHISEL HDL", "Open Source Hardware",
            "SoC Design", "FPGA/ASIC", "Making chips less scary"
        ]
        self.current_focus = "UCIe Protocol Verification"
        self.mentality = "If it's not open source, is it even real?"
    
    def say_hi(self):
        print("Thanks for stopping by! Star if you're team RISC-V ⭐")

💼 What I Actually Do

Role Company Focus
Design Verification Engineer 10xEngineers UCIe Protocol Verification
Ambassador CHERI Alliance Capability-based security
RISC-V Advocate RISC-V International Community & technical outreach
CPU Design Engineer Intensivate (ex) CHISEL, PCIe, debug modules
Research Associate MERL SoC design, Google MPW6 tape-out

🛠️ Stuff I'm Embarrassingly Good At


📦 Projects That Keep Me Up at Night

Project What It Does Tech Status
SoC Studio Cloud GUI for generating RISC-V SoCs (drag & drop, real-time sim, waveforms) CHISEL, React, Django 🔥 Active
SoC-Now Parameterized SoC generator with plug-and-play components CHISEL, Tilelink, Wishbone Production
Bitstream Chef EDA tool for rapid FPGA bitstream generation Python, F4PGA Cooking
Rocket Chip RE Reverse-engineered Rocket Chip into actual documentation RISC-V, Blood, Sweat Published

"I don't always write hardware, but when I do, I make sure it's parameterized."


🎤 Talks & Street Cred

Event Role Topic
CAMP-V Workshop Organizer & Host RISC-V architecture & ecosystem
RISC-V Karachi Meetup Co-Host Community building
RISC-V Summit Europe 2023 Presenter ChipShop
ASPLOS 2023 Workshop ChipShop
WOSET 2023 Poster SoC-Now + Bitstream Chef
RISC-V Summit NA 2020 Tutorial Reverse-engineering Rocket Chip

🏅 Badges of Honor

🏆 RISC-V Advocate (official, not just a vibe)
🏆 RISC-V Foundational Associate (RVFA)
🏆 RISC-V Fundamentals (LFD210)
🏆 LFX Mentorship (Spring'22, Spring'23) [Mentor]
🏆 Google Summer of Code (LiveHD)

📊 GitHub Statistics (The Boring but Important Part)


📫 Slide Into My DMs


⚡ "Open source hardware isn't just a movement, it's a lifestyle."

Pinned Loading

  1. Functional-Programming-Scala Functional-Programming-Scala Public

    This repo contains the content of Learning Journey # 02 ; Functional Programming with Scala

    Scala 1

  2. merledu/cachefy merledu/cachefy Public

    CHISEL API for plug n play connection of Caches in CHISEL designs

    Scala 3 1

  3. The-Nova-Project/Runtime-Drivers The-Nova-Project/Runtime-Drivers Public

    This Repo contains RUNTIME C Drivers for THE NOVA PROJECT

    C 1

  4. tinytapeout-barrel-shifter tinytapeout-barrel-shifter Public

    This repo contains Barrel Shifter made via GUI through TinyTapeout for MPW7 Shuttle :D

    Verilog 1 1

  5. The-Nova-Project/the-nova-project.github.io The-Nova-Project/the-nova-project.github.io Public

    Website for The Nova Project

    JavaScript

  6. masc-ucsc/livehd masc-ucsc/livehd Public

    Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

    C++ 233 56