Stars
Explainable Constraint Solving - A Hands-On Tutorial
A guidance language for controlling large language models.
We will build Tetris using logic design concepts (Hardware threads, 18-240 Lab 3b) on an Altera FPGA.
DSL and compiler framework for automated finite-differences and stencil computation
Pono: A flexible and extensible SMT-based model checker
The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.
Experiments with adding session types for hardware using magma
Python package for numerical derivatives and partial differential equations in any number of dimensions.
Intermediate Language (IL) for Hardware Accelerator Generators
"Multi-Level Intermediate Representation" Compiler Infrastructure
Build Customized FPGA Implementations for Vivado
A Just-In-Time Compiler for Verilog from VMware Research
C++ parsing library for simple formats used in logic synthesis and formal verification



