examples: convert to `wiring.Component`.

Release version 0.5.

hdl.mem: warn about indexing memories with a `Value`.

CI: automatically publish GitHub releases.

sim.pysim: Only close VCD/GTKW files if we opened them ourselves.

Fixes amaranth-lang#1107.

hdl._dsl: fix using 0-width `Switch` with integer keys.

Fixes amaranth-lang#1133.

Implement RFC 39: Warn on `Case()` and `matches()` with no patterns.

Implement RFC 5: Remove `Const.normalize`.

Closes amaranth-lang#754.

Release version 0.4.

setup: fix documentation URL for releases.