add TL-Verilog

.gitmodules

@@ -1035,6 +1035,9 @@
 [submodule "vendor/grammars/thrift.tmbundle"]
 	path = vendor/grammars/thrift.tmbundle
 	url = https://github.com/textmate/thrift.tmbundle
+[submodule "vendor/grammars/tlv-vscode"]
+	path = vendor/grammars/tlv-vscode
+	url = https://github.com/adamint/tlv-vscode
 [submodule "vendor/grammars/toml.tmbundle"]
 	path = vendor/grammars/toml.tmbundle
 	url = https://github.com/textmate/toml.tmbundle

grammars.yml

@@ -894,6 +894,8 @@ vendor/grammars/tcl.tmbundle:
 - text.html.tcl
 vendor/grammars/thrift.tmbundle:
 - source.thrift
+vendor/grammars/tlv-vscode:
+- source.tlverilog
 vendor/grammars/toml.tmbundle:
 - source.toml
 vendor/grammars/turtle.tmbundle:

lib/linguist/languages.yml

@@ -5670,6 +5670,13 @@ TI Program:
   - ".8xp.txt"
   language_id: 422
   tm_scope: none
+TL-Verilog:
+  type: programming
+  extensions:
+    - ".tlv"
+  tm_scope: source.tlverilog
+  ace_mode: verilog
+  language_id: 118656070
 TLA:
   type: programming
   extensions:

samples/TL-Verilog/calculator_kernel.tlv

@@ -0,0 +1,71 @@
+\m4_TLV_version 1d: tl-x.org
+\SV
+m4+definitions(['
+   m4_include_url(['https://raw.githubusercontent.com/stevehoover/makerchip_examples/ceebf870862e222ebc6eaf92d5a7fb85a525d069/1st-claas_template_with_macros.tlv'])
+'])
+m4_makerchip_module_with_random_kernel_tb(my, ['assign passed = cyc_cnt > 20;'])
+m4+definitions([''])  // A hack to reset line alignment to address the fact that the above macro is multi-line.
+\TLV
+   // A default direct hookup from |in to |out.
+   m4+tlv_wrapper(|in, @0, |out, @0, /trans)
+   |in
+      @0
+         $data[31:0] = >>1$output;
+      @1
+         // Calculator logic
+
+
+         // Extract input fields from input data
+         $val1[31:0] = >>1$output;
+         $val2[31:0] = /trans$data[31:0];
+         $op[2:0] = /trans$data[34:32];
+
+         //counter
+         $counter = $reset?0:(>>1$counter+1);
+         $valid = $reset || $counter;
+
+      ?$valid
+         @1
+            $sum[31:0] = $val1[31:0] + $val2[31:0];
+            $diff[31:0] = $val1[31:0] - $val2[31:0];
+            $mult[31:0] = $val1[31:0] * $val2[31:0];
+            $quot[31:0] = $val1[31:0] / $val2[31:0];
+             //@2
+            $mem[31:0] =
+               $reset ? 0:
+               ($op[2:0]==3'b101)
+                  ? >>1$mem[31:0] : >>1$output;
+
+
+            $output[31:0] =
+               $reset ? 0:
+               ($op[2:0]==3'b000)
+                  ? $sum[31:0] :
+               ($op[2:0]==3'b001)
+                  ? $diff[31:0] :
+               ($op[2:0]==3'b010)
+                  ? $mult[31:0] :
+               ($op[2:0]==3'b011)
+                  ? $quot[31:0] :
+               ($op[2:0]==3'b100)
+                  ? >>1$mem[31:0] : $val1[31:0];
+
+
+   |out
+      @0
+         // Hook up inputs to outputs to implement a no-op kernel.
+         // Delete this to add your kernel.
+         $ANY = /top|in<>0$ANY;
+
+         $ready = *out_ready;
+         *out_avail = $avail;
+         *out_data = $data;
+         //`BOGUS_USE($op $rand $ready)
+         `BOGUS_USE($ready)
+
+         // Extract output data to the output field
+         /trans@0$data = |in@1$output;
+
+   m4+rename_flow(/top, |in, @0, |out, @0, /trans)
+\SV
+   endmodule

samples/TL-Verilog/warp-v_config.tlv

@@ -0,0 +1,46 @@
+
+Viewed
+@@ -0,0 +1,43 @@
+\m4_TLV_version 1d: tl-x.org
+m4+definitions(['
+   // This file can be used to build a coarsely-configured implementation of WARP-V within makerchip.com.
+   // This enables exploration of a generated model (as TL-Verilog (without M4 macros) and/or Verilog/SystemVerilog).
+   // Simulation waveforms can be explored.
+   //
+   // High-level settings are described here. For detailed settings, consult the included warp-v.tlv file.
+
+
+   // -----------------------------------------------------------
+   // CONFIGURATION:
+
+   // ISA. Legal Values: [MINI, RISCV, MIPSI, POWER, DUMMY]
+   m4_define(M4_ISA, RISCV)
+
+   // Standard configuration. Legal Values: [1-stage, 4-stage, 6-stage, none (and define individual parameters)]
+   m4_define(M4_STANDARD_CONFIG, 4-stage)
+
+
+   // OPTIONAL CONFIGURATION:
+
+   // Branch predictor. Legal Values: [fallthrough, two_bit]
+   // m4_define(M4_BRANCH_PRED, fallthrough)
+
+
+   // DETAILED CONFIGURATION:
+
+   // (See included warp-v.tlv)
+
+   // -----------------------------------------------------------
+
+'])
+\SV
+   // Include WARP-V.
+   m4_include_lib(['https://raw.githubusercontent.com/stevehoover/warp-v/master/warp-v.tlv'])
+
+m4+module_def
+\TLV
+   m4+warpv()
+   m4+warpv_makerchip_cnt10_tb()
+   m4+makerchip_pass_fail()
+\SV
+   endmodule

vendor/README.md

@@ -442,6 +442,7 @@ This is a list of grammars that Linguist selects to provide syntax highlighting
 - **Svelte:** [umanghome/svelte-atom](https://github.com/umanghome/svelte-atom)
 - **Swift:** [textmate/swift.tmbundle](https://github.com/textmate/swift.tmbundle)
 - **SystemVerilog:** [TheClams/SystemVerilog](https://github.com/TheClams/SystemVerilog)
+- **TL-Verilog:** [adamint/tlv-vscode](https://github.com/adamint/tlv-vscode)
 - **TLA:** [agentultra/TLAGrammar](https://github.com/agentultra/TLAGrammar)
 - **TOML:** [textmate/toml.tmbundle](https://github.com/textmate/toml.tmbundle)
 - **TSQL:** [beau-witter/language-tsql](https://github.com/beau-witter/language-tsql)