Stars
RISC-V Sv39 Page Table Entry Visualization Tool
Pytorch Implementation of "Multi-Level Optimal Transport for Universal Cross-Tokenizer Knowledge Distillation on Language Models", AAAI 2025
Linux-capable out-of-order superscaler multicore LoongArch32 (LA32 / LA32R) processor.
Linux capable RISC-V SoC designed to be readable and useful.
This project aims to build an Embedded Linux System, in order to analyze the chip from the power-on execution of the first instruction to the entire system running, based on qemu simulator developm…
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
A simple full system emulator. Currently support RV64IMACSU and MIPS32 and LoongArch32. Capable of booting Linux. Suitable for education and research.
Basic systemverilog difftest environment for RTL design
Unofficial guide for ysyx students applying to ShanghaiTech University
verilog module add prefix script 可用于ysyx项目添加学号
16-bit CPU for Excel, and related files
A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
A chisel library for generate DPI-C bindings automatically
eBPF-based Linux high-performance transparent proxy solution.
How to make undergraduates or new graduates ready for advanced computer architecture research or modern CPU design
WoWs Info is an assistant for World of Warships
一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。