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asserBitVector add to Prelude.Testbench #891

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Merged
martijnbastiaan merged 1 commit into from
Nov 1, 2019
Merged

asserBitVector add to Prelude.Testbench #891

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17 changes: 17 additions & 0 deletions clash-prelude/src/Clash/Prelude/Testbench.hs
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Original file line number Diff line number Diff line change
Expand Up @@ -18,6 +18,7 @@ Maintainer : Christiaan Baaij <christiaan.baaij@gmail.com>
module Clash.Prelude.Testbench
( -- * Testbench functions for circuits
assert
, assertBitVector
, ignoreFor
, outputVerifier'
, outputVerifierBitVector'
Expand Down Expand Up @@ -69,6 +70,22 @@ assert msg actual expected ret =
hideReset (hideClock E.assert) msg actual expected ret
{-# INLINE assert #-}

-- | The same as 'assert', but can handle don't care bits in it's expected value.
assertBitVector
:: (KnownNat n, HiddenClock dom , HiddenReset dom )
=> String
-- ^ Additional message
-> Signal dom (BitVector n)
-- ^ Checked value
-> Signal dom (BitVector n)
-- ^ Expected value
-> Signal dom b
-- ^ Return value
-> Signal dom b
assertBitVector msg actual expected ret =
hideReset (hideClock E.assertBitVector) msg actual expected ret
{-# INLINE assertBitVector #-}

-- |
--
-- Example:
Expand Down