Seminar on field programmable gate array

SEMINAR ON
FIELD PROGRAMMABLE GATE ARRAY
PRESENTED BY :
SARANSH CHOUDHARY,
DEPARTMENT OF ECE, 3RD YEAR,
ROLL NUMBER : 11900314029
DEPARTMENT OF ECE, SIT
UNDER THE GUIDANCE OF :
DR. SUBHOJIT SARKER
DATE OF PRESENTATION :
20.05.2017

PRESENTATION OUTLINE
 INTRODUCTION
ARCHITECTURE OF FPGA
CASE STUDY
DSP USING FPGA
APPLICATIONS OF FPGA
CONCLUSION
REFERENCES

INTRODUCTION
 What is FPGA?
An FPGA(Field Programmable Gate Array) is a semiconductor device on which the function can
be defined after manufacturing. An FPGA enables the user to program product features and
functions, adapt to new standards, and reconfigure hardware for specific applications even after
the product has been installed in the field — hence the term field programmable. And gate
arrays are two-dimensional arrays of logic gates.

PROGRAMMABLE LOGIC DEVICE (PLD)
A Programmable Logic Device (PLD) refers to any type of integrated circuit through which a
logic design can be implemented and reconfigured in the field by the end user.
Inputs Outputs
The above figure shows the basic block diagram of PLDs. They have certain advantages, viz.,
Less board space and thus reduced cost
Increased processing speed
Availability of design software
4
AND Array OR Array

Programmable Logic
Device(PLD)
Simple
Programmable
Logic
Device(SPLD)
High Density
Programmable Logic
Device(HDPLD)
Complex
Programmable Logic
Device(CPLD)
Field Programmable
Gate Array(FPGA)
Programmable
Logic
Array(PLA)
Programmable
Array Logic(PAL)
THE PLD FAMILY
Programmable
Read Only
Memory(PROM)
5

NEED FOR FPGA
Systems based on FPGAs (Field Programmable Gate Arrays) provide many advantages over
conventional implementations, e.g., CPLD, some of which are:
Capacity
Storage of the image
Feature
Fast and efficient systems
Massively Parallel Data Processing
Owing to these advantages, FPGAs have established themselves as favourites for application in
manifold areas of technology ranging from Digital Signal Processing to Artificial Intelligence,
development of high speed communication networks ,etc. to mention a few.
6

ARCHITECTURE OF FPGA
The basic cell structure for FPGA is somewhat complicated than the basic cell structure of
standard gate array. The FPGA architecture consists of three types of configurable elements :
IOBs : a perimeter of input/output blocks
CLBs : a core array of configurable logic blocks
Programmable Interconnects
In general, FPGA chip consists of a large number of programmable logic blocks surrounded by
programmable I/O block, the logic blocks being distributed across the entire chip. In our
discussion we will see the FPGA architecture used by Xilinx.
7

The programmable logic blocks in the Xilinx family of FPGAs are called Configurable Logic
Blocks (CLBs).The Xilinx architecture uses, CLBs, I/O blocks, switch matrix and an external
memory chip to realize a logic function. The general structure of an FPGA chip is shown as
follows :
8
GENERAL STRUCTURE OF XILINX FPGA

 I/O BLOCK (IOB)
Each user-configurable IOB provides an interface between the external package pin of the device
and the internal user logic as well as a programmable 3-state output buffer, which may be driven
by a registered or direct output signal.
Configuration options allow each IOB
An inversion
A controlled slew rate
A high impedance pull-up
Each input circuit also provides input clamping diodes to provide electrostatic protection, and
circuits to inhibit latch-up produced by input currents.
9

I/O block of Xilinx XC3000 Series 10

Summary of I/O Options:
Inputs
Direct
Flip-flop/latch
CMOS/TTL threshold (chip inputs)
Pull-up resistor/open circuit
Outputs
 Direct/registered
 Inverted/not
 3-state/on/off
 Full speed/Slew limited
 3-state/output enable (inverse) 11

 CONFIGURATIONAL LOGIC BLOCK (CLB)
The array of Configurational Logic Blocks(CLBs) provides the functional elements from which the
user’s logic is constructed. Each CLB has a combinatorial logic section, two flip-flops, and an
internal control section. There are
five logic inputs (A, B, C, D and E)
a common clock input (K)
an asynchronous direct RESET input (RD)
an enable clock (EC)
a direct data in DI
two outputs X and Y
12

Block diagram of CLB of Xilinx XC3000 Series 13

 MODES
The combinatorial-logic portion of the CLB uses a 32 by 1 look-up table to implement Boolean
functions. Variables selected from the five logic inputs and two internal block flip-flops are used
as table address inputs.
The combinatorial propagation delay through the network is independent of the logic function
generated and is spike free for single input variable changes, which generates the following three
modes :
FG Mode F Mode FGM Mode 14

 PROGRAMMABLE INTERCONECTS
Programmable-interconnection resources in FPGA provide routing paths to connect inputs and
outputs of the IOBs and CLBs into logic networks.
Specially designed pass transistors, each controlled by a configuration bit, form Programmable
Interconnect Points (PIPs) and switching matrices used to implement the necessary connections
between selected metal segments and block pins.
Three types of metal resources are provided to accommodate various network interconnect
requirements :
General Purpose Interconnect
Direct Connection
Longlines (multiplexed buses and wide AND gates) 15

A Design Editor view of routing resources forming a typical interconnection network from CLB GA 16

 EXAMPLE : AND GATE USING FPGA
Although logic gates can be designed using Digital ICs (e.g., IC 7408 for 2-input AND gate), each
one of such ICs has a specific function. FPGA provides flexibility to implement any logic
function, as discussed in the following example :
Introduction to AND Gate
An AND gate is a logic gate which gives a high output when all of its inputs are high. Here the
truth table of a 2-input AND gate is shown along with its logic symbol.
17

Writing the code
The Verilog code for designing an AND gate is shown. Here a module named AND_Gate has been
written. Switches 1 and 2 are the inputs and the correct output is determined by the glow of LED
1.
18

Synthesizing the code
The synthesis of the code yields the following results. The usage report is inside the outer box (with solid
border), while the content inside the inner box gives the cell usage and total number of LUTs used ,i.e., 1.
Similarly, any Boolean function can be implemented following the above method. 19

CASE STUDY
One of the most important benchmarks in financial markets is the computation of option prices
via the Monte Carlo Black-Scholes method, The Monte Carlo Black-Scholes technique is based on
conducting random simulations of the underlying stock price and averaging the expected payoff
over millions of different paths. The accompanying figure shows a graphical representation of
this method.
The entire algorithm can be implemented in about 300 lines of OpenCL code that is portable
from an FPGA to a CPU and GPU. The FPGA solution outperforms both the CPU and GPU in
power, performance, and efficiency as shown in the next table.
20

FPGAs are inherently parallel — meaning they can be coded to break complex calculations into
computations that can be done in parallel. This results in much faster execution and increased
power efficiency and hence they’re highly favourable for wide applications.
Courtesy of Altera Corporation.
21
Platform Power
(Watts)
Performance
Simulations per
second(Bsims/s)
Efficiency Simulations
per second
Watt(Msims/s/W)
CPU 130 0.032 0.0025
GPU 212 10.1 48
FPGA 45 12.0 266

DSP USING FPGA
Why FPGA over DSP ?
Because of their size and the components they contain, FPGAs now offer a wide variety of
interesting possibilities in the field of digital signal processing. The difference between the
classical solution - using a Digital Signal Processor (DSP) - and implementation on an FPGA lies
in the fact that the DSP has to be programmed in Assembler or C whereas FPGA algorithms are
described in VHDL. While a DSP works through its program more or less sequentially, an FPGA
maps the entire algorithm at the hardware level.
22

EXAMPLE : THREE-BAND AUDIO EQUALIZER
In the brief example below, a three-band audio equalizer has been implemented on an FPGA. For
reasons of clarity, we use half-band filters in the equalizer algorithm. In this, a digital high-pass
(HP) and a digital low-pass (LP) each split the discrete-time input signal into two sub-bands. In
turn, the sum of the two sub-bands yields the input signal.
In MATLAB, it is possible to calculate this type of filter using just a few instructions:
% Buttworth low-pass filter with cut-off frequency w1:
[G_LP_num, G_LP_den] = butter(2, w1);
% Complement-res high-pass filter:
G_HP_num = G_LP_den - G_LP_num;
G_HP_den = G_LP_den;
The block diagram for the entire equalizer with two half-band filter stages is shown.
23

Fig. : Block diagram of Three-band digital equalizer
Each of the three bands is multiplied by a coefficient (K_Low, K_Mid and K_High). The output
signal y[.] is given by the sum of the three weighted sub-bands. If one of the coefficients is greater
than one then the corresponding band is amplified. If it is less than one, then the band is
attenuated.
24

The equalizer was developed, simulated and checked using MATLAB and Simulink. The next
stage represents the start of the actual FPGA design phase - it is necessary to verify that the
algorithm meets requirements even when calculations to bit accuracy are needed. To this end,
Xilinx offers a block set for Simulink. The number representations, word width, overflow and
rounding behaviour etc. of the relevant blocks are configurable and perform calculations to bit
accuracy.
It should be noted that an additional bit may arise when adding two fixed-point numbers.
Consequently, multiplication can lead to a result of almost double the length. So, the numbers
must be truncated or rounded off in an appropriate way during processing. Thanks to its
flexibility, the Xilinx block set is perfectly suited for this task.
At the end of this operation, the digital equalizer is present in the form of a Simulink model.
Because of the bit accuracy of the description, it behaves in exactly the same way as it is to
subsequently run on the FPGA.
25
TOOL CHAIN

GENERATING THE VHDL CODE
The second important feature of the Xilinx blocks is the fact that these blocks can be directly
converted into VHDL. This task is performed by the Xilinx System Generator. This does not just
convert the individual blocks but also the entire Simulink model from which it generates an
FPGA project folder. It should be noted that the System Generator is only able to convert blocks
from the Xilinx block set. The IIR Filter in Simulink looks as follows :
26

The above diagram depicts a half-band filter created using Xilinx blocks. Here, it is seen that the delay
networks that are typical of IIR filters (at the extreme left and right) together with five multipliers and four
adders. The System Generator will subsequently recognize the multipliers and assign them to the hardware
multipliers present on the selected chip.
Following figure presents the menu for a multiplier. The top four boxes relate to the numerical
presentation and word width. In signal processing applications it is normal to represent numbers as two's
complements and in fraction format. The next two boxes control the way the result value is delimited on
the left and right sides. A number of rounding approaches are possible for the right-hand side. All the other
parameters refer to the VHDL generation.
27

SUMMARY
The following table indicates the equalizer's occupancy of a Xilinx XC2V1000-4FG456C FPGA.
This makes it clear that the selected FPGA is more than generously sized for a single equalizer.
Flip-flops were primarily used for the serial interface and for shift registers. Look-up tables are
used when adding the filters.
28

The design presented here is completely parallel, with the result that an output value is calculated
in every FPGA clock cycle. However, to achieve this, the equalizer occupies 20 of the 40 available
18x18-bit multipliers on the chip.
The data rate, in particular, indicates the phenomenal arithmetic performance offered by today's
FPGAs. The equalizer presented here processes 18 k samples per second. The FPGA's limit is
approximately 80 internal logical layers at slightly more than 10 MHz. If adapted correctly, our
equalizer would therefore be able to cope with more than 500 audio channels.
29

APPLICATIONS OF FPGA
FPGA
Switches and
Routers,
Edge QAM
Digital Signal
Processing,
Image Processing
PLL,
Missiles
MRI,
X-Rays,
CT Scanner Supercomputer,
High end RADAR
Baseband,
Mobile
Backhaul,
Servers
30

CONCLUSION
With rapid advancement in contemporary technology, there has been an ever-increasing need for
faster data processing, more and more compact hardware and multi-dimensional functionalities
of modern devices and FPGAs emerge out to be the perfect candidates for varied
implementations across diverse domains of technology. From implementation of simple Boolean
functions to complex algorithms with significant time efficiency or Image Processing, Artificial
Intelligence and Wireless Communications, FPGAs have opened an all new horizon to be
explored in various fields of science and technology. With unprecedented development in VLSI
technology, the real potential of this class of logic devices has been unearthed and it provides
even brighter prospects for future .
31

REFERENCES
FPGAs for Dummies by Andrew Moore (Altera Special Edition, Wiley & sons Inc.)
Xilinx datasheet for XC3000 Series Field Programmable Gate Arrays(November
9,1998,Version 3.1)
Google
Wikipedia
FPGA Central
Quora

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