OIF CEI 56-G-FOE-April2015
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The document outlines the specifications and applications of the OIF CEI-56G electrical interfaces, including various configurations like usr, xsr, vsr, mr, and lr, with a focus on port density requirements. It discusses test results for nrz and pam4 signaling methods, highlighting the advantages and disadvantages of each in terms of performance and implementation. The OIF is actively defining solutions for future electrical interfaces, with both nrz and pam4 specifications being developed for these applications.
OIF CEI 56-G-FOE-April2015
- 1. OIF CEI-56G Common Electrical Interfaces Tom Palkert Luxtera/MoSys OIF PLL Vice Chair Electrical Tom Palkert Luxtera/MoSys OIF PLL Vice Chair Electrical
- 2. Outline Port Density Requirements OIF CEI-56G applications • USR (die to die in an MCM) • XSR (Chip to optical engine/memory) • VSR (Chip to Pluggable module) • MR (Chip to Chip) • LR (Backplane) NRZ and PAM4 test and simulation results NRZ vs PAM4 arguments Conclusion 2 FOE 2015 Port Density Requirements OIF CEI-56G applications • USR (die to die in an MCM) • XSR (Chip to optical engine/memory) • VSR (Chip to Pluggable module) • MR (Chip to Chip) • LR (Backplane) NRZ and PAM4 test and simulation results NRZ vs PAM4 arguments Conclusion
- 3. Port density requirements for Data Centers de RJ-45 – 48 Channels 10GBaseT = 480 Gbps SFP+ – 48 Channels 50G = 2.7 Tbps Channels/Bandwidth 3 FOE 2015 iPass – 160 Channels QSFP 144 Channels 50G = 7.2 Tbps CXP – 320 Channels 50G = 16 Tbps
- 4. OIF CEI Interfaces for 56G LR MR Switch card XSR USR 4 FOE 2015 VSR MR XSR USR
- 5. CEI-56G-USR Key specifications for USR • 10mm trace length • DC coupled • Common clock • Low voltage swing HOST LSI PCB LSI_PKG HOST LSI LSI_PKG Memory IC MCM with memory IC 5 FOE 2015 Key specifications for USR • 10mm trace length • DC coupled • Common clock • Low voltage swing Optical I/O core HOST LSI Driver IC Mod Optical I/O LSI_PKG Si-photonics chip PCB MCM with OPTICAL ENGINE
- 6. CEI-56G-XSR Key specifications for XSR • 50-100mm trace length • DC coupled • Common clock • Low voltage swing 6 FOE 2015 XSR interop points ASIC Optical Engine or Memory device Optical Fiber Key specifications for XSR • 50-100mm trace length • DC coupled • Common clock • Low voltage swing
- 7. NRZ SIMULATIONS for 56G XSR 7 FOE 2015
- 8. PAM4 XSR simulations RxS eye at slicer (post 3.5dB CTLE) Tx swing 400mVpp 8 FOE 2015 EW = 0.38 UI EH= 45 mV (for case Including 3dB total package losses) Tx eye at package
- 9. CEI-56G-VSR Key specifications for VSR • 100mm trace length • One connector • Uses a test/compliance board to measure host and module waveforms Optical Module Module connector 9 FOE 2015 Key specifications for VSR • 100mm trace length • One connector • Uses a test/compliance board to measure host and module waveforms Host PCBA Optical Module Interoperability point Chip Module connector AC coupling capacitor
- 10. CEI-56G-VSR candidate channel Channel includes: • Package model • RX input termination capacitance • VSR (QSFP) connector model 10 FOE 2015 Channel includes: • Package model • RX input termination capacitance • VSR (QSFP) connector model
- 11. CEI-56G-VSR-NRZ eye diagram Note: simulations included: - RX jitter and package -3mv rms input noise -TX jitter 11 FOE 2015 Courtesy: MoSys
- 12. VSR PAM4 simulation results 12 FOE 2015
- 13. VSR NRZ test results 13 FOE 2015 Courtesy Credo Semiconductor
- 14. VSR-PAM4 test results 14 FOE 2015
- 15. CEI-56G-MR TX RX Key specifications for MR • 500mm trace length • Zero or One connector • Compliance uses COM code 15 FOE 2015 Chip to Chip interop points AC coupling capacitor MR
- 16. MR channel for NRZ testing 16 FOE 2015
- 17. NRZ test results for MR channel 17 FOE 2015 NRZ test results for MR channel
- 18. MR measured results PAM4 18 FOE 2015
- 19. CEI-56G-LR Key specifications for LR • 1000mm trace length • Two connectors 19 FOE 2015
- 20. LR measured results NRZ 20 FOE 2015 Courtesy: Credo Semiconductor
- 21. LR NRZ Measured results 21 FOE 2015 Courtesy: Credo Semiconductor
- 22. LR PAM4 Measured Results Design Con 2015 demos 22 FOE 2015 Parthasarathy_3bs_01_0315
- 23. Why NRZ over PAM4? PAM4 has a 9dB SNR penalty • 3 PAM4 eyes in the same voltage swing as 1 NRZ eye • VSR channel shows an 8-9dB difference NRZ has more equalization techniques that can be used before we move to PAM4 • Higher gain CTLE • DFE • TX equalization Low cost/Low loss Printed circuit board materials are available 23 FOE 2015 PAM4 has a 9dB SNR penalty • 3 PAM4 eyes in the same voltage swing as 1 NRZ eye • VSR channel shows an 8-9dB difference NRZ has more equalization techniques that can be used before we move to PAM4 • Higher gain CTLE • DFE • TX equalization Low cost/Low loss Printed circuit board materials are available
- 24. Why PAM4 over NRZ? As process nodes get smaller density is increasing but not speed • PAM designs can use lower cost semiconductor processes PAM operates over legacy channels • Same baud rate as 28G NRZ Lower loss channels may not require as much equalization as NRZ 24 FOE 2015 As process nodes get smaller density is increasing but not speed • PAM designs can use lower cost semiconductor processes PAM operates over legacy channels • Same baud rate as 28G NRZ Lower loss channels may not require as much equalization as NRZ
- 25. Conclusions 1) The OIF is defining solutions for the next generation electrical interfaces 2) Both NRZ and PAM4 specifications are being developed for CEI-56G solutions 25 FOE 2015