AVR Family of Micro-Controllers
What is AVR ?
Modified Harvard architecture 8-bit RISC single chip microcontroller Complete System-on-a-chip
On Board Memory (FLASH, SRAM & EEPROM) On Board Peripherals
Advanced (for 8 bit processors) technology Developed by Atmel in 1996 First In-house CPU design by Atmel
AVR Family
8 Bit tinyAVR
Small package as small as 6 pins
8 Bit megaAVR
Wide variety of configurations and packages
8 / 16 Bit AVR XMEGA
Second Generation Technology
32 Bit AVR UC3
Higher computational throughput
Harvard Architecture
Harvard Architecture Advantages
Separate instruction and data paths Simultaneous accesses to instructions & data Hardware can be optimized for access type and bus width.
AVR Architecture
Modified Harvard Architecture
Special instructions can access data from program space. Data memory is more expensive than program memory Dont waste data memory for non-volatile data
What is RISC?
Reduced Instruction Set Computer As compared to Complex Instruction Set Computers, i.e. x86 Assumption: Simpler instructions execute faster Optimized most used instructions Other RISC machines: ARM, PowerPC, SPARC Became popular in mid 1990s
Characteristics of RISC Processors
Faster clock rates Single cycle instructions (20 MIPS @ 20 MHz) Better compiler optimization
AVR Register File
32 8 Bit registers Mapped to address 0-31 in data space Most instructions can access any register and complete in one cycle Last 3 register pairs can be used as 3 16 bit index registers 32 bit stack pointer
Register File
7 0
addr 0x00 0x01 0x02 0x03 0x04 0x05
R0 R1 R3 R4 R5 R6 R26 R27 R28 R29 R30 R31
0x1A 0x1B 0x1C 0x1D 0x1E 0x1F
x register low byte x register high byte y register low byte y register high byte z register low byte z register high byte
AVR Memory
FLASH
Non-volatile program space storage 16 Bit width Some devices have separate lockable boot section At least 10,000 write/erase cycles
AVR Memories
FLASH Memory Map
ATmega 48
0x000
ATmega 88/168/328
0x000
Application Flash
Application Flash
0x7FF
Boot Flash
0x1FFF 0x3FFF 0x7FFF
AVR Memories
SRAM
Data space storage 8 Bit width
AVR Memories
SRAM - Memory Map
32 Registers 64 I/O Registers 160 External I/O Reg Internal SRAM (512/1024/2048x8)
0x0000 0x001F 0x0020 0x005F 0x00060 0x00FF 0x0100
0x04FF/0x6FF/0x8FF
External SRAM
AVR Memories
EEPROM Electrically Erasable Programmable Read Only Memory 8 bit width Requires special write sequence Non-volatile storage for program specific data, constants, etc. At least 100,000 write/erase cycles
AVR Memories
DEVICE
ATmega48A ATmega48PA ATmega88A ATmega88PA ATmega168A ATmega168PA ATmega328
FLASH
4K Bytes 4K Bytes 8K Bytes 8K Bytes 16K Bytes 16K Bytes 32K Bytes
EEPROM
256 Bytes 256 Bytes 512 Bytes 512 Bytes 512 Bytes 512 Bytes 1K Bytes
SRAM
512 Bytes 512 Bytes 1K Bytes 1K Bytes 1K Bytes 1K Bytes 2K Bytes
ATmega328P
32K Bytes
1K Bytes
2K Bytes
Memory Mapped I/O Space
I/O registers visible in data space
I/O can be accessed using same instructions as data Compilers can treat I/O space as data access
Bit manipulation instructions
Set/Clear single I/O bits Only work on lower memory addresses
ALU Arithmetic Logic Unit
Directly connected to all 32 general purpose registers Operations between registers executed within a single clock cycle Supports arithmetic, logic and bit functions On-chip 2-cycle Multiplier
Instruction Set
131 instructions
Arithmetic & Logic Branch Bit set/clear/test Data transfer MCU control
Instruction Timing
Register register in 1 cycle Register memory in 2 cycles Branch instruction 1-2 cycles Subroutine call & return 3-5 cycles Some operations may take longer for external memory
Pipelined Execution
AVR Clock System
Clock control module generates clocks for memory and IO devices Multiple internal clock sources Provisions for external crystal clock source (max 20 MHz) Default is internal RC 8 MHz oscillator with 8 prescale yielding 1 MHz CPU clock
Clock Sources
Timer/Counter Oscillator Timer/ Counters Crystal Oscillator IO Modules
ADC External Clock
Clock Mux
System Clock Prescaler
AVR Clock Control
CPU Core
Low Freq Crystal Oscillator
8
RAM
Calibrated RC Oscillator
FLASH & EEPROM
Power Management
Multiple power down modes
Power down mode
Wake on external reset or watchdog reset
Power save mode
Wake on timer events
Several standby modes
Unused modules can be shut down
Reset Sources
Power on reset External reset Watchdog system reset Brown out detect (BOD) reset
23 General Purpose IO Bits Two 8 bit & one 16 bit timer/counters Real time counter with separate oscillator 6 PWM Channels 6 or 8 ADC channels (depends on package) Serial USART SPI & I2C Serial Interfaces Analog comparator Programmable watchdog timer
ATmega Peripherals
General Purpose IO Ports
Three 8 Bit IO Ports
Port B, Port C & Port D Pins identified as PBx, PCx or PDx (x=0..7)
Each pin can be configured as:
Input with internal pull-up Input with no pull-up Output low Output high
Alternate Port Functions
Most port pins have alternate functions Internal peripherals use the alternate functions Each port pin can be assigned only one function at a time
Alternate Pins for PDIP Package
Atmega 16 Block Diagram
Instruction Set
