Microprocessor Architecture
Syllabus
Unit 1
● History of Intel Processor:
https://www.meridianoutpost.com/resources/articles/timeline-Intel-processor-h
istory.php
● Basics of microprocessor
○ Computer System
Introduction to 80386
● Also known as i8386,
● Developed by intel
● Part of intel x86 family
● Introduced in 1985 as a successor to 80286 processor.
● 2 versions are available:
○ 80386DX
○ 80386SX
80386DX
● DX:'DX' stood for 'Double word eXternal' referring to the 32-bit external bus
allowing faster data transfer between processor and other components in the
system.
● It is more powerful and fully featured version of 80386.
● Supports both 32-bit and 16-bit external data bus.
● Commonly used in high performance desktop and server systems.
80386SX
● SX:'DX' stood for 'Single word eXternal' referring to the 16-bit external bus
which leads to slower data transfer between processor and other components as
compared to DX.
● Supports 16-bit external data bus only.
● Mainly designed for budget friendly systems i.e used in mid-range or lower end
desktop computers.
Features of 80386
● 32 bit processor, it has 32 bit ALU which allows to process 32 bit data at a
time.
● 32 bit address bus, therefore it can access 4GB physical memory and 64
Terabytes of Virtual memory.
● It has pipeline architecture which allows simultaneous instruction fetching,
decoding, and executing and memory management.(3 stage pipeline)
● It allows user to switch between different OS such as DOS and UNIX
● Operates in Real, Protected and Virtual 8086 mode.
Features of 80386
● It compatible with 8086, 8088, 80186, 80286 architecture.
● It has different data types like bits, byte, word, double word, Quadword,
(signed and unsigned form).
● It has Separate pins for its address and data line, this result in higher
performance and easier hardware design.
● Prefetch unit permits to prefetch up to 16 bytes of instruction code.
● Therefore fetch time for most instruction is hidden, increase the
performance.
Memory Organisation
Flat mode
Segmented mode
Architecture of 80386
1. Bus Interface Unit(BIU)
● The bus interface unit or BIU holds
a 32-bit bidirectional data bus as
well as a 32-bit address bus.
● Whenever a need for instruction or
a data fetch is generated by the
system, then the BIU generates
signals (according to the priority)
for activating the data and address
bus in order to fetch the data from
the desired address.
● The BIU connects the peripheral
devices through the memory unit
and also controls the interfacing of
external buses with the
coprocessors.
2. Code Prefetch Unit
● This unit fetches the instructions stored
in the memory by making use of
system buses.
● Whenever the system generates a
need for instruction then the code
prefetch unit fetches that instruction
from the memory and stores it in a 16-
byte prefetch queue.
● So to speed up the operation this unit
fetches the instructions in advance and
the queue stores these instructions.
● The sequence in which the instructions
are fetched and gets stored in the
queue depends on the order they exist
in the memory.
3. Instruction Decode Unit
● We know that instructions in the
memory are stored in the form of
bits.
● So, this unit decodes the
instructions stored in the
prefetch queue.
● Basically the decoder changes
the machine language code into
assembly language and
transfers it to the processor for
further execution.
4. Execution Unit
● The decoded instructions are stored in
the decoded instruction queue.
● So, these instructions are provided to
the execution unit in order to execute
the instructions.
● The execution unit controls the
execution of the decoded instructions.
● This unit has a 32- bit ALU, that
performs the operation over 32-bit data
in one cycle.
● Also, it consists of 8 general purpose
as well as 8 special purpose registers.
● These are used for data handling and
calculation of offset address.
5. Memory Management Unit
● This unit has two separate units within it.
● These are
○ 1.Segmentation Unit and
○ 2.Paging Unit
● Segmentation unit:
● The segmentation unit plays a vital role
in the 80836 microprocessor.
● It offers a protection mechanism in order
to protect the code or data present in
the memory from application programs.
● It gives 4 level protection to the data or
code present in the memory.
● Every information in the memory is
assigned a privilege level from PL0 to
PL3.
● Here, PL0 holds the highest priority and
PL3 holds the lowest priority.
Operating modes of 80386
● 80286 supports two operating modes. The first is real address mode while the
second is the protected virtual address mode. However, 80386 supports 3
operating modes: real, protected, and virtual real mode.
● Requires the resetting of the microprocessor in order to switch to real mode
from protected mode. This drawback was eliminated in 80386 that allows the
switching between the modes using software commands.
Operating modes of 80386
● 80286 supports two operating modes. The first is real address mode while
the second is the protected virtual address mode. However, 80386 supports 3
operating modes: real, protected, and virtual real mode.
● Requires the resetting of the microprocessor in order to switch to real mode
from protected mode. This drawback was eliminated in 80386 that allows
the switching between the modes using software commands.
Address Generation
Virtual 80386 mode
Register Organization
System Registers(i386)
