AXI Timer in
ZYNQ
Zaid A. Abdulrazzaq
ZC702 Evaluation Board
Source: ZC702 Evaluation Board Reference Manual
A Simplified Model of the Zynq Architecture
Source: The Zynq Book
Mapping of an Embedded SoC
Hardware Architecture to Zynq
Source: Xilinx White Paper: Extensible Processing Platform
AXI Timer
Functions of a Typical Timer (1)
1. Generating delays - imposing a specific delay
between two points in the program
label 1 instr1
instr2
delay
label2 instrN
Functions of a Typical Timer (2)
2. Output compare - generating signals with the given
timing characteristics
single pulse periodical signal
pulse width period
Functions of a Typical Timer (3)
3. Input capture - measuring the time between signal
edges
start stop
start stop
Block Diagram of AXI Timer
Source: LogiCORE IP AXI Timer: Product Guide
AXI Timer: Modes of Operation
• Generate Mode
• Capture Mode
• Pulse Width Modulation Mode
• Cascade Mode
Generate Mode
• Counter when enabled begins to count up or down
• On transition of carry out, the counter
• stops, or
• automatically reloads the initial value from the load register,
and continues counting
• if enabled, GenerateOut is driven to 1 for one clock cycle
• if enabled, the interrupt signal for the timer is driven to 1
• Can be used to
• Generate repetitive interrupts
• One-time pulses
• Periodical signals
Capture Mode
• The counter can be configured as an up or down counter
• The value of the counter is stored in the load register when
the external capture signal is asserted
• The TINT flag is also set on detection of the capture event
• The Auto Reload/Hold (ARHT) bit controls whether the
capture value is overwritten with a new capture value
before the previous TINT flag is cleared
• Can be used to measure
• Widths of non-periodical signals
• Periods of periodical signals
• Intervals between edges of two different signals, etc.
Pulse Width Modulation (PWM) Mode
• Two timer/counters are used as a pair to produce an output
signal (PWM0) with a specified frequency and duty factor
• Timer 0 sets the period
• Timer 1 sets the high time for the PWM0 output
• Can be used to generate
• Periodical signals with varying period and duty cycle
Cascade Mode
• Two timer/counters are cascaded to operate as
a single 64-bit counter/timer
• The cascaded counter can work in both generate
and capture modes
• TCSR0 acts as the control and status register for the
cascaded counter. TCSR1 is ignored in this mode.
• Can be used to
• Generate longer delays
• Generate signals with larger pulse widths or periods
• Measure longer time intervals
Timer/Counter Register, TCR0, TCR1
Source: LogiCORE IP AXI Timer: Product Guide
Load Register, TLR0, TLR1
Control/Status Registers, TCSR0
Source: LogiCORE IP AXI Timer: Product Guide
Control/Status Register 0, TCSR0
Control/Status Registers, TCSR0
Control/Status Register 0, TCSR0
Control/Status Registers, TCSR0
Source: LogiCORE IP AXI Timer: Product Guide
Control/Status Register 0, TCSR0
Source: LogiCORE IP AXI Timer: Product Guide
Control/Status Registers, TCSR0
Source: LogiCORE IP AXI Timer: Product Guide
Control/Status Register 0, TCSR0
Source: LogiCORE IP AXI Timer: Product Guide
Class Exercise 2:
Modifying a Counter Using
AXI Timer
(every N ms)
C Program (1)
#include "xparameters.h"
#include "xgpio.h"
#include "xtmrctr.h"
#include "xscugic.h"
#include "xil_exception.h"
#include "xil_printf.h"
// Parameter definitions
#define INTC_DEVICE_ID XPAR_PS7_SCUGIC_0_DEVICE_ID
#define TMR_DEVICE_ID XPAR_TMRCTR_0_DEVICE_ID
#define BTNS_DEVICE_ID XPAR_AXI_GPIO_0_DEVICE_ID
#define LEDS_DEVICE_ID XPAR_AXI_GPIO_1_DEVICE_ID
#define INTC_GPIO_INTERRUPT_ID
XPAR_FABRIC_AXI_GPIO_0_IP2INTC_IRPT_INTR
#define INTC_TMR_INTERRUPT_ID
XPAR_FABRIC_AXI_TIMER_0_INTERRUPT_INTR
#define BTN_INT XGPIO_IR_CH1_MASK
#define TMR_LOAD 0xF8000000
Board Support Package
Hardware Platform
Specification
AXI Timer Core
Implemented in Programmable Logic
Configuration of Zynq Processing System
in Vivado
Integrated logic analyzer Core
Implemented in Programmable Logic
Block Design for ZYNQ with timer
