Digital Modulation

Contents:
Digital Modulation Techniques
Bandwidth requirements
Transmitter and Receiver
Operations
 Digital Modulation
Techniques
Digital modulation techniques are two types
 Basic digital modulation Technique
◦ Amplitude shift keying (ASK/OOK)
◦ Frequency shift keying (FSK)
◦ Phase shift keying (PSK)
 Advanced digital modulation techniques
◦ QPSK
◦ DPSK
◦ MSK
◦ M-ary Modulations
 M-ary ASK
 M-ary PSK
 Mary FSK
 M-ary QAM
 ASK/OOK Modulation

1 0 0 1 1 0
1 f (t ) f m (t )  Af (t ) cos c t
ASK
Modulator
f c (t )  A cos c t
 ASK/OOK Modulation
Let f (t ) cos m t

f m (t )  A cos mt cos c t 1 2 [cos(m  c )t  cos(m  c )t ]

F( f )

f
 f m Fc ( f ) f m
f
 fc fc
Fm ( f )

Bandwidth
f requirement
fc  fm fc  fm 2fm
 FSK Modulation
1 0 0 1

In binary FSK, the binary data waveform d(t) generates a binary

signal
vFSK (t )  2 Ps cos[0t  d (t )t ]
d(t) equal +1 or -1 corresponding to logic level “1” or “0” of the
data waveform. The transmitted signals are of amplitude 2Ps

vFSK (t ) S H (t )  2 Ps cos[0t  t ] “1” is transmitted

vFSK (t ) S L (t )  2 Ps cos[0t  t ] “0” is transmitted

 FSK Modulation
Let  H 0   and  L 0  

2 2 Ps PH (t ) cos  H t
cos  H t
Tb
PsTb PH (t ) Adder vFSK (t )
2
cos  L t
Tb 2 Ps PL (t ) cos  L t
PsTb PL (t )
Two balance modulators are used. One Logic d(t) PH(t) PL(t)
with carrier H and one with carrier L. level
The voltage PH(t) and PL(t) are related to 1 +1V +1V 0V
the Voltage values of d(t) in the following 0 -1V 0V +1V
manner
 Bandwidth requirement
for FSKF ( f )

f
 fm fm Bandwidth
Fc ( f )
requirement is
f wider in the
f c  f f c  f order of 2f
Fm ( f ) with respect to
ASK
modulation
f
f c  f  f m f c  f  f m f c  f  f m f c  f  f m
2f  2 f m
 Binary PSK Modulation
+1V
-1V

2 Ps cos 0t “1” is trans. 2 Ps cos(0t   ) “0” is trans.

Data ‘b(t)’ is a binary stream of binary digits with voltage levels

+1V and -1V when “1” is trans. and “0” is trans., respectively

2 Ps cos 0t vPSK (t ) b(t ) 2 Ps cos 0t

b(t )
Bandwidth requirement of
BPSK
F( f )

f
 fm fm
Fc ( f )

 fc fc f
Fm ( f )

Bandwidth
f requirement
fc  fm fc  fm 2fm
 Detection of Binary Signal
There are two types of detection schemes
in Digital Communication
 Synchronous/ Coherent detection
 Noncoherent/ Envelope detection
Synchronous
detection Lowpa Binary output
f m (t )  f (t ) cos c t ss
filter Kf (t ) 2
Local
f LO (t ) K cos c t Oscillat
or
Why Frequency Synchronization is needed?

Frequency
Synchronization
In synchronous detection, local carrier must be in same frequency with
incoming carrier. If local carrier at a frequency of
cos(c   )t
Kf (t ) cos(c   )t cos c t
K Kf (t )
 f (t )[cos(2c   )t  cos t ]  cos t
2 2
If  within pass band then output will be distorted
Why Phase Synchronization is needed?
In synchronous detection, local carrier must be in same phase with
incoming carrier. If local carrier at right frequency c but  radians out
of phase with incoming carrier
cos(c t   )
Kf (t ) cos(c t   ) cos c t
K Kf (t )
 f (t )[cos(2c t   )  cos  ]  cos 
2 2

If  increases cos  decreases. If  /2 , output is zero. If  increases

beyond /2, the output signal reverse in sign. If baseband signal bipolar
in polarity,

‘1’ becomes ‘0’ and ‘0’ becomes ‘1’.

Phase Synchronization Techniques

A pilot carrier may be

transmitted, and superimposed
on the high frequency binary
signal stream, which may be
extracted at the receiver and
used to synchronized the receiver
local oscillator.
A phase-locked loop is used to
drive the phase difference to zero
 Incoherent/ Envelope Detection
In case of envelope detection, timing and
phasing information are not needed

output

In case of ASK,f m (t )  Af (t ) cos ct

At the output of the diode
2
A
A2 f 2 (t ) cos 2 c t  f 2 (t ) f(t) ‘1’ or ‘o’ so f2(t)=‘1’ or ‘0’
2
The PSK signal has constant envelope so envelope detector can not be
used to detect PSK modulated signal. PSK require synchronous detector
In case of PSK, f(t) =’1’, so f2(t)=‘1’
 Reception of BPSK Modulated Signal
The received signal has the from vPSK (t ) b(t ) 2 Ps cos(0t   )
Here  is phase shift which depends on the path length from Tx to Rx.
Phase shift may also cause by the amplifiers in the front-end.
Balance
b(t ) Square
d FD
Modulat
law BF
2
cos(0t   )
device
or
b(t ) 2 Ps cos 2 (0t   )
2 P cos  t
s 0
Integrator
Ss
Synchron v0 ( KTb ) 
o-us DM
b(t ) 2 Ps cos(0t   ) PsTb
b(t )
Bit Sc 2
synchroni
zer
cos 2 (0t   ) 1 2  1 2[cos 2(0t   )]
b(t ) 2 Ps cos 2 (0t   ) b(t ) 2 Ps [1 2  1 2 cos 2(0t   )]
 Reception of BPSK Modulated Signal
Bit Synchronizer: Able to recognize precisely the moment which
corresponds to the end of the time interval allocated to one bit and the
beginning of the next.

Switch Sc: Closes briefly to discharge (dump) integrator capacitor at the

moment of the end of the time period allocated for one bit and the
beginning of the next bit.
Switch Ss: Sample the output voltage just prior to the dumping the
capacitor.
The output voltage v0(KTb) at the end of a bit interval extending from time
(K-1)Tb to KTb.
KTb KTb
1 1
v0 ( KTb ) b( KTb ) 2 Ps  dt  b( KTb ) 2 Ps  cos 2(0t   )dt
( K  1)Tb
2 ( K  1)Tb
2
1
v0 ( KTb ) b( KTb ) 2 Ps Tb
2
 Differential Phase Shift Keying (DPSK)
DPSK is the modified form of BPSK in which need for synchronous
carrier for demodulating BPSK signal can be avoided.

vDPSK (t ) b(t ) 2 Ps cos 0t

d (t ) b(t ) Balanced
b(t  Tb ) Modulator  2 Ps cos 0t
2 Ps cos 0t
Delay Tb
Logic level
d(t) d(t-Tb) b(t)
Logic level Voltage Logic level Voltage Logic level Voltage
0 -1 0 -1 0 -1
0 -1 1 1 1 1
1 1 0 -1 1 1
1 1 1 1 0 -1
 Differential Phase Shift Keying (DPSK)
Logic waveform
Interv
al No.0 1 2 3 4 5 6 7 8 9 1 11 12 13 14
d(t) 0

b(t-Tb)

b(t)

b(t ) d (t )  b(t  Tb )
vDPSK (t ) b(t ) 2 Ps cos 0t vDPSK (t )  2 Ps cos 0t

When d(t)=0, the voltage level is -1V, and the phase of the carrier does
not change. When d(t)=1, the voltage level is +1V, and the phase of the
carrier changes by the magnitude 
 DPSK Receiver

b(t )b(t  Tb )(2 Ps ) cos(0t   ) cos[0 (t  Tb )   ]

b(t )b(t  Tb ) Ps
b(t ) 2 Ps cos(0t   ) Ss
Synchron
0Tb 2n ous DM

Delay Tb Bit Sc
synchroni
zer
b(t  Tb ) 2 Ps cos[0 (t  Tb )   ] Integrator

The multiplier output b(t )b(t  Tb )(2 Ps ) cos(0t   ) cos[0 (t  Tb )   ]

b(t )b(t  Tb ) Ps cos(0Tb  cos[20 (t  Tb 2)  2 ]
The second term i.e. double frequency term will not appear at the output
of the integrator. Only the first the term will appear at the output of the
Integrator. 0Tb 2n With n is an integer, cos(0Tb ) 1
 DPSK Receiver
Output of the integrator = b(t)b(t-Tb)Ps

 When d(t)=0, b(t)=b(t-Tb) both being +1V or both being -1V, in this
case b(t)b(t-Tb)=1

 When d(t)=1, b(t)=1V with b(t-Tb)=-1V or vice versa. In either case ,

b(t) b(t-Tb) =-1.

 When d(t)=0, b(t) b(t-Tb) =1 that means phase of the carrier does not
change. When d(t)=1, b(t) b(t-Tb) =-1 that means phase of the carrier
has been changed.
Advantage of DPSK over BPSK
 No need to generate local carrier at the receiver which leads to
avoid complicate circuitry.
 Cost can be reduced
Disadvantage
 The error rate in DPSK greater than BPSK
 Noise in one bit interval may cause error in two bits