Chapter 11: Nanometer Design Studies

11.1 Transistor Design

Considerations
11.2 Deep-Submicron Effects
11.3 Transconductance Scaling
11.4 Transistor Design
11.5 Op Amp Design Examples
11.6 High-Speed Amplifier
11.7 Summary
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 Transistor Design Considerations
• Large signal model is necessary in two cases:
– When transistor experiences large voltage (or
current changes) due to input or output signals,
disobeying the small-signal model
– When transistor must be biased, requiring certain
terminal voltages so as to carry a specified
current
• Former case occurs occasionally while latter almost
always occurs
• Large-signal behavior of nanometer MOSFETs
departs from “long-channel” model developed
• Due to technology scaling, several effects manifest
altering the I/V characteristics

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 Transistor Design Considerations

• Above figure plots the actual ID-VDS characteristics of

an NFET with W/L = 5 μm/40 nm and VTH ≈ 300 mV
(using a BSIM4 model) as against a “best-fit” long-
channel square-law approximation
• The two models diverge considerably
– Cannot perform bias calculations using square-
law model
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 Transistor Design Considerations
• MOS small-signal model still
holds for short-channel devices
• Expressions relating gm and rO to
bias conditions need revision
• Difficult to distinguish between
triode and saturation regions
• Can associate a “knee” point to
each curve as a rough boundary

• Above figure plots actual 40-nm device

characteristics for VGS – VTH = 50 mV, 100 mV, …, 350
mV
• Knee points are observed below VDS = 0.2 V (W = 5μm
and VTH ≈ 200 mV)

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 Deep-Submicron Effects
• Velocity Saturation:
• In a MOSFET, as VDS and hence the electric field
along the source-drain path increase, ‘v’ does not
increase proportionally
• Carriers experience “velocity saturation”, i.e.,
mobility falls
• Effect arises because length of MOSFETs has shrunk
from 1 μm to 40 nm while the allowable drain-source
voltage has decreases from 5 V to about 1 V
• Lateral electric field has exceeded Ecrit in fig. below

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 Deep-Submicron Effects
• Velocity Saturation:
• Suppose charge carriers reach saturated velocity, vsat
as soon as they depart from the source
• Since I = Qd∙v where Qd is the charge density per unit
length and given by WCox(VGS - VTH), we have

• Extreme velocity saturation creates three departures

from square-law behavior
– ID is linearly proportional to overdrive and
independent of channel length
– ID reaches saturation even for VDS < VGS – VTH
– gm of a fully velocity-saturated MOSFET emerges
to be relatively constant

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 Deep-Submicron Effects
• Velocity Saturation:

• Above figure shows that ID saturates even for VDS <

VGS - VTH due to velocity saturation
• Knee points occur at relatively small VDS’s even for
moderate overdrives

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 Deep-Submicron Effects
• Mobility Degradation with Electric Field:
• Mobility of charge carriers in the channel also
declines as the gate-source voltage and the vertical
field increase

• We intuitively expect that gm no longer follows the

linear relationship gm = μCox(W/L)(VGS – VTH), with the
overdrive voltage

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 Deep-Submicron Effects
• Mobility Degradation with Electric Field:

• Above figure shows the nonlinear relationship

between gm and VGS – VTH for the 5 μm/40 nm NFET
device

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 Transconductance Scaling
• Suppose a transistor operates in the saturation region
but does not provide the required transconductance,
from gm equations,

• Adjustment in three parameters, namely, W/L, VGS –

VTH, or ID can scale gm
• Assume a long-channel device and hence

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 Transconductance Scaling

• If W/L is increased while keeping VGS – VTH constant,

both gm and ID linearly scale with W/L and so does the
power consumption [Fig. (a)]
• If VGS – VTH is increased but keep W/L constant, thus
requiring a higher drain current [Fig. (b)]
• In the former case, device capacitances rise whereas
in the latter, VDS,min increases
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 Transconductance Scaling

• If W/L is increased with ID constant, VGS – VTH is

lowered [Fig. (c)]
• gm does not climb indefinitely however, due to
subthreshold conduction
• If W/L is held constant and ID is increased, then VGS –
VTH and hence VDS,min rises

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 Transconductance Scaling

• If ID is increased while VGS – VTH is constant, W/L is

needed to increase [Fig. (e)]
• Alternatively, if VGS – VTH is lowered with ID kept
constant, W/L must increase [Fig. (f)]
• For VGS – VTH ≈ 0, device enters subthreshold region
and gm ≈ ID/(ξVT)
• Device capacitances increase in both cases
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 Transconductance Scaling - Example

• Linear scaling of gm and ID with W/L holds regardless

of transistor characteristics
• Consider two identical transistors are connected in
parallel, each with transconductance gm
• If VGS changes by ΔV, then drain current of each
device changes by gmΔV, hence current of composite
device changes by 2gmΔV; parallel combination
exhibits a transconductance 2gm
• Scaling preserves device “current density” (ID/W)
• Bias overdrive voltage and gm/ID ratio remains
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 Transistor Design
• A given transistor in a circuit is characterized by
many parameters
• Assume transistor operates in saturation
• Interested in:
– Bias quantities: ID and VGS – VTH (=VDS,min)
– Small-signal parameter: gm
– Physical parameter: W/L
• Typical transistor design problem:
– Given two of gm, ID and VGS – VTH, determine the
other two parameters

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 Transistor Design

• Design problems shown above are “overconstrained”

• Two given parameters lead to certain values for the
other two, even though results may not always be
desirable
• Design revisions are necessary in such a case

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 Design for given ID and VDS,min
• Suppose for a given transistor, we have chosen:
– A bias current (according to a power budget)
– Minimum VDS (according to voltage headroom
restrictions imposed by supply voltage and
output swing requirements)
• We wish to determine the dimensions and
transconductance of the device, recognizing that
square-law models are inaccurate
• Three-step approach
• Consider ID = 0.5 mA and VDS,min = 200 mV as an
example

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 Design for given ID and VDS,min
• Step 1: Select a reference transistor, with a width WREF
and length equal to minimum allowable value, Lmin
(e.g., Lmin = 40 nm). Choose WREF = 5 μm as an
example
• Step 2: Using actual device models and a circuit
simulator, plot ID-VDS characteristics of the reference
transistor for different values of VGS – VTH
– Typically VGS – VTH ranges from 50 mV to 600 mV
– Can construct the characteristics with the
overdrive incrementing in steps of 50 mV

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 Design for given ID and VDS,min

• Above figure shows results for WREF/Lmin = 5 μm/40 nm

and overdrive ranging from 50 mV to 350 mV
• Step 3: Since in our example, ID = 0.5 mA and VDS,min =
200 mV, we draw a vertical line at VDS = 200 mV and
find its intersection with the plots
• If device obeyed square law, we would choose the
plot for VGS – VTH = VDS,min = 200 mV
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 Design for given ID and VDS,min

• Step 3 (contd.): Short-channel device remains in

saturation even for VGS – VTH = 350 mV and VDS = 200
mV
– Situation is more complex, proceed with VGS – VTH
= 200 mV for now
• This procedure yields one operating point for the
reference transistor satisfying VDS requirement
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 Design for given ID and VDS,min

• Step 4: The drain current, ID,REF is not close to the

necessary value, 0.5 mA, in our example
• We must scale the width and hence the drain current
of the transistor
• Since ID,REF ≈ 100 μA above, we choose a transistor
width of (500 μA/ 100 μA) x WREF = 5WREF = 25 μm

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 Design for given ID and VDS,min

• Step 4 (contd.): From ID-VDS plots, gm of the reference

transistor can be approximated from gm = ΔID/ ΔVGS ≈ 2
mS
• To get a more accurate value of gm, we plot gm versus
VGS – VTH for VDS = 200 mV using simulations as shown
above
• This predicts gm = 1.5 mS for VGS – VTH = 200 mV
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 Design for given ID and VDS,min

• Step 4 (contd.): If both width and drain current are

scaled up by a factor of 5, gm increases to 7.5 mS
• If this is insufficient, W/L must be increased further
• We can perform scaling to determine width and
transconductance of other transistors in the circuit,
using ID and gm plots for the reference device

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 Design for given ID and VDS,min

• Step 4 (contd.): We typically choose VGS – VTH ≈ VDS,min

to obtain a higher gm even though it translates to a
wider transistor

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 Design for given ID and VDS,min

• Output impedance rO of short-channel devices cannot

be expressed as 1/(λID)
• We use simulations to plot rO for the reference device
as a function of ID as shown above
• Reference transistor carries a current of 100 μA,
exhibiting rO = 8 kΩ
• When width and drain current are scaled up by factor
of 10, rO falls by the same factor to 800 Ω
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 Design for given gm and ID
• In many analog circuits, a given transistor must
provide sufficient transconductance while consuming
minimal power
• Suppose we are given a specified transconductance
gm1 and an upper limit for the drain bias current ID1,
seeking the corresponding values of W/L and VGS –
VTH
• Assume gm1 = 10 mS and ID1 = 1 mA
• To determine whether gm1 can be obtained with ID ≤ ID1,
we note that maximum gm occurs in the subthreshold
region and is given by ID/(ξVT) where ξ = 1.5
• For ID = 1 mA, gm cannot exceed 26 mS at room
temperature
• Since gm1 < ID1/(ξVT), this design is feasible

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 Design for given gm and ID
• Step 1: Using simulations, we plot gm as a function of
ID for a reference transistor, e.g., WREF/Lmin = 5 μm/40
nm

• Step 2: We identify the point (ID1,gm1) on the gm-ID plane

and draw a line through the origin and this point,
obtaining the intersection at (ID,REF,gm,REF) = (240 μA, 2.4
mS) and a corresponding overdrive
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 Design for given gm and ID

• Step 3: We multiply WREF by gm1/gm,REF = 4.2 so as to

travel on the straight line to point (ID1, gm1) while
maintaining the same overdrive
• This completes the transistor design

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 Design for given gm and ID
• Above procedure elicits two questions
• Question 1: Does the straight line passing through
the origin and (ID1,gm1) always intersect the gm-ID plot?
• For a square-law device in strong inversion,
ssssss has a slope of infinity at the
origin, guaranteeing an intersection point
• In the subthreshold region, on the other hand,
sssss which means the (ID,gm) combinations in the
gray region are not achievable

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 Design for given gm and ID
• Question 2: If (VGS – VTH)REF is excessively large, then
by factor must W be increased?

• In above figure, suppose an overdrive of (VGS – VTH)2 <

(VGS – VTH)REF is desired
• We then find the corresponding current ID2 and
transconductance gm2 on the gm-ID plane
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 Design for given gm and ID

• Next, we draw a line through the origin and the point

(ID2,gm2) continue to ID = ID1, i.e., we multiply WREF by
ID1/ID2
• The resulting width guarantees an overdrive of (VGS –
VTH)2 at a drain current of ID1 and provides a
transconductance of at least gm1
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 Design for given gm and VDS,min
• In some designs, the transconductance is dictated by
some performance requirements (voltage gain, noise,
etc.) and the minimum VDS by the voltage headroom,
without an explicit specification of ID
• Step 1: We use simulations to plot gm as a function of
VGS – VTH for the reference transistor
• Now we select (VGS – VTH)1 = VDS,min and obtain the
corresponding transconductance gm,REF
• It is helpful to plot ID on the same plane and find ID,REF
at (VGS – VTH)1

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 Design for given gm and VDS,min
• Step 2: To reach the required transconductance gm1,
we scale the transistor width by a factor of gm1/gm,REF
– ID scales by the same factor
• If the resulting ID is too large, we redesign for a given
gm and ID
• Device is now smaller and has a smaller
transconductance

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 Design for given gm
• Suppose a design problem only specifies the
transconductance, and we wish to compute the
remaining parameters
• Two scenarios may be envisaged
• We select a certain W/L and raise ID until the desired
transconductance, gm1 is reached
– Required ID and hence power consumption may
be excessive
– Overdrive voltage may be excessively large
• We select a reasonable value for ID (perhaps
according to a power budget) and increase W/L to
obtain gm1
– Increasing W/L (hence decreasing VGS) eventually
drives device into subthreshold region, where gm
cannot exceed ID/(ξVT)
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 Design for given gm
• First, we construct plots representing gm and VGS – VTH
as a function of ID for the reference device, using
simulations
– Here VDS is kept constant and approximately
equal to VDD/2
• We select a reasonable value for VGS – VTH, e.g., 200
mV, which points to ID,REF and gm,REF
• Next, we scale the width and drain current by a factor
of gm1/gm,REF

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 Choice of Channel Length
• If the selection of ID, VGS – VTH and gm does not yield a
sufficiently high rO, we must increase the transistor
length
• To maintain the same drain current, overdrive and gm,
the width must also be scaled proportionally
• Such scaling is not straightforward
– If drawn length increases from Lmin to 2Lmin,
effective length increases from Lmin – 2LD to 2Lmin
– 2LD
• We must use simulations to construct the ID-VDS, gm
and rO characteristics for several channel lengths,
e.g., 60 nm, 80 nm, 100 nm (drawn values)

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 Op Amp Design Examples
• Consider an op-amp design example in 40-nm
technology
• We target the following specifications
– Differential output voltage swing = 1 V pp
– Power consumption = 2mW
– Voltage Gain = 500
– Supply Voltage = 1 V
• Single-ended output swing of 0.5 Vpp is small enough
to make telescopic or folded-cascode op-amps a
plausible choice
• Begin with minimum allowable width and length
devices unless otherwise dictated by current,
transconductance, VD,sat, output resistance, etc

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 Design 1: Telescopic Op-Amp

• Consider the telescopic op-amp topology shown

above to meet previously mentioned requirements
• Of the total supply current of 2 mA, we allocate 50 μA
each to IREF1 and IREF2, and 0.95 mA for each branch of
the differential pair
• To accommodate a single-ended peak-peak swing of
0.5 V, we must distribute the remaining 0.5 V over M9,
M1,2, M3,4, M5,6 and M7,8, allowing 100 mV for each
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 Design 1: Telescopic Op-Amp

• With the bias currents and overdrives known, we can

determine W/L’s by examining I/V characteristics
• For L = 40 nm, the intrinsic gain gmrO of NMOS devices
is around 7-10 and for PMOS devices is 5-7
• It is difficult to raise gmrO beyond 10 for PFETs
• If we approximate gm as 2ID/(VGS – VTH) = 2 x 0.95
mA/100 mV = 19 mS, we estimate rO ≈ 530 Ω from gmrO
≈ 10
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 Design 1: Telescopic Op-Amp

• If gm1,2 ≈ 19 mS, then for the gain GmRout to reach 500,

the op-amp output impedance must exceed 26 kΩ
• However, with gm3,4rO3,4 ≈ 10 and rO7,8 ≈ 530 Ω, we have
(gm3,4rO3,4)rO1,2 ≈ 5.3 kΩ, obtaining a voltage gain of only
100 even if the PMOS devices have λ = 0
• Telescopic arrangement is impractical for a gain of
500
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 Design 1: Telescopic Op-Amp
• We still continue with the design out of curiosity
• Using simulations, we construct the I/V
characteristics of NMOS and PMOS devices with L =
40 nm and 80 nm, since minimum length may exhibit
unacceptably low rO and gmrO
• Simulation parameters must ensure that devices
remain in saturation for |VDS| ≥ 100 mV
• Since threshold and overdrive elude clear definitions
in nanometer technologies, we must adjust VGS in
simulations to ensure saturation

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 Design 1: Telescopic Op-Amp

• Fig. (a) plots ID-VDS curves for (W/L)N = 5 μm/40 nm

(blue) and 10 μm/80 nm (gray) with VGS = 300 mV
• Fig. (b) plots ID-VDS curves for (W/L)P = 5 μm/40 nm
(blue) and 5 μm/80 nm (gray) with VGS = -400 mV
• Difficult to distinguish between triode and saturation
regions, especially for PFETs
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 Design 1: Telescopic Op-Amp

• 40-nm PMOS device displays a decreasing output

impedance as |VDS| reaches 400 mV
• For other three characteristics, we can roughly
identify a “knee” point beyond which slope falls
considerably
– VGS chosen to place this point below |VDS| = 100
mV
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 Design 1: Telescopic Op-Amp

• At VDS = 100 mV, the 10 μm/80 nm NMOS provides rO

of 22.8 kΩ and ID of 16 μA
• If scaled up to carry 950 μA, rO drops to 385 Ω
• Similarly, the 5 μm/80 nm PMOS has an rO of 18.45 k Ω
at VDS = -100 mV with ID = 15 μA, thus offering rO = 290
Ω if scaled up to carry 950 μA
• These low values of rO are discouraging
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 Design 1: Telescopic Op-Amp
• We scale the NMOS and PMOS device widths to
accommodate a drain current of 950 μA with VGS,N =
300 mV, VGS,P = -400 mV and |VDS| = 100 mV, resulting
in the design shown below

• Minimum-length devices are used in the signal path to

maximize speed and minimize capacitances

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 Design 1: Telescopic Op-Amp

• Bias voltages are tentatively chosen as follows:

• Input common-mode level VCM,in = 100 mV for the tail
current source plus VGS1,2 (= 300 mV)
• Vb1 = VD1,2 (= 200 mV) + VGS3,4 (= 300 mV)
• Vb2 = VDD – |VDS7,8| – |VGS5,6|
• Vb3 = VDD – |VGS7,8|
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 Design 1: Telescopic Op-Amp

• We perform a dc sweep of differential input voltage Vin

• Drain voltages of M1 and M2 (VA, VB)are around 220 mV
in the middle of the range
• Drain voltages of M7 and M8 (VC, VD)are close to
targeted value

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 Design 1: Telescopic Op-Amp

• Output behavior shown above (VX, VY)

• Slope of each single-ended output is approximately
15 near Vin = 0, yielding a differential gain of 30
• Characteristic becomes nonlinear as each output
rises towards 0.7 V

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 Design 1: Telescopic Op-Amp
• Gain can be raised by increasing (W/L)3,4 to 600 μm/80
nm, characteristics plotted below
• Characteristics exhibit a gain of about 54 but a limited
output swing

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 Design 1: Telescopic Op-Amp- Bias
Circuit
• Op-amp circuit relies on proper choice of bias
quantities ISS, Vb1, Vb2 and Vb3
• ISS and Vb3 must be established by current mirror
action and Vb2 by low-voltage cascode
• Vb1 requires a different approach
• We begin with ISS = 1.9 mA, choosing a channel length
of 40 nm and scaling from reference device curves, a
width of 600 μm for VDS = 100 mV
• With reference current budget of 25 μA, we arrive at
the arrangement of Fig. (a), with W12 scaled down
from W11 by a factor of 1.9 mA/25 μA

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 Design 1: Telescopic Op-Amp- Bias
Circuit

• Since M11 operates with a VDS of 100 mV, R1 is inserted

in series with drain of M12 such that VDS12 = VGS12 – VR1
= 100 mV
• Design of Fig. (a) is sensitive to CM level since VDS11 =
VCM,in – VGS1,2 whereas VDS12 = VGS1,2 – VR1
• Drain voltage of M12 must track VCM,in
• This can be done as in Fig. (b) where R1 is replaced by
a differential pair driven by Vin1 and Vin2
• With proper width scaling, we have VGS13,14 = VGS1,2 and
Copyright ©hence VEducation.
2017 McGraw-Hill DS12 = VDS12
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 Design 1: Telescopic Op-Amp- Bias
Circuit
• In op-amp circuit designed, Vb1 must equal VGS3,4 +
VDS1,2 + VP, where VDS1,2 = 100 mV
• Diode-connected device in series with a drain-source
voltage added to VP can produce Vb1
• Ib must be much less than ISS
• We select Ib = 15 μA and hence (W/L)15,16 = 10 μm/80
nm
• If VCM,in rises, so do VP and hence Vb1, keeping VDS1,2
constant

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 Design 1: Telescopic Op-Amp- Bias
Circuit
• In order to generate Vb3 and Vb2, a low-voltage
cascode is constructed as shown below
• M17 and M18 are scaled down respectively down from
M7,8 and M5,6, ensuring that VDS17 = VDS7,8
• To create Vb2 = VDD - |VDS7,8| - |VGS5,6|, a diode-connected
device M20 is connected in series with VDS produced
by M19

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 Design 1: Telescopic Op-Amp- Common-Mode
Feedback
• Due to various mismatches, PMOS currents are not
exactly ISS/2, forcing the output CM level to VDD or
ground and hence requiring CMFB
• Output CM level, VCM must be sensed and fed to the
NMOS or PMOS current sources
• CM level can be sensed by resistors, triode
transistors or source followers
• High output impedance of op-amps dictates very
large resistors and tight voltage margins demand
precise CM control and preclude triode devices
• Source followers cannot measure CM level across a
wide output swing

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 Design 1: Telescopic Op-Amp- Common-Mode
Feedback

• In Fig. (a), if VX (or VY) falls, I1 (or I2) eventually

collapses, disabling the source follower
• Complement NMOS followers by PMOS counterparts
• In Fig. (b), PMOS followers M23 and M24 also sense the
output CM level and drive R3, R4 respectively
• Here

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 Design 1: Telescopic Op-Amp- Common-Mode
Feedback
• A linear combination of V1 and V2 can remove VGS
terms, yielding a value proportional to VCM
• If , then
we must choose , obtaining
vvvvvv
• We can choose so that reconstructed value
is equal to actual op-amp output CM level
• α and β can be implemented by R1-R4
• If V1 and V2 are shorted, the weighted sum of V1 and V2
is produced

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 Design 1: Telescopic Op-Amp- Common-Mode
Feedback
• Using Fig. (c) below, it can be shown that

• Where RN = R1 = R2 and RP = R3 = R4
• We therefore choose RN/RP = VGS21,22/|VGS23,24|

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 Design 1: Telescopic Op-Amp- Common-Mode
Feedback
• To evaluate feasibility of this idea, we run a dc sweep
and observe the behavior of Vtot
• We select a bias current of 10 μA and W/L = 10 μm/40
nm for all source followers and RN = RP = 20 kΩ
• The 10-μA current sources are also implemented as
10 μm/40 nm transistors
• Figure below plots the actual CM level, defined as
(VX+VY)/2 and the reconstructed counterpart, Vtot

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 Design 1: Telescopic Op-Amp- Common-Mode
Feedback
• In the next test, the CMFB loop is closed: we compare
Vtot to a reference, amplify the error and return the
result to control ISS
• Error amplifier is designed as a five-transistor OTA
with W/L = 5 μm/80 nm for all transistors, tail current
of 20 μA and voltage gain of 10
• Amplifier output controls a fraction of main tail
current I1

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 Design 1: Telescopic Op-Amp- Common-Mode
Feedback
• Figure below shows closed-loop dc sweep results
with Vref = 0.5 V
• By virtue of feedback, the CM variation is greatly
reduced as VX and VY reach high or low values
• With a 10% mismatch between PMOS current
sources, dc sweep is repeated [Fig. (b)]
− CMFB suppresses mismatch by adjusting I1

(a) (b)

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 Design 1: Telescopic Op-Amp- CMFB
Stability
• To investigate stability of CM loop, the overall op amp
is placed its intended feedback system, applying
differential pulses at input, and examining differential
and common-mode behavior at output
• Fig. (a) shows a feedback topology for a nominal
closed-loop gain of 2
• Fig. (b) shows a more detailed diagram highlighting
the CM feedback loop

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 Design 1: Telescopic Op-Amp- CMFB
Stability
• Output waveforms in response to an input step are
plotted below, revealing common-mode instability
• CM loop contains a pole at input of error amplifier,
one at node H, one at node P, one at the sources of
the NMOS cascode devices and one at the main
outputs [Refer Fig. (b) on previous slide]
• Loop demands compensation

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 Design 1: Telescopic Op-Amp- CMFB
Stability
• Break the CM loop at node H as shown below
• Error amplifier drives a dummy device Md identical to
MT to see loading effect of the latter

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 Design 1: Telescopic Op-Amp- CMFB
Stability
• Fig. (a) plots the magnitude and phase of –VF/Vt as a
function of frequency, revealing a phase of -190 ⁰ at
the unity-gain frequency
• We seek a convenient node for compensation
• Error amplifier does not provide signal inversion from
Vtot to H and hence cannot employ Miller
compensation

(a)

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 Design 1: Telescopic Op-Amp- CMFB
Stability
• Adding capacitance from high-impedance nodes X
and Y to ground affects differential response
• A 3-pF capacitor is tied from error amplifier output to
ground, obtaining the response shown in Fig. (b), with
a phase margin of 50⁰

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 Design 1: Telescopic Op-Amp- CMFB
Stability
• Closed-loop response of Fig. (a) implies that CMFB
loop is properly compensated and CM level incurs
differential ringing
• Pole formed by large feedback resistors and input
capacitance of op-amp is located at a low frequency,
degrading phase margin of differential feedback
• To compensate differential signal path, two 7-pF
capacitors are connected from outputs of op-amp to
its inputs to create Miller multiplication [Fig. (b)]

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 Design 1: Telescopic Op-Amp-Design
Summary
• Telescopic cascode op-amp for a voltage gain of 500
and a differential output swing of 1 V pp is not
achievable with a 1-V supply
• General steps followed:
– Allocation of VDS and ID to transistors according to
required swings and power dissipation
– Characterization and scaling of MOSFETs for
allowable VDS and desired currents
– Quick estimate of achievable voltage gain
– Dc sweep to study bias conditions and
nonlinearity
– Design of bias circuitry using current mirrors and
low-voltage cascodes
– CMFB design and compensation
– Closed-loop transient analysis to study CM and
differential stability
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 Design 2: Two-Stage Op-Amp
• Relatively high voltage gain and 1-Vpp swing point to a
two-stage configuration as a feasible candidate
• Gain of 500 dictates use of cascading in the first
stage
• With a gain of about 50 in the first stage, gain of
second stage can be around 10
• Single-ended peak-to-peak swing at output of first
stage can be as small as 50 mV, allowing redesign of
cascode for greater VDS’s and more robust operation
• Partitioning of power budget between two stages
requires speed and/or noise specifications
• We split the power equally here, with further
optimization after one round of complete design
• With about 100 μA reserved for bias network, we
allocate 1.9 mA/4 = 475 μA to each transistor branch
in the first and second stages
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 Design 2: Two-Stage Op-Amp- First Stage
Design
• Telescopic-cascode configuration must
accommodate a single-ended swing of 50 mV pp,
allowing 0.95 V for the sum of five VDS’s
• We choose VDS,N = 150 mV and VDS,P = 200 mV and
simulate reference transistors [W/L = 5 μm/40 nm
(gray) and 10 μm/80 nm (blue)], seeking acceptable
knee voltages
• Fig. (a) shows curves for VGS,N = 350 mV while Fig. (b)
shows curves for VGS,P = - 450 mV

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 Design 2: Two-Stage Op-Amp- First Stage
Design
• Width of NMOS transistors in the signal path must be
scaled by a factor of 450 μA/50 μA for either L = 40 nm
or L = 80 nm
• Width of PMOS device must be scaled by a factor of
450 μA/50 μA for either L = 40 nm or L = 80 nm
• For tail current device, we choose W = (900 μA/50 μA)
x 10 μm and L = 80 nm
• First-stage design is shown in Fig. (a) and simulated
behavior in Fig. (b), revealing a gain of about 50

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 Design 2: Two-Stage Op-Amp- Second Stage
Design
• Second stage must provide a voltage gain of about
10, dictating channel lengths greater than 40 nm for
both NMOS and PMOS devices
• Output CM level of first stage is around 0.55 V
• Consider a transistor having W/L = 10 μm/ 80 nm and
determine its gmrO if it is an NFET with VGS ≈ 0.55 V or
a PFET with |VGS| ≈ 0.45 V
• Using simulations, we get (gmrO)N = 12.8 and rON = 1.86
kΩ at VDS = 0.5 V and ID = 900 μA, and (gmrO)P = 17.5
and rOP = 9.75 kΩ at |VDS| = 0.5 V and |ID| = 110 μA
• We therefore select the PFET as input of second
stage and scale its width to (450 μA/110 μA) x 10 μm ≈
41 μm, exhibiting an output resistance of 2.38 kΩ
• Drain of the PFET is tied to an NMOS current source

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 Design 2: Two-Stage Op-Amp- Second Stage
Design
• The NMOS current source must not lower the gain of
the second stage, |Av2| below 10
• Since |Av2| = gmP(rOP||rON) ≥ 10, we have rON ≥ 1.33rOP =
3.0 kΩ at ID = 475 μA
• If the 10 μm/80 nm NFET considered before with rO =
1.86 kΩ and ID = 900 μA is scaled down by a factor of
2, it yields rON = 3.72 kΩ, close to the desired value
• Fig. (a) shows op-amp developed so far

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 Design 2: Two-Stage Op-Amp- Second Stage
Design
• Fig. (b) plots input-output characteristics
• To determine the maximum output swing that the op-
amp can handle, we plot the slope of the differential
characteristic in Fig. (c), noting that the differential
output cannot exceed 450 mV if the gain must not
drop below 500

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 Design 2: Two-Stage Op-Amp- Second Stage
Design
• To resolve this issue, we double the width and length
of the output NFETs, raising the gain and arriving at
the results shown below
• Now, single-ended swing reaches 530 mV for a
minimum gain of 500

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 Design 2: Two-Stage Op-Amp- Common-Mode
Feedback
• Two-stage op-amps generally require CMFB for both
stages
• For first stage, the CMFB scheme described
previously can be used
• For second stage, the lower output impedance allows
the use of resistors for direct sensing of the CM level

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 Design 2: Two-Stage Op-Amp- Common-Mode
Feedback
• In topology of Fig. (a), R1 and R2 (≈ 30 kΩ) reconstruct
the CM level at node G, applying the result to the
gates of M11 and M12
• Under equilibrium, resistors draw no current,
establishing an output CM level equal to VGS11,12
• This voltage varies by about 50 mV with PVT
• This CMFB loop is stable

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 Design 2: Two-Stage Op-Amp- Common-Mode
Feedback
• If VGS11,12 is not close to the desired output CM level,
we inject a current IB into node G, and the output CM
level is shifted by IBR1/2 (=IBR2/2), as shown in Fig. (b)
• For example, a shift of 100 mV requires a current of
(100 mV/30 kΩ) x 2 = 6.7 μA
• A positive IB shifts the CM level down and vice versa

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 Design 2: Two-Stage Op-Amp- Frequency
Compensation
• Two-stage op-amp contains several poles and
demands compensation
• First non-dominant pole of two-stage op-amps
typically arises from the output node and depends on
the load capacitance, CL
• Choose a single-ended load capacitance of 1 pF here,
obtaining an output pole frequency of around 90 MHz
• We begin with the open-loop op-amp, realizing that
the feedback network may add its own effects and
require changes

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 Design 2: Two-Stage Op-Amp- Frequency
Compensation
• Open-loop (differential) magnitude and phase
response of the circuit is plotted below
• Low-frequency gain is 57 dB (≈ 700) and unity-gain
frequency is 3.2 GHz, with a phase margin of 8⁰
• Phase reaches -120⁰ at 240 MHz, therefore after
compensation for 60⁰ phase margin, the unity-gain
bandwidth can drop by a factor of 13

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 Design 2: Two-Stage Op-Amp- Frequency
Compensation
• To compensate the op-amp, we begin at 240 MHz and
0 dB on the magnitude plot and draw a straight line
toward the y-axis with a slope of -20 dB/dec
• The frequency at which this line intersects the
magnitude plot is roughly 240 MHz/700 = 344 kHz,
yielding the desired value for the dominant pole
• Node X is preferred over the output node to produce
the dominant pole due to Miller multiplication and
pole splitting

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 Design 2: Two-Stage Op-Amp- Frequency
Compensation
• With the output resistance of 8 kΩ seen at node X and
a voltage gain of about 12 provided by the output
stage, we choose a Miller compensation capacitor, CC
equal to 4.5 pF so as to create a 344-kHz pole at this
node
• Resulting open-loop frequency response is shown
below

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 Design 2: Two-Stage Op-Amp- Frequency
Compensation
• Dominant pole is now located around 340 kHz
• Gain crossover occurs at 350 MHz and the phase
margin is only 18⁰ because the zero introduced by CC,
ωz = gm10/CC, is as low as 250 MHz
• We can insert a resistor Rz, in series with CC, so as to
move the zero to the second pole, ωp2,
• Second pole can be roughly estimated as the
frequency at which H reaches -135 and is equal to
185 MHz

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 Design 2: Two-Stage Op-Amp- Frequency
Compensation
• Selecting Rz according to (ωp2CC)-1 = 190 Ω, the
response observed is shown in Fig. (a)
• Phase margin rises to 96 because of pole-zero
cancellation

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 Design 2: Two-Stage Op-Amp- Frequency
Compensation
• CC can be smaller and the unity-gain bandwidth larger
• By some iteration, we choose CC = 0.8 pF and Rz = 450
Ω, arriving at the response of Fig. (b)
• The op-amp now exhibits a unity-gain bandwidth of
1.9 GHz with a phase margin of 65

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 Design 2: Two-Stage Op-Amp- Closed-Loop
Behavior
• Configure the op-amp as a closed-loop amplifier with
a nominal gain of 2 and a load capacitance of 1 pF
[Fig. (a)]
• Small-signal transient response shows significant
ringing due to large resistance values used in
feedback network [Fig. (b)]

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 Design 2: Two-Stage Op-Amp- Closed-Loop
Behavior
• Draw the single-ended equivalent circuit as in Fig. (a)
below for loop transmission calculation
• We observe that an open-loop pole around [2(100
kΩ||50 kΩ)Cin]-1 ≈ 95 MHz is formed at the input of the
op-amp

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 Design 2: Two-Stage Op-Amp- Closed-Loop
Behavior
• To improve closed-loop stability, we can reduce R1
and R2 to 25 kΩ and 50 kΩ, respectively before the
open-loop gain falls appreciably at the cost of double
input pole frequency
• Alternatively, we can increase the resistance in series
with the compensation capacitors from 450 Ω to 1500
Ω, arriving at the response in Fig. (b) below

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 High-Speed Amplifier
• Some applications require an amplifier with fast
settling and accurate gain
• We design a differential amplifier according to the
following specifications:
– Voltage gain = 4
– Gain Error ≤ 1%
– Differential output swing = 1 Vpp
– Load capacitance = 1 pF
– Step response settling time to 0.5% accuracy = 5
ns
– VDD = 1 V

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 High-Speed Amplifier

• As shown above, the settling time ts, is defined as the

time necessary for the output to reach within 0.5% of
its final value
• Objective is to minimize the power consumption of
the circuit

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 High-Speed Amplifier: Precision Issues
• Maximum tolerable gain error of 1% indicates a
closed-loop configuration to make gain relatively
independent of PVT
• Must design an amplifier with open-loop gain high
enough to yield closed-loop gain error of less than 1%
• Also, output swing of 1 Vpp calls for a two-stage op-
amp
• We arrive at the feedback arrangement shown below

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 High-Speed Amplifier: Precision Issues

• For the above feedback configuration, closed-loop

gain is given by

• We choose R2/R1 = 4, and ensure that the gain error

falls below 1%, obtaining A0 ≥ 500

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 High-Speed Amplifier: Precision Issues
• If R1 and R2 are large enough not to reduce the open-
loop gain of the op-amp, they form a significant pole
with the input capacitance, degrading the phase
margin
• Consider capacitive feedback as shown in Fig. (a)
• Closed-loop gain is now C1/C2, or more accurately,

• Cin denotes the (single-ended) input capacitance of

the op-amp

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 High-Speed Amplifier: Precision Issues

• In the single-ended counterpart of Fig. (b) for loop

transmission calculation, we observe that C1 and C2
do not contribute additional poles because
(C1+Cin)C2/(C1+C2+Cin) simply appears in parallel with
CL

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 High-Speed Amplifier: Precision Issues
• To provide bias for the op-amp inputs, we add two
feedback resistors so that the input and output dc
levels become equal [Fig. (a)]
• Finite time constant at X and Y leads to a high-pass
response

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 High-Speed Amplifier: Precision Issues
• If A0 = , then

• The corner frequency, 1/(2RFC2), must be chosen

less than the minimum frequency of interest
• We proceed assuming RFC2 is sufficiently large
• Capacitive-feedback amplifier’s gain also depends on
Cin
• For example, if Cin ≈ (C1+C2)/5 then A0 must be 20%
higher than that predicted previously
• We can choose C1+C2 >> Cin but at the cost of settling
speed
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 High-Speed Amplifier: Speed Issues
• The amplifier must settle to 0.5% accuracy in 5 ns
• Assuming a linear, first-order circuit, we can write the
step response as

• The time necessary for Vout to reach 0.995V0 is ts

= -*ln 0.005 = 5.3, i.e.,  must be no more than 0.94
ns
• Closed-loop amplifier must achieve a -3-dB bandwidth
of at least 1/(2  0.94 ns)  170 MHz

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 High-Speed Amplifier: Speed Issues
• If the op-amp is modeled by a dependent current
source, GmVin, and an output resistance, Rout, then the
closed-loop time constant is given by

• GmRout is assumed much greater than unity; above

expression can be rewritten as

• Op-amp sees the series combination of C2 and C1+Cin

in parallel with CL

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 High-Speed Amplifier: Speed Issues
• The foregoing model is not accurate for a two-stage
op-amp since the internal pole also affects the
response
• Consider a frequency-compensated two-stage op-
amp
• If the loop gain falls to 1 at the second pole ωp2, the
phase margin is about 45 for unity-gain feedback
• To compensate the op-amp for a closed-loop gain of
4, |βH| must fall to 0 dB at ωp2 (i.e., circuit is not
compensated for unity-gain feedback)

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 High-Speed Amplifier: Speed Issues
• As shown in Fig. (a), we begin at ω = ωp2 and draw a
line with slope -20 dB/decade toward the y-axis,
seeking its intercept with the plot of |βH| [Fig. (a)]
• Between the compensated dominant pole ω’p1, and
ωp2, we can approximate the compensated βH(s) as
βA0/(1 + s/ω’p1); we set its magnitude to 1 at ωp2

 

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 High-Speed Amplifier: Speed Issues
• To construct the closed-loop frequency response with
the value of ω’p1 calculated before, we plot the
magnitude of the loop transmission |βH|, for β = 1,
and after compensation [Fig. (b)]
• The closed-loop response begins at A0/(1+ βA0) at low
frequencies and begins to roll off at ω  ωp2
• The two responses intersect at ω  βA0ω’p1  ωp2
• We choose this bandwidth equal to 2(170 MHz)/125 =
2(1.36 MHz)

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 High-Speed Amplifier: Op-Amp Design
• Based on foregoing calculations, we seek a two-stage
op-amp with an open-loop gain of 500, a dominant
pole at 1.36 MHz and a second pole at 170 MHz and a
differential output swing of 1 Vpp
• Prototype designed earlier can serve our purpose
• Since the compensation can be relaxed to suit a
feedback factor of 1/5, the dominant pole of the op-
amp need not be as low as 344 kHz
• If the feedback factor is reduced from 1 to β, then the
dominant pole can increase by roughly a factor of 1/β
• Compensation capacitor can be lowered from 4.5 pF
to 0.9 pF, raising the dominant pole frequency from
340 kHz to 1.7 MHz
• For the feedforward zero to cancel the second pole,
R2 must rise by the same factor, reaching 950 Ω

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 High-Speed Amplifier: Closed-Loop Small-Signal
Performance

• Above figure shows overall op-amp and its closed-

loop environment
• For a nominal gain of 4, we choose C1 = 1pF and C2 =
0.25 pF
• With Cin  50 fF, gain equation predicts a gain error
less than 1% if A0 > 520
• For a settling time of 5 ns, we select RFC2 > 10 μs, i.e.,
RF = 40 MΩ
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 High-Speed Amplifier: Closed-Loop Small-Signal
Performance
• Applying a differential input step of 25 mV, we expect
an output around 99 mV (for 1% gain error)
• Fig. (a) is the differential output waveform and Fig. (b)
is a close-up showing the fine settling
• Final value is equal to 98.80 mV, a result of
insufficient open-loop gain

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 High-Speed Amplifier: Closed-Loop Small-Signal
Performance
• In order to increase gain, if we raise the length (and
hence width) of the first-stage input transistors, Cin
also increases, counteracting A0
• Instead, we double the (drawn) width and length of
the NMOS cascode transistors, obtaining the output
shown below
• Now the gain error is below 1%

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 High-Speed Amplifier: Closed-Loop Small-Signal
Performance
• If the output reaches 99.1 mV at t = , the settling
time ts to 1% precision must be defined as follows:
– Find the time at which Vout = 99.1 mV  0.01 
99.1 mV  99.1 mV  1 mV
– From Fig. (b) on previous slide, we obtain ts  5.8
ns
• From Fig. (a) on slide 104, output appears
“overcompensated”, thus speed can be improved

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 High-Speed Amplifier: Closed-Loop Small-Signal
Performance
• With CC = 0.3 pF and Rz = 700 Ω, we observe the
settling behavior shown below
• Settling time drops to 800 ps, a remarkable
improvement
• Rz is reduced in this case, moving the zero to higher
frequencies

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 High-Speed Amplifier: Op-Amp Scaling
• If the settling time is much shorter than the required
value, we can trade speed for power dissipation by
“linear scaling”
• Beginning with the response in Fig. (a), we scale
down all transistor widths and bias currents by a
factor of , thereby reducing the power by the same
factor while retaining the voltage gain and the
headroom

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 High-Speed Amplifier: Op-Amp Scaling
• With the load capacitance fixed, the output pole
(before compensation) is scaled down by a factor of 
[Fig. (b)]
• To maintain the same phase margin, the dominant
pole after compensation must also be scaled down by
this factor [Fig. (c)]
• Since the output impedance of first stage is multiplied
by , CC should remain unchanged
• To place the zero introduced by Rz atop ωp2/, we
multiply Rz by 

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 High-Speed Amplifier: Op-Amp Scaling
• Let us try  = 2
• Fig. (a) plots the output waveform, revealing the same
final values as before and an overdamped response
with ts  2.5 ns

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 High-Speed Amplifier: Op-Amp Scaling
• We can try scaling by another factor of 4 (i.e.,  = 8
with respect to the original design), observing the
heavily overdamped response in Fig. (b)
• Now, we adjust CC and Rz manually to optimize the
speed
• With CC = 0.15 pF and Rz = 9 kΩ, the step response
appears as in Fig. (c), exhibiting ts  4.5 ns

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 High-Speed Amplifier: Op-Amp Scaling
• Linear scaling along with some adjustment of CC and
Rz affords an eightfold reduction of power and area
• Minimal design effort needed because it does not
alter circuit’s gain and swing values
• Scaling gives rise to longer settling and higher noise
(and offset)

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 High-Speed Amplifier: Large-Signal
Behavior
• The amplifier’s ultimate test is with large signal
swings (1 Vpp,diff)
• Open-loop gain may drop as some transistors sustain
less VDS, and speed may suffer due to slewing
• In previous simulations, the differential output begins
from zero, jumps to some value, and returns to zero
• For large-signal tests, Vout must swing from -0.5 V to
+0.5 V, which can be accomplished by setting the
initial differential conditions at the op-amp inputs
such that Vout = -0.5 V at t = 0

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 High-Speed Amplifier: Large-Signal
Behavior
• The large-signal response is shown in Fig. (a)
• Total change in Vout from t  20 ns to t  40 ns is
equal to 987.4 mV, about 2.6 mV less than the allowed
value for 1% gain error
• Settling to 1% from final value is about 6 ns

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 High-Speed Amplifier: Large-Signal
Behavior
• Let us first deal with insufficient gain
• We can measure voltage gain of each stage under
these conditions by dividing its differential output
swing by its differential input swing (after the
voltages have settled)
• We obtain Av = 39.5 and 10.2 for first and second
stages respectively (in small-signal operation, these
values are equal to 46.3 and 11.2)
• Thus, open-loop gain has dropped from 518 to 403

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 High-Speed Amplifier: Large-Signal
Behavior
• To raise the gain, we double W and L of the NMOS
cascode transistors in the first stage and the NMOS
current sources in the second, arriving at the output
shown below
• Gain error is now less than 1%, but settling has
become longer because the pole associated with the
source of the NMOS cascode transistors degrades the
phase margin

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 High-Speed Amplifier: Large-Signal
Behavior
• To address the settling issue, we consider cascode
compensation
• With some iteration, we reach the design of Fig. (a)
• As shown in Fig. (b), the settling to 1% takes less than
5 ns
• This performance is achieved with a power of 370 μW

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 Summary
• Three steps in good analog design:
– Closely examine the circuit’s behavior and
understand the root cause of undesired
phenomena
– Adjust only the circuit parameters that relate to
the root cause – do not play blindly with any
random device
– Continue to explore various techniques and new
ideas, many a time improving performance

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