Operating Systems Administration

CCCS 321
Module 3: Memory Management
Graham Thorpe

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 Session Learning Outcomes
• Identify how memory is used in a computer system.
• Explain the difference between physical and logical memory

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 Memory Management
• Background
• Swapping
• Contiguous Memory Allocation
• Paging
• Structure of the Page Table
• Example: The Intel 32 and 64-bit Architectures
• Example: ARM Architecture

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 Background
• Program must be brought (from disk) into memory and placed
within a process for it to be run
• Main memory and registers are only storage CPU can access
directly
• Memory unit only sees a stream of addresses + read requests, or
address + data and write requests
• Register access in one CPU clock (or less)
• Main memory can take many cycles, causing a stall
• Cache sits between main memory and CPU registers
• Protection of memory required to ensure correct operation
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 Base and Limit Registers
• A pair of base and limit registers
define the logical address space
• CPU must check every memory access
generated in user mode to be sure it is
between base and limit for that user

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Hardware Address Protection

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 Logical vs. Physical Address Space
• The concept of a logical address space that is bound to a separate
physical address space is central to proper memory management
– Logical address – generated by the CPU; also referred to as virtual address
– Physical address – address seen by the hardware’s memory unit
• Logical and physical addresses are the same in compile-time and load-
time address-binding schemes; logical (virtual) and physical addresses
differ in execution-time address-binding scheme
• Logical address space is the set of all logical addresses generated by a
program
• Physical address space is the set of all physical addresses generated by
a program
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 Memory-Management Unit (MMU)
• Hardware device that at run time maps virtual to physical address
• Many methods possible, covered in the rest of this chapter
• To start, consider simple scheme where the value in the relocation
register is added to every address generated by a user process at the
time it is sent to memory
– Base register now called relocation register
• The user program deals with logical addresses; it never sees the real
physical addresses
– Execution-time binding occurs when reference is made to location in
memory
– Logical address bound to physical addresses

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 Dynamic Linking
• Static linking – system libraries and program code combined by the loader into
the binary program image
• Dynamic linking –linking postponed until execution time
• Small piece of code, stub, used to locate the appropriate memory-resident
library routine
• Stub replaces itself with the address of the routine, and executes the routine
• Operating system checks if routine is in processes’ memory address
– If not in address space, add to address space
• Dynamic linking is particularly useful for libraries
• System also known as shared libraries
• Consider applicability to patching system libraries
– Versioning may be needed
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 Swapping
• A process can be swapped temporarily out of memory to a backing
store, and then brought back into memory for continued execution
– Total physical memory space of processes can exceed physical memory
– Different than paging (which we’ll cover later in this unit)
• Backing store – fast disk large enough to accommodate copies of all
memory images for all users; must provide direct access to these
memory images
• Roll out, roll in – swapping variant used for priority-based scheduling
algorithms; lower-priority process is swapped out so higher-priority
process can be loaded and executed
• Major part of swap time is transfer time; total transfer time is directly
proportional to the amount of memory swapped
• System maintains a ready queue of ready-to-run processes which have
memory images on disk
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 Swapping (Cont.)
• Does the swapped out process need to swap back in to same
physical addresses?
– Depends on address binding method
– Consider pending I/O to / from process memory space
• Modified versions of swapping are found on many systems
(i.e., UNIX, Linux, and Windows)
– Swapping normally disabled
– Started if more than threshold amount of memory allocated
– Disabled again once memory demand reduced below threshold

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Schematic View of Swapping

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 Context Switch Time including Swapping
• If next processes to be put on CPU is not in memory, need to swap out
a process and swap in target process
• Context switch time can then be very high
• 100MB process swapping to hard disk with transfer rate of 50MB/sec
– Swap out time of 2000 ms
– Plus swap in of same sized process
– Total context switch swapping component time of 4000ms (4 seconds)
• Can reduce if reduce size of memory swapped – by knowing how
much memory really being used
– System calls to inform OS of memory use via request_memory() and
release_memory()

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 Context Switch Time and Swapping (Cont.)
• Other constraints as well on swapping
– Pending I/O – can’t swap out as I/O would occur to wrong process
– Or always transfer I/O to kernel space, then to I/O device
• Known as double buffering, adds overhead
• Standard swapping is no longer commonly used in modern
operating systems
– Often the term ‘swapping’ is still used even though it is actually the
more modern ‘paging’

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 Swapping on Mobile Systems
• Not typically supported
– Flash memory based
• Small amount of space
• Limited number of write cycles
• Poor throughput between flash memory and CPU on mobile platform
• Instead use other methods to free memory if low
– iOS asks apps to voluntarily relinquish allocated memory
• Read-only data thrown out and reloaded from flash if needed
• Failure to free can result in termination
– Android terminates apps if low free memory, but first writes application
state to flash for fast restart
– Both OSes support paging as discussed below
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 Dynamic Storage-Allocation Problem
• First-fit: Allocate the first hole that is big enough
How to satisfy a request of size n from a list of free holes?

• Best-fit: Allocate the smallest hole that is big enough; must

search entire list, unless ordered by size
– Produces the smallest leftover hole

• Worst-fit: Allocate the largest hole; must also search entire list

– Produces theand
First-fit largest
best-fit leftover hole in terms of speed and storage
better than worst-fit
utilization

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 Fragmentation
• External Fragmentation – total memory space exists to satisfy
a request, but it is not contiguous
• Internal Fragmentation – allocated memory may be slightly
larger than requested memory; this size difference is memory
internal to a partition, but not being used
• First fit analysis reveals that given N blocks allocated, 0.5 N
blocks lost to fragmentation
– 1/3 may be unusable -> 50-percent rule

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 Fragmentation (Cont.)
• Reduce external fragmentation by compaction
– Shuffle memory contents to place all free memory together in one
large block
– Compaction is possible only if relocation is dynamic, and is done at
execution time
– I/O problem
• Latch job in memory while it is involved in I/O
• Do I/O only into OS buffers
• Now consider that backing store has same fragmentation
problems

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 Paging
• Physical address space of a process can be noncontiguous; process is allocated
physical memory whenever the latter is available
– Avoids external fragmentation
– Avoids problem of varying sized memory chunks
• Divide physical memory into fixed-sized blocks called frames
– Size is power of 2, between 512 bytes and 16 Mbytes
• Divide logical memory into blocks of same size called pages
• Keep track of all free frames
• To run a program of size N pages, need to find N free frames and load program
• Set up a page table to translate logical to physical addresses
• Backing store (e.g. hard drive) likewise split into pages
• Still have Internal fragmentation

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 Address Translation Scheme
• Address generated by CPU is divided into:
– Page number (p) – used as an index into a page table which contains
base address of each page in physical memory
– Page offset (d) – combined with base address to define the physical
memory address that is sent to the memory unit

page number page offset

p d
m -n n

– For given logical address space 2m and page size 2n

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Paging Hardware

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Paging Model of Logical and Physical Memory

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 Paging Example

n=2 and m=4 32-byte memory and 4-byte pages

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 Paging (Cont.)
• Calculating internal fragmentation
– Page size = 2,048 bytes
– Process size = 72,766 bytes
– 35 pages + 1,086 bytes
– Internal fragmentation of 2,048 - 1,086 = 962 bytes
– Worst case fragmentation = 1 frame – 1 byte
– On average fragmentation = 1 / 2 frame size
– So small frame sizes desirable?
– But each page table entry takes memory to track
– Page sizes growing over time
• Solaris supports two page sizes – 8 KB and 4 MB
• Process view and physical memory now very different
• By implementation process can only access its own memory
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 Free Frames

Before allocation After allocation

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 Implementation of Page Table
• Page table is kept in main memory
• Page-table base register (PTBR) points to the page table
• Page-table length register (PTLR) indicates size of the page
table
• In this scheme every data/instruction access requires two
memory accesses
– One for the page table and one for the data / instruction
• The two memory access problem can be solved by the use of a
special fast-lookup hardware cache called associative memory
or translation look-aside buffers (TLBs)
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 Implementation of Page Table (Cont.)
• Some TLBs store address-space identifiers (ASIDs) in each TLB
entry – uniquely identifies each process to provide address-
space protection for that process
– Otherwise need to flush at every context switch
• TLBs typically small (64 to 1,024 entries)
• On a TLB miss, value is loaded into the TLB for faster access
next time
– Replacement policies must be considered
– Some entries can be wired down for permanent fast access

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 Memory Protection
• Memory protection implemented by associating protection bit
with each frame to indicate if read-only or read-write access is
allowed
– Can also add more bits to indicate page execute-only, and so on
• Valid-invalid bit attached to each entry in the page table:
– “valid” indicates that the associated page is in the process’ logical
address space, and is thus a legal page
– “invalid” indicates that the page is not in the process’ logical address
space
– Or use page-table length register (PTLR)
• Any violations result in a trap to the kernel
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Valid (v) or Invalid (i) Bit In A Page Table

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 Shared Pages
• Shared code
– One copy of read-only (reentrant) code shared among processes (i.e.,
text editors, compilers, window systems)
– Similar to multiple threads sharing the same process space
– Also useful for interprocess communication if sharing of read-write
pages is allowed
• Private code and data
– Each process keeps a separate copy of the code and data
– The pages for the private code and data can appear anywhere in the
logical address space

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Shared Pages Example

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 Example: The Intel 32 and 64-bit Architectures
• Dominant industry chips for desktops/laptops and servers.
• Pentium CPUs are 32-bit and called IA-32 or X86 architecture
• Current Intel CPUs are 64-bit and called IA-64 or x64
architecture
• AMD has a line of CPUs that are x64 compatible and competes
with Intel for market share.
• Many variations in the chips
• Dominant CPU architecture for smartphones and tablets is
ARM. https://simple.wikipedia.org/wiki/ARM_architecture

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Intel IA-32 Paging Architecture

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 Intel IA-32 Page Address Extensions
 32-bit address limits led Intel to create page address extension (PAE),
allowing 32-bit apps access to more than 4GB of memory space
 Paging went to a 3-level scheme
 Top two bits refer to a page directory pointer table
 Page-directory and page-table entries moved to 64-bits in size
 Net effect is increasing address space to 36 bits – 64GB of physical
memory

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 Intel x86-64
 Current generation Intel x86 architecture
 64 bits is ginormous (> 16 exabytes)
 In practice only implement 48 bit addressing
 Page sizes of 4 KB, 2 MB, 1 GB
 Four levels of paging hierarchy
 Can also use PAE so virtual addresses are 48 bits and physical
addresses are 52 bits

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 Example: ARM Architecture
 Dominant mobile platform chip
(Apple iOS and Google Android
devices for example)
 Modern, energy efficient, 32-bit
CPU
 4 KB and 16 KB pages
 1 MB and 16 MB pages (termed
sections)
 One-level paging for sections, two-
level for smaller pages
 Two levels of TLBs
 Outer level has two micro
TLBs (one data, one
instruction)
 Inner is single main TLB
 First inner is checked, on
miss outers are checked,
and on miss page table
walk performed by CPU

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Virtual Memory

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 Virtual Memory
• Background
• Demand Paging
• Copy-on-Write
• Page Replacement
• Allocation of Frames
• Thrashing
• Memory-Mapped Files
• Allocating Kernel Memory
• Other Considerations
• Operating-System Examples
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 Objectives
• To describe the benefits of a virtual memory system
• To explain the concepts of demand paging, page-replacement
algorithms, and allocation of page frames
• To discuss the principle of the working-set model
• To examine the relationship between shared memory and
memory-mapped files
• To explore how kernel memory is managed

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 Background
• Code needs to be in memory to execute, but entire program rarely
used
– Error code, unusual routines, large data structures
• Entire program code not needed at same time
• Consider ability to execute partially-loaded program
– Program no longer constrained by limits of physical memory
– Each program takes less memory while running -> more programs run at the
same time
• Increased CPU utilization and throughput with no increase in response time or
turnaround time
– Less I/O needed to load or swap programs into memory -> each user
program runs faster
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 Background (Cont.)
• Virtual memory – separation of user logical memory from
physical memory
– Only part of the program needs to be in memory for execution
– Logical address space can therefore be much larger than physical
address space
– Allows address spaces to be shared by several processes
– Allows for more efficient process creation
– More programs running concurrently
– Less I/O needed to load or swap processes

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Virtual Memory That is Larger Than Physical Memory

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 Virtual-address Space
 Usually design logical address space for stack to start at Max
logical address and grow “down” while heap grows “up”
 Maximizes address space use
 Unused address space between the two is hole
 No physical memory needed until heap or stack grows to
a given new page
 Enables sparse address spaces with holes left for growth,
dynamically linked libraries, etc
 System libraries shared via mapping into virtual address space
 Shared memory by mapping pages read-write into virtual address
space
 Pages can be shared during fork(), speeding process creation

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Shared Library Using Virtual Memory

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 Demand Paging
• Could bring entire process into memory at load time
• Or bring a page into memory only when it is needed
– Less I/O needed, no unnecessary I/O
– Less memory needed
– Faster response
– More users
• Similar to paging system with swapping (diagram on right)
• Page is needed  reference to it
– invalid reference  abort
– not-in-memory  bring to memory
• Lazy swapper – never swaps a page into memory unless
page will be needed
– Swapper that deals with pages is a pager

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 Basic Concepts
• With swapping, pager guesses which pages will be used before
swapping out again
• Instead, pager brings in only those pages into memory
• How to determine that set of pages?
– Need new MMU functionality to implement demand paging
• If pages needed are already memory resident
– No difference from non demand-paging
• If page needed and not memory resident
– Need to detect and load the page into memory from storage
• Without changing program behavior
• Without programmer needing to change code
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 Valid-Invalid Bit
• With each page table entry a valid–invalid bit is
associated
(v  in-memory – memory resident, i  not-in-memory)
• Initially valid–invalid bit is set to i on all entries
• Example of a page table snapshot:

• During MMU address translation, if valid–invalid bit in

page table entry is i  page fault
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Page Table When Some Pages Are Not in Main Memory

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 Page Fault

• If there is a reference to a page, first reference to that page will trap to

operating system:
page fault
1. Operating system looks at another table to decide:
– Invalid reference  abort
– Just not in memory
2. Find free frame
3. Swap page into frame via scheduled disk operation
4. Reset tables to indicate page now in memory
Set validation bit = v
5. Restart the instruction that caused the page fault
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Steps in Handling a Page Fault

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 Aspects of Demand Paging
• Extreme case – start process with no pages in memory
– OS sets instruction pointer to first instruction of process, non-memory-resident -> page
fault
– And for every other process pages on first access
– Pure demand paging
• Actually, a given instruction could access multiple pages -> multiple page faults
– Consider fetch and decode of instruction which adds 2 numbers from memory and stores
result back to memory
– Pain decreased because of locality of reference
• Hardware support needed for demand paging
– Page table with valid / invalid bit
– Secondary memory (swap device with swap space)
– Instruction restart

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 What Happens if There is no Free Frame?
• Used up by process pages
• Also in demand from the kernel, I/O buffers, etc
• How much to allocate to each?
• Page replacement – find some page in memory, but not really
in use, page it out
– Algorithm – terminate? swap out? replace the page?
– Performance – want an algorithm which will result in minimum
number of page faults
• Same page may be brought into memory several times

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 Page Replacement
• Prevent over-allocation of memory by modifying page-fault
service routine to include page replacement
• Use modify (dirty) bit to reduce overhead of page transfers –
only modified pages are written to disk
• Page replacement completes separation between logical
memory and physical memory – large virtual memory can be
provided on a smaller physical memory

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Need For Page Replacement

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 Basic Page Replacement
1. Find the location of the desired page on disk

2. Find a free frame:

- If there is a free frame, use it
- If there is no free frame, use a page replacement algorithm to select a victim
frame
- Write victim frame to disk if dirty

3. Bring the desired page into the (newly) free frame; update the page and frame tables

4. Continue the process by restarting the instruction that caused the trap

Note now potentially 2 page transfers for page fault – increasing EAT

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Page Replacement

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 Page and Frame Replacement Algorithms
• Frame-allocation algorithm determines
– How many frames to give each process
– Which frames to replace
• Page-replacement algorithm
– Want lowest page-fault rate on both first access and re-access
• Evaluate algorithm by running it on a particular string of memory references
(reference string) and computing the number of page faults on that string
– String is just page numbers, not full addresses
– Repeated access to the same page does not cause a page fault
– Results depend on number of frames available
• In all our examples, the reference string of referenced page numbers is
7,0,1,2,0,3,0,4,2,3,0,3,0,3,2,1,2,0,1,7,0,1

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Graph of Page Faults Versus The Number of Frames

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 Applications and Page Replacement
• All of these algorithms have OS guessing about future page
access
• Some applications have better knowledge – i.e. databases
• Memory intensive applications can cause double buffering
– OS keeps copy of page in memory as I/O buffer
– Application keeps page in memory for its own work
• Operating system can given direct access to the disk, getting
out of the way of the applications
– Raw disk mode
• Bypasses buffering, locking, etc
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 Non-Uniform Memory Access
• So far all memory accessed equally
• Many systems are NUMA – speed of access to memory varies
– Consider system boards containing CPUs and memory,
interconnected over a system bus
• Some multi-CPU systems will optimize performance so that CPUs can have
higher performance to different memory blocks.
• Optimal performance comes from allocating memory “close
to” the CPU on which the thread is scheduled
– And modifying the scheduler to schedule the thread on the same
system board when possible

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 Thrashing
• If a process does not have “enough” pages, the page-fault rate is
very high
– Page fault to get page
– Replace existing frame
– But quickly need replaced frame back
– This leads to:
• Low CPU utilization
• Operating system thinking that it needs to increase the degree of
multiprogramming
• Another process added to the system

• Thrashing  a process is busy swapping pages in and out

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Thrashing (Cont.)

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