Single Cycle Processor Design

COE 233
Logic Design and Computer Organization
Dr. Muhamed Mudawar

King Fahd University of Petroleum and Minerals

 Presentation Outline

 Designing a Processor: Step-by-Step

 Datapath Components and Clocking

 Assembling an Adequate Datapath

 Controlling the Execution of Instructions

 Main, ALU, and PC Control

Single Cycle Processor Design COE 233 – Logic Design and Computer Organization © Muhamed Mudawar – slide 2
 Designing a Processor: Step-by-Step
1. Analyze instruction set => datapath requirements
 The meaning of each instruction is given by the register transfers

 Datapath must include storage elements for ISA registers

 Datapath must support each register transfer

2. Select datapath components and clocking methodology

3. Assemble datapath meeting the requirements

4. Analyze implementation of each instruction

 Determine the setting of control signals for register transfer

5. Assemble the control logic

Single Cycle Processor Design COE 233 – Logic Design and Computer Organization © Muhamed Mudawar – slide 3
 Review of MIPS Instruction Formats
 All instructions are 32-bit wide
 Three instruction formats: R-type, I-type, and J-type

Op6 Rs5 Rt5 Rd5 sa5 funct6

Op6 Rs5 Rt5 immediate16

Op6 address26

 Op6: 6-bit opcode of the instruction

 Rs5, Rt5, Rd5: 5-bit source and destination register numbers
 sa5: 5-bit shift amount used by shift instructions
 funct6: 6-bit function field for R-type instructions
 immediate16: 16-bit immediate constant or PC-relative offset
 address26: 26-bit target address of the jump instruction

Single Cycle Processor Design COE 233 – Logic Design and Computer Organization © Muhamed Mudawar – slide 4
 MIPS Subset of Instructions
 Only a subset of the MIPS instructions is considered
 ALU instructions (R-type): add, sub, and, or, xor, slt
 Immediate instructions (I-type): addi, slti, andi, ori, xori
 Load and Store (I-type): lw, sw
 Branch (I-type): beq, bne
 Jump (J-type): j

 This subset does not include all the integer instructions

 But sufficient to illustrate design of datapath and control
 Concepts used to implement the MIPS subset are used to
construct a broad spectrum of computers
Single Cycle Processor Design COE 233 – Logic Design and Computer Organization © Muhamed Mudawar – slide 5
 Details of the MIPS Subset
Instruction Meaning Format
add rd, rs, rt addition op6 = 0 rs5 rt5 rd5 0 0x20
sub rd, rs, rt subtraction op6 = 0 rs5 rt5 rd5 0 0x22
and rd, rs, rt bitwise and op6 = 0 rs5 rt5 rd5 0 0x24
or rd, rs, rt bitwise or op6 = 0 rs5 rt5 rd5 0 0x25
xor rd, rs, rt exclusive or op6 = 0 rs5 rt5 rd5 0 0x26
slt rd, rs, rt set on less than op6 = 0 rs5 rt5 rd5 0 0x2a
addi rt, rs, imm16 add immediate 0x08 rs5 rt5 imm16
slti rt, rs, imm16 slt immediate 0x0a rs5 rt5 imm16
andi rt, rs, imm16 and immediate 0x0c rs5 rt5 imm16
ori rt, rs, imm16 or immediate 0x0d rs5 rt5 imm16
xori rt, imm16 xor immediate 0x0e rs5 rt5 imm16
lw rt, imm16(rs) load word 0x23 rs5 rt5 imm16
sw rt, imm16(rs) store word 0x2b rs5 rt5 imm16
beq rs, rt, branch if equal 0x04 rs5 rt5 offset16
offset 16

bne rs, rt, branch not equal 0x05 rs5 rt5 offset16
offset16
SinglejCycle Processor Design
address jump 0x02 address26
26
COE 233 – Logic Design and Computer Organization © Muhamed Mudawar – slide 6
 Instruction Fetch/Execute
 R-type Fetch instruction: Instruction ← MEM[PC]
Fetch operands: data1 ← Reg(rs), data2 ← Reg(rt)
Execute operation: ALU_result ← func(data1, data2)
Write ALU result: Reg(rd) ← ALU_result
Next PC address: PC ← PC + 4
 I-type Fetch instruction: Instruction ← MEM[PC]
Fetch operands: data1 ← Reg(rs), data2 ← Extend(imm16)
Execute operation: ALU_result ← op(data1, data2)
Write ALU result: Reg(rt) ← ALU_result
Next PC address: PC ← PC + 4
 BEQ Fetch instruction: Instruction ← MEM[PC]
Fetch operands: data1 ← Reg(rs), data2 ← Reg(rt)
Equality: zero ← subtract(data1, data2)
Branch: if (zero) PC ← PC + 4 + 4×sign_ext(offset16)
else PC ← PC + 4
Single Cycle Processor Design COE 233 – Logic Design and Computer Organization © Muhamed Mudawar – slide 7
 Instruction Fetch/Execute – cont’d
 LW Fetch instruction: Instruction ← MEM[PC]
Fetch base register: base ← Reg(rs)
Calculate address: address ← base + sign_extend(imm16)
Read memory: data ← MEM[address]
Write register Rt: Reg(rt) ← data
Next PC address: PC ← PC + 4

 SW Fetch instruction: Instruction ← MEM[PC]

Fetch registers: base ← Reg(rs), data ← Reg(rt)
Calculate address: address ← base + sign_extend(imm16)
Write memory: MEM[address] ← data
Next PC address: PC ← PC + 4

 Jump Fetch instruction: Instruction ← MEM[PC] concatenation

Target PC address: target ← { PC[31:28] , address26 , 00 }

Jump: PC ← target

Single Cycle Processor Design COE 233 – Logic Design and Computer Organization © Muhamed Mudawar – slide 8
 Requirements of the Instruction Set
 Memory
 Instruction memory where instructions are stored
 Data memory where data is stored
 Registers
 31 × 32-bit general purpose registers, R0 is always zero
 Read source register Rs
 Read source register Rt
 Write destination register Rt or Rd
 Program counter PC register and Adder to increment PC
 Sign and Zero extender for immediate constant
 ALU for executing instructions

Single Cycle Processor Design COE 233 – Logic Design and Computer Organization © Muhamed Mudawar – slide 9
 Next . . .

 Designing a Processor: Step-by-Step

 Datapath Components and Clocking

 Assembling an Adequate Datapath

 Controlling the Execution of Instructions

 Main, ALU, and PC Control

Single Cycle Processor Design COE 233 – Logic Design and Computer Organization © Muhamed Mudawar – slide 10
 Components of the Datapath
 Combinational Elements 32

0
 ALU, Adder 16 32 m A 32
zero

Extend u L ALU result

x U
 Immediate extender ExtOp 1
32 overflow

select ALUOp
 Multiplexers

 Storage Elements Instruction

32
Data
32
Memory
32 32 32

 Instruction memory Address

PC
Address
32
32 Data_out
Instruction Data_in
 Data memory clk Memory

clk
 PC register Mem Mem
Registers Read Write
5 32
 Register file RA BusA
5 32
RB BusB
 Clocking methodology 5
RW
BusW

 Timing of writes clk

32
RegWrite

Single Cycle Processor Design COE 233 – Logic Design and Computer Organization © Muhamed Mudawar – slide 11
 Register Element
 Register
Data_In
 Similar to the D-type Flip-Flop
n bits

 n-bit input and output

Write
Enable
WE Register Clock
 Write Enable (WE):
n bits
 Enable / disable writing of register
Data_Out
 Negated (0): Data_Out will not change

 Asserted (1): Data_Out will become Data_In after clock edge

 Edge triggered Clocking

 Register output is modified at clock edge

Single Cycle Processor Design COE 233 – Logic Design and Computer Organization © Muhamed Mudawar – slide 12
 MIPS Register File
 Register File consists of 31 × 32-bit registers
 BusA and BusB: 32-bit output busses for reading 2 registers
 BusW: 32-bit input bus for writing a register when RegWrite is 1
 Two registers read and one written in a cycle
Register
 Registers are selected by: 5
File BusA 32
RA

 RA selects register to be read on BusA 5

RB
32
5 BusB
 RB selects register to be read on BusB RW

 RW selects the register to be written Clock

BusW

 Clock input RegWrite

32

 The clock input is used ONLY during write operation

 During read, register file behaves as a combinational logic block
 RA or RB valid => BusA or BusB valid after access time

Single Cycle Processor Design COE 233 – Logic Design and Computer Organization © Muhamed Mudawar – slide 13
 Details of the Register File
RA 5 RB 5
32
Decoder "0" Decoder "0"
Tri-state
R0 is not
WE R1 buffers
used
32 32

.
Decoder

RW WE R2
.
5 . 32

.
.
32 32 . 32
BusW BusA
WE R31

RegWrite 32
32
Clock BusB

Single Cycle Processor Design COE 233 – Logic Design and Computer Organization © Muhamed Mudawar – slide 14
 Tri-State Buffers
 Allow multiple sources to drive a single bus
 Two Inputs: Enable
 Data_in
 Enable (to enable output) Data_in Data_out

 One Output: Data_out

 If (Enable) Data_out = Data_in
else Data_out = High Impedance state (output is disconnected)

 Tri-state buffers can be Data_0

Output
used to build multiplexors
Data_1
Select

Single Cycle Processor Design COE 233 – Logic Design and Computer Organization © Muhamed Mudawar – slide 15
 Building a Multifunction ALU
2
Shift/Rotate

SLL = 00 SLT: ALU does a SUB

Operation

SRL = 00 Shift Amount 5

then check the sign
SRA = 01 and overflow
Shifter
ROR = 11
32

c0 0
A 32 ALU Result
sign
A SLT 1 32
d
d 2
B 32
Arithmetic
Operation

32 e
r 3
ADD = 0
SUB = 1 2
overflow zero

0 ALU
Selection
1
Logic Unit Shift = 00
2 SLT = 01
AND = 00 Arith = 10
Operation

3
Logical

OR = 01 Logic = 11
XOR = 10 2
NOR = 11

Single Cycle Processor Design COE 233 – Logic Design and Computer Organization © Muhamed Mudawar – slide 16
 Instruction and Data Memories
 Instruction memory needs only provide read access
 Because datapath does not write instructions
 Behaves as combinational logic for read 32
Address Instruction
32

 Address selects Instruction after access time Instruction

Memory
 Data Memory is used for load and store
 MemRead: enables output on Data_out
Data
 Address selects the word to put on Data_out Memory
32 32
 MemWrite: enables writing of Data_in 32
Address Data_out

Data_in
 Address selects the memory word to be written
Clock
 The Clock synchronizes the write operation

 Separate instruction and data memories MemRead MemWrite

 Later, we will replace them with caches

Single Cycle Processor Design COE 233 – Logic Design and Computer Organization © Muhamed Mudawar – slide 17
 Next . . .

 Designing a Processor: Step-by-Step

 Datapath Components and Clocking

 Assembling an Adequate Datapath

 Controlling the Execution of Instructions

 Main, ALU, and PC Control

Single Cycle Processor Design COE 233 – Logic Design and Computer Organization © Muhamed Mudawar – slide 18
 Instruction Fetching Datapath
 We can now assemble the datapath from its components
 For instruction fetching, we need …
 Program Counter (PC) register
 Instruction Memory
Improved datapath
 Adder for incrementing PC
increments upper 30
bits of PC by 1
next PC
4
The least significant 2 bits of next PC

A the PC are ‘00’ since PC is Improved

d
32
32
d a multiple of 4 30
+1 Datapath
30
32 32

00
00

Instruction Instruction
32
Datapath does not 32
PC

Address Address

PC
handle branch or
Instruction Instruction
clk Memory jump instructions clk Memory

Single Cycle Processor Design COE 233 – Logic Design and Computer Organization © Muhamed Mudawar – slide 19
 Datapath for R-type Instructions
Op6 Rs5 Rt5 Rd5 sa5 funct6

RegWr
ALUOp
30
+1
Instruction Registers 32
Memory Rs 5
30 32 RA BusA A 32
00

Instruction Rt 5 L
32 RB
Address BusB 32 U
PC

Rd 5
RW ALU result
BusW

clk

Rs and Rt fields select two BusA & BusB provide data input to ALU.
registers to read. Rd field ALU result is connected to BusW
selects register to write
Same clock updates PC and Rd register
 Control signals
 ALUOp is the ALU operation as defined in the funct field for R-type
 RegWr is used to enable the writing of the ALU result

Single Cycle Processor Design COE 233 – Logic Design and Computer Organization © Muhamed Mudawar – slide 20
 Datapath for I-type ALU Instructions
Op6 Rs5 Rt5 immediate16

RegWr
ALUOp
30
+1
Instruction Registers 32
Memory Rs 5
30 32 RA BusA A 32
00

Instruction 5
32 L
32 RB
Address BusB 32 U
PC

Rt 5
RW ALU result
BusW

clk ExtOp Same clock edge

Imm16 updates PC and
Rt selects register to Extender
Rt
write, not Rd
Second ALU input comes from the extended
 Control signals immediate. RB and BusB are not used

 ALUOp is derived from the Op field for I-type instructions

 RegWr is used to enable the writing of the ALU result
 ExtOp is used to control the extension of the 16-bit immediate

Single Cycle Processor Design COE 233 – Logic Design and Computer Organization © Muhamed Mudawar – slide 21
 Combining R-type & I-type Datapaths
RegWr

+1
ALUOp A mux selects RW
30
Instruction Registers 32 as either Rt or Rd
Memory Rs 5
30 32 RA BusA A 32
00

Instruction Rt 5 32 L Another mux selects

32 RB BusB 0 U
Address
2nd ALU input as
PC

0
RW 1
Rd
1 BusW
32
either data on BusB
clk RegDst ExtOp ALUSrc or the extended
ALU result immediate
Extender
Imm16

 Control signals
 ALUOp is derived from either the Op or the funct field
 RegWr enables the writing of the ALU result
 ExtOp controls the extension of the 16-bit immediate
 RegDst selects the register destination as either Rt or Rd
 ALUSrc selects the 2nd ALU source as BusB or extended immediate

Single Cycle Processor Design COE 233 – Logic Design and Computer Organization © Muhamed Mudawar – slide 22
 Controlling ALU Instructions
RegWr = 1
ALUOp
30
+1 For R-type ALU
Instruction Registers 32
Memory Rs 5 instructions, RegDst is ‘1’
30 RA BusA A
32 32 to select Rd on RW and
00

Instruction Rt 5 32 L
32 RB BusB 0 U ALUSrc is ‘0’ to select
Address
PC

Rd
0
RW 1 BusB as second ALU
1 BusW
input. The active part of
ALUSrc = 0
clk RegDst = 1 ExtOp datapath is shown in
ALU result green
Extender
Imm16

RegWr = 1

+1
ALUOp For I-type ALU
30
Instruction Registers 32 instructions, RegDst is ‘0’
Rs 5
30 Memory
32 RA BusA A to select Rt on RW and
32
00

32
Instruction Rt 5
RB
32 L ALUSrc is ‘1’ to select
Address
BusB 0 U Extended immediate as
PC

0
Rd RW 1
1 BusW second ALU input. The
ExtOp ALUSrc = 1 active part of datapath is
clk RegDst = 0
ALU result
shown in green
32
Extender
Imm16

Single Cycle Processor Design COE 233 – Logic Design and Computer Organization © Muhamed Mudawar – slide 23
 Details of the Extender
 Two types of extensions
 Zero-extension for unsigned constants
 Sign-extension for signed constants
 Control signal ExtOp indicates type of extension
 Extender Implementation: wiring and one AND gate

ExtOp = 0  Upper16 = 0
.. Upper
.
ExtOp 16 bits ExtOp = 1 
Upper16 = sign bit
.. Lower
Imm16 .
16 bits

Single Cycle Processor Design COE 233 – Logic Design and Computer Organization © Muhamed Mudawar – slide 24
 Adding Data Memory to Datapath
 A data memory is added for load and store instructions
ExtOp ALUOp MemRd MemWr
Imm16 32 ALUSrc
E WBdata
ALU result

30
+1
Instruction Rs 5 32
RA BusA Data
30 Memory Memory
32
Registers A 32
0
32
00

Instruction Rt 5 L Address
32 RB 32
Address
BusB 0 U Data_out 1
PC

0
Rd RW Data_in
1 BusW 1
32
RegDst Reg
Wr
clk

ALU calculates data memory address A 3rd mux selects data on BusW as either
ALU result or memory data_out
 Additional Control signals
BusB is connected to Data_in of Data
 MemRd for load instructions Memory for store instructions
 MemWr for store instructions
 WBdata selects data on BusW as ALU result or Memory Data_out

Single Cycle Processor Design COE 233 – Logic Design and Computer Organization © Muhamed Mudawar – slide 25
 Controlling the Execution of Load
ExtOp = 1 ALUOp MemRd MemWr
= ADD =1 =0
ALUSrc
Imm16 32 WBdata
=1
E ALU result =1

30
+1
Instruction Rs 5 32
RA BusA Data
30 Memory Memory
32
Registers A 32
0
32
00

Instruction Rt 5 L Address
32 RB 32
Address
BusB 0 U Data_out 1
PC

0
Rd RW Data_in
1 BusW 1
32
RegDst
RegWr
=0
clk =1

RegDst = ‘0’ selects Rt RegWr = ‘1’ to enable ExtOp = 1 to sign-extend

as destination register writing of register file Immmediate16 to 32 bits

ALUSrc = ‘1’ selects extended ALUOp = ‘ADD’ to calculate data memory

immediate as second ALU input address as Reg(Rs) + sign-extend(Imm16)

MemRd = ‘1’ to read WBdata = ‘1’ places the data read Clock edge updates PC
data memory from memory on BusW and Register Rt

Single Cycle Processor Design COE 233 – Logic Design and Computer Organization © Muhamed Mudawar – slide 26
 Controlling the Execution of Store
ExtOp = 1 ALUOp MemRd MemWr
= ADD =0 =1
ALUSrc
Imm16 32 WBdata
=1
E ALU result =X

30
+1
Instruction Rs 5 32
RA BusA Data
30 Memory Memory
32
Registers A 32
0
32
00

Instruction Rt 5 L Address
32 RB 32
Address
BusB 0 U Data_out 1
PC

0
Rd RW Data_in
1 BusW 1
32
RegDst
RegWr
=X
clk =0

RegDst = ‘X’ because no RegWr = ‘0’ to disable ExtOp = 1 to sign-extend

register is written writing of register file Immmediate16 to 32 bits

ALUSrc = ‘1’ selects extended ALUOp = ‘ADD’ to calculate data memory

immediate as second ALU input address as Reg(Rs) + sign-extend(Imm16)

MemWr = ‘1’ to write WBdata = ‘X’ because don’t care Clock edge updates PC
data memory what data is put on BusW and Data Memory

Single Cycle Processor Design COE 233 – Logic Design and Computer Organization © Muhamed Mudawar – slide 27
 Adding Jump and Branch to Datapath
PCSrc

Branch Target Address Adding a mux at the PC input

2
Jump Target = PC[31:28] ‖ Imm26
1

0
ExtOp New adder for computing branch
Next PC Address
target address
Imm16 +
E
+1 Zero ALU result

Instruction Rs BusA
Data
RA
A
00

Memory Memory
Registers L Address
Rt 0
Address U
PC

RB 1 Data_out 1
Instruction 0 BusB 0
Rd Data_in
1 RW
BusW

clk

Op Reg RegW ALU ALU Mem Mem WB

Dst r Src Op Rd Wr data

 Additional Control Signals

 PCSrc for PC control: 1 for a jump and 2 for a taken branch
 Zero flag for branch control: whether branch is taken or not
Single Cycle Processor Design COE 233 – Logic Design and Computer Organization © Muhamed Mudawar – slide 28
 Controlling the Execution of a Jump
PCSrc
=1
Branch Target Address
2
Jump Target = PC[31:28] ‖ Imm26 If (Opcode == J) then
1

0
ExtOp = X PCSrc = 1 (Jump Target)
Next PC Address

Imm16 +
E
+1 Zero = X ALU result

Instruction Rs BusA
Data
RA
A
00

Memory Memory
Registers L Address
Rt 0
Address U
PC

RB 1 Data_out 1
Instruction 0 BusB 0
Rd Data_in
1 RW
BusW

clk
Reg Reg ALU ALU Mem Mem WB
Op Dst Wr Src Op Rd Wr data
=J =X =0 =X =X =0 =0 =X

MemRd = MemWr = RegWr = 0, Don't care about other control signals

Clock edge updates PC register only

Single Cycle Processor Design COE 233 – Logic Design and Computer Organization © Muhamed Mudawar – slide 29
 Controlling the Execution of a Branch
PCSrc
=2
Branch Target Address
2
If (Opcode == BEQ && Zero == 1)
Jump Target = PC[31:28] ‖ Imm26
1
ExtOp = 1
then PCSrc = 2 (Branch Target)
0
Next PC Address
else PCSrc = 0 (Next PC)
Imm16 +
E
+1 Zero = 1 ALU result

Instruction Rs BusA
Data
RA
A
00

Memory Memory
Registers L Address
Rt 0
Address U
PC

RB 1 Data_out 1
Instruction 0 BusB 0
Rd Data_in
1 RW
BusW

clk
Reg Reg ALU ALU Mem Mem WB
Op Dst Wr Src Op Rd Wr data
BEQ =X =0 =0 = SUB =0 =0 =X

ALUSrc = 0, ALUOp = SUB, ExtOp = 1, MemRd = MemWr = RegWr = 0

Clock edge updates PC register only

Single Cycle Processor Design COE 233 – Logic Design and Computer Organization © Muhamed Mudawar – slide 30
 Next . . .

 Designing a Processor: Step-by-Step

 Datapath Components and Clocking

 Assembling an Adequate Datapath

 Controlling the Execution of Instructions

 Main, ALU, and PC Control

Single Cycle Processor Design COE 233 – Logic Design and Computer Organization © Muhamed Mudawar – slide 31
 Main, ALU, and PC Control

Zero
Instruction

Datapath
0 Memory
A
PC
1 Address L
32
2 Instruction U

RegDst

WBdata
MemRd

MemWr
ALUSrc
RegWr

ExtOp
Op6
PCSrc ALUOp
funct6
Zero
PC Main ALU
Op 6

Control Control Control

PC Control Input Main Control Input ALU Control Input
 6-bit opcode  6-bit opcode field
 6-bit opcode field
 ALU zero flag  6-bit function field
PC Control Output Main Control Output ALU Control Output
 PCSrc signal  Main control signals  ALUOp signal for ALU

Single Cycle Processor Design COE 233 – Logic Design and Computer Organization © Muhamed Mudawar – slide 32
 Single-Cycle Datapath + Control
Branch Target Address

Jump Target = PC[31:28] ‖ Imm26

ExtOp
Next PC Address

Imm16 +
Ext
+1 ALU result
Zero

Instruction Rs BusA
Data
RA
A
00

0 Memory Memory
Registers L Address
Rt 0
Address U
PC

1 RB 1 Data_out
Instruction 1
2 0 BusB 0
Rd Data_in
1 RW
BusW
PCSrc
clk
ALUop
func
MemRd WBdata
RegDst RegWr
Op ALU
PC
Ctrl MemWr
Ctrl
ExtOp ALUSrc

Main
Zero
Control

Single Cycle Processor Design COE 233 – Logic Design and Computer Organization © Muhamed Mudawar – slide 33
 Main Control Signals
Signal Effect when ‘0’ Effect when ‘1’

RegDst Destination register = Rt Destination register = Rd

Destination register (Rt or Rd) is

RegWr No register is written
written with the data on BusW

ExtOp 16-bit immediate is zero-extended 16-bit immediate is sign-extended

Second ALU operand is the value of Second ALU operand is the value of
ALUSrc
register Rt that appears on BusB the extended 16-bit immediate

Data memory is read

MemRd Data memory is NOT read
Data_out ← Memory[address]

Data memory is written

MemWr Data Memory is NOT written
Memory[address] ← Data_in

WBdata BusW = ALU result BusW = Data_out from Memory

Single Cycle Processor Design COE 233 – Logic Design and Computer Organization © Muhamed Mudawar – slide 34
 Main Control Truth Table
Op RegDst RegWr ExtOp ALUSrc MemRd MemWr WBdata

R-type 1 = Rd 1 X 0 = BusB 0 0 0 = ALU

ADDI 0 = Rt 1 1 = sign 1 = Imm 0 0 0 = ALU
SLTI 0 = Rt 1 1 = sign 1 = Imm 0 0 0 = ALU
ANDI 0 = Rt 1 0 = zero 1 = Imm 0 0 0 = ALU
ORI 0 = Rt 1 0 = zero 1 = Imm 0 0 0 = ALU
XORI 0 = Rt 1 0 = zero 1 = Imm 0 0 0 = ALU
LW 0 = Rt 1 1 = sign 1 = Imm 1 0 1 = Mem
SW X 0 1 = sign 1 = Imm 0 1 X
BEQ X 0 1 = sign 0 = BusB 0 0 X
BNE X 0 1 = sign 0 = BusB 0 0 X
J X 0 X X 0 0 X

X is a don’t care (can be 0 or 1), used to minimize logic

Single Cycle Processor Design COE 233 – Logic Design and Computer Organization © Muhamed Mudawar – slide 35
 Logic Equations for Main Control Signals
Op6
RegDst = R-type

RegWrite = (SW + BEQ + BNE + Decoder

J)

R-type

XORI
ADDI

ANDI

BEQ
BNE
SLTI

ORI

SW
LW

J
ExtOp = (ANDI + ORI + XORI)

ALUSrc = (R-type + BEQ + Logic Equations

BNE)

MemRd = LW

WBdata
MemRd

MemWr
ALUSrc
RegDst

RegWr
ExtOp
MemWr = SW

WBdata = LW
Single Cycle Processor Design COE 233 – Logic Design and Computer Organization © Muhamed Mudawar – slide 36
 ALU Control Truth Table
Op funct ALUOp 4-bit Code
The 4-bit codes
R-type AND AND 11 00 define the binary
R-type OR OR 11 01 ALU operations.
R-type XOR XOR 11 10
R-type ADD ADD 10 00 The 4-bit codes
R-type SUB SUB 10 10 match the ALU
R-type SLT SLT 01 10 implementation.
ADDI X ADD 10 00
SLTI X SLT 01 10 Upper 2 bits =
ANDI X AND 11 00 ALU selection
ORI X OR 11 01 Lower 2 bits =
XORI X XOR 11 10 Logic or Arith op.
LW X ADD 10 00
SW X ADD 10 00 The 4-bit codes can
be derived easily
BEQ X SUB 10 10 from the opcode and
BNE X SUB 10 10 function code.
J X X X
Single Cycle Processor Design COE 233 – Logic Design and Computer Organization © Muhamed Mudawar – slide 37
 Multifunction ALU
2
Shift/Rotate

SLL = 00 SLT: ALU does a SUB

Operation

SRL = 00 Shift Amount 5

then check the sign
SRA = 01 and overflow
Shifter
ROR = 11
32

c0 0
A 32 ALU Result
sign
A SLT 1 32
d
d 2
B 32
Arithmetic
Operation

32 e
r 3
ADD = 0
SUB = 1 2
overflow zero

0 ALU
Selection
1
Logic Unit Shift = 00
2 SLT = 01
AND = 00 Arith = 10
Operation

3
Logical

OR = 01 Logic = 11
XOR = 10 2
NOR = 11

Single Cycle Processor Design COE 233 – Logic Design and Computer Organization © Muhamed Mudawar – slide 38
 PC Control Truth Table

Op Zero flag PCSrc

R-type X 0 = Increment PC

J X 1 = Jump Target Address

BEQ 0 0 = Increment PC

BEQ 1 2 = Branch Target Address

BNE 0 2 = Branch Target Address

BNE 1 0 = Increment PC

Other than Jump or Branch X 0 = Increment PC

The ALU Zero flag is used by BEQ and BNE instructions

Single Cycle Processor Design COE 233 – Logic Design and Computer Organization © Muhamed Mudawar – slide 39
 PC Control Logic
 The PC control logic can be described as follows:
if (Op == J) PCSrc = 1;
else if ((Op == BEQ && Zero == 1) ||
(Op == BNE && Zero == 0)) PCSrc = 2;
else PCSrc = 0; Op

Decoder
Branch = (BEQ . Zero) + (BNE . Zero) BEQ BNE J
Zero
Branch = 1, Jump = 0  PCSrc = 2
Branch = 0, Jump = 1  PCSrc = 1
Branch = 0, Jump = 0  PCSrc = 0

Branch Jump
Single Cycle Processor Design COE 233 – Logic Design and Computer Organization © Muhamed Mudawar – slide 40
 Summary
 5 steps to design a processor
 Analyze instruction set => datapath requirements

 Select datapath components & establish clocking methodology

 Assemble datapath meeting the requirements

 Analyze implementation of each instruction to determine control signals

 Assemble the control logic

 MIPS makes Control easier

 Instructions are of the same size

 Source registers always in the same place

 Immediate constants are of same size and same location

 Operations are always on registers/immediates

Single Cycle Processor Design COE 233 – Logic Design and Computer Organization © Muhamed Mudawar – slide 41