We learned about combinational circuit and their working.

The
combinational circuits have set of outputs, which depends only
on the present combination of inputs. Below is the block
diagram of the synchronous logic circuit.
The sequential circuit is a special type
of circuit that has a series of inputs
and outputs. The outputs of the
sequential circuits depend on both the
combination of present inputs and
previous outputs. The previous output
is treated as the present state. So, the
sequential circuit contains the
combinational circuit and its memory
storage elements. A sequential circuit
doesn't need to always contain a
combinational circuit. So, the
sequential circuit can contain only the
As shownelement.
memory in the figure, there are two types of input to the combinational
logic :
1.External inputs which are not controlled by the circuit.
2.Internal inputs, which are a function of a previous output state.
Secondary inputs are state variables produced by the storage elements,
 Types Of Sequential Circuits

1) Asynchronous sequential
circuits
2) Synchronoussequential
Asynchronous sequentialcircuits
circuits
The clock signals are not used by the Asynchronous sequential
circuits. The asynchronous circuit is operated through the pulses. So,
the changes in the input can change the state of the circuit. The
asynchronous circuits do not use clock pulses. The internal state is
changed when the input variable is changed. The un-clocked flip-flops
or time-delayed are the memory elements of asynchronous sequential
circuits. The asynchronous sequential circuit is similar to the
combinational circuits with feedback.
Synchronous sequential circuits

In synchronous sequential circuits, synchronization of the memory

element's state is done by the clock signal. The output is stored in
either flip-flops or latches(memory devices). The synchronization of the
outputs is done with either only negative edges of the clock signal or
only positive edges.
 Combinational Circuits Sequential Circuits

1) The outputs of the combinational The outputs of the sequential circuits

circuit depend only on the present depend on both present inputs and present
inputs. state(previous output).
2) The feedback path is not present in The feedback path is present in the
the combinational circuit. sequential circuits.
3) In combinational circuits, memory In the sequential circuit, memory
elements are not required. elements play an important role and
require.
4) The clock signal is not required for The clock signal is required for sequential
combinational circuits. circuits.
5) The combinational circuit is simple It is not simple to design a sequential
to design. circuit.
SR LATCH
 Flip-Flop
A flip-flop is a sequential digital electronic circuit having two
stable states that can be used to store one bit of binary data.
Flip-flops are the fundamental building blocks of all memory
devices.

Types of Flip–Flops
•S-R flip-flop
•J-K flip-flop
•D flip-flop
•T flip-flop

A flip-flop is the basic memory element for storing a bit of information. It is

an edge-triggered device. That is, it reacts to the edge of a pulse. A simple
flip-flop has two stable states (remember, for instance, that a capacitor has
two states: charged and discharged). States are represented by 1 and 0.
A basic flip-flop has two inputs and two outputs, as shown in Figure 1. The two inputs are used to set
or reset the device and are denoted by R and S. The outputs are denoted by Q and ¯¯¯¯QQ¯; they
reflect the state of the flip-flop either 1 or 0. If Q = 1, then ¯¯¯¯QQ¯ = 0, and if Q = 0, then and ¯¯¯¯QQ¯ =
1. Figure 1 illustrates also the truth table for the states of a flip-flop.

A flip-flop acts like a single-pole double throw (SPDT) switch. When activated, it’s output toggles. This
property can be used for many operations performed in digital electronics. The toggle action is
performed through the inputs to a flip-flop.
1. S-R Flip Flop
The SET-RESET flip flop is designed with the help of two NOR gates and
also two NAND gates. These flip flops are also called S-R Latch.
•S-R Flip Flop using NOR Gate
The design of such a flip flop includes two inputs, called the SET [S] and
RESET [R]. There are also two outputs, Q and Q’. The diagram and truth
table is shown below.
S=1, R=0—Q=1, Q’=0
This state is also called the SET state.
S=0, R=1—Q=0, Q’=1
This state is known as the RESET state.
In both the states you can see that the outputs are
just compliments of each other and that the value
of Q follows the value of S.
S=0, R=0—Q & Q’ = Remember
If both the values of S and R are switched to 0,
then the circuit remembers the value of S and R in
their previous state.
S=1, R=1—Q=0, Q’=0 [Invalid]
•S-R Flip Flop using NAND Gate
The circuit of the S-R flip flop using NAND Gate and its truth table is shown
below.
Like the NOR Gate S-R flip flop, this one also
has four states. They are
S=1, R=0—Q=0, Q’=1
This state is also called the SET state.
S=0, R=1—Q=1, Q’=0
This state is known as the RESET state.
In both the states you can see that the outputs
are just compliments of each other and that
the value of Q follows the compliment value of
S.
S=0, R=0—Q=1, & Q’ =1 [Invalid]
If both the values of S and R are switched to 0
it is an invalid state because the values of both
Q and Q’ are 1. They are supposed to be
compliments of each other. Normally, this state
must be avoided.
S=1, R=1—Q & Q’= Remember
If both the values of S and R are switched to 1,
then the circuit remembers the value of S and
R in their previous state.
•Clocked S-R Flip Flop
It is also called a Gated S-R flip flop.
The problems with S-R flip flops using NOR and NAND
gate is the invalid state. This problem can be overcome
by using a bistable SR flip-flop that can change outputs
when certain invalid states are met, regardless of the
condition of either the Set or the Reset inputs. For this,
a clocked S-R flip flop is designed by adding two AND
gates to a basic NOR Gate flip flop. The circuit diagram
and truth table is shown below.

A clock pulse [CP] is given to the inputs of the AND

Gate. When the value of the clock pulse is ‘0’, the
outputs of both the AND Gates remain ‘0’. As soon as a
pulse is given the value of CP turns ‘1’. This makes the
values at S and R to pass through the NOR Gate flip
flop. But when the values of both S and R values turn
‘1’, the HIGH value of CP causes both of them to turn
to ‘0’ for a short moment. As soon as the pulse is
removed, the flip flop state becomes intermediate.
Thus either of the two states may be caused, and it
depends on whether the set or reset input of the flip-
flop remains a ‘1’ longer than the transition to ‘0’ at
the end of the pulse. Thus the invalid states can be
2. D Flip Flop
The circuit diagram and truth table is
given below.

D flip flop is actually a slight

modification of the above explained
clocked SR flip-flop. From the figure
you can see that the D input is
connected to the S input and the
complement of the D input is
connected to the R input. The D input
is passed on to the flip flop when the
value of CP is ‘1’. When CP is HIGH,
the flip flop moves to the SET state. If
it is ‘0’, the flip flop switches to the
CLEAR state.
A D (or Delay) Flip Flop is a digital electronic
circuit used to delay the change of state of its
Triggering a flip flop.
The output of a flip flop can be changed by bring a small change in the
input signal. This small change can be brought with the help of a clock
pulse or commonly known as a trigger pulse.

When such a trigger pulse is applied to the input, the output changes
and thus the flip flop is said to be triggered. Flip flops are applicable in
designing counters or registers which stores data in the form of multi-
bit numbers. But such registers need a group of flip flops connected to
each other as sequential circuits. And these sequential circuits require
trigger pulses.

The number of trigger pulses that is applied to the input of the circuit
determines the number in a counter. A single pulse makes the bit move
one position, when it is applied onto a register that stores multi-bit
data.
In the case of SR Flip Flops, the change in signal level decides the type
If a clock pulse is given to the input of the flip flop at the same time when
the output of the flip flop is changing, it may cause instability to the circuit.
The reason for this instability is the feedback that is given from the output
combinational circuit to the memory elements. This problem can be solved
to a certain level by making the flip flop more sensitive to the pulse
transition rather than the pulse duration.
There are mainly four types of pulse-triggering methods. They differ in the
manner
1. High in which
Level the electronic circuits respond to the pulse. They are
Triggering
When a flip flop is required to respond at its HIGH state, a HIGH level
triggering method is used. It is mainly identified from the straight lead
from the clock input. Take a look at the symbolic representation shown
below.
2. Low Level Triggering
When a flip flop is required to respond at its LOW state, a LOW level triggering method is used..
It is mainly identified from the clock input lead along with a low state indicator bubble. Take a
look at the symbolic representation shown below.
3. Positive Edge Triggering
When a flip flop is required to respond at a LOW to HIGH transition state, POSITIVE edge
triggering method is used. It is mainly identified from the clock input lead along with a triangle.
Take a look at the symbolic representation shown below.
4. Negative Edge Triggering
When a flip flop is required to respond during the HIGH to LOW transition
state, a NEGATIVE edge triggering method is used.. It is mainly identified
from the clock input lead along with a low-state indicator and a triangle.
Take a look at the symbolic representation shown below.
Clock Pulse Transition
The movement of a trigger pulse is always from a 0 to 1 and then 1 to 0 of a signal. Thus it takes
two transitions in a single signal. When it moves from 0 to 1 it is called a positive transition and
when it moves from 1 to 0 it is called a negative transition. To understand more take a look at
the images below.
Clock Pulse Transition
The clocked flip-flops already introduced are triggered during the 0 to 1
transition of the pulse, and the state transition starts as soon as the
pulse reaches the HIGH level. If the other inputs change while the clock
is still 1, a new output state may occur. If the flip-flop is made to then
the multiple-transition problem can be eliminated.

The multi-transition problem can be stopped is the flip flop is made to

respond to the positive or negative edge transition only, other than
responding to the entire pulse duration.
A J-K J (Jump) and K (Kill), flip flop can also be defined as a
3. J-K Flip
modification Flop
of the S-R flip flop. The only difference is that
the intermediate state is more refined and precise than
that of a S-R flip flop.
The behavior of inputs J and K is same as the S and R
inputs of the S-R flip flop. The letter J stands for SET and the
letter K stands for CLEAR.
When both the inputs J and K have a HIGH state, the flip-
flop switch to the complement state. So, for a value of Q =
1, it switches to Q=0 and for a value of Q = 0, it switches to
Q=1.
The circuit includes two 3-input AND gates. The output Q of
the flip flop is returned back as a feedback to the input of
the AND along with other inputs like K and clock pulse [CP].
So, if the value of CP is ‘1’, the flip flop gets a CLEAR signal
and with the condition that the value of Q was earlier 1.
Similarly output Q’ of the flip flop is given as a feedback to
the input of the AND along with other inputs like J and clock
pulse [CP]. So the output becomes SET when the value of
CP is 1 only if the value of Q’ was earlier 1.
The output may be repeated in transitions once they have
been complimented for J=K=1 because of the feedback
connection in the JK flip-flop. This can be avoided by setting The circuit diagram and truth-table of
a time duration lesser than the propagation delay through a J-K flip flop is shown below.
the flip-flop. The restriction on the pulse width can be
4. T Flip Flop

This is a much simpler version

of the J-K flip flop. Both the J
and K inputs are connected
together and thus are also
called a single input J-K flip
flop. When clock pulse is
given to the flip flop, the
output begins to toggle. Here
also the restriction on the
pulse width can be eliminated
with a master-slave or edge-
triggered construction. Take a
look at the circuit and truth
table.
 Master-Slave Flip Flop Circuit

Before knowing more about the master-

slave flip flop you have to know more on
the basics of a J-K flip flop and S-R flip
flop. To know more about the flip flops. So
in this, we are learning in detail about
Master Slave Flip Flops. We will see what
are MS flip flops, how they operate, how
to build a master slave flip flop circuit and
many other things in detail.

Master-slave flip flop is designed using

two separate flip flops. Out of these, one
acts as the master and the other as a
slave. The figure of a master-slave J-K flip
flop is shown below.
From the above figure you can see that both the J-K flip flops are
presented in a series connection. The output of the master J-K flip flop is
fed to the input of the slave J-K flip flop. The output of the slave J-K flip
flop is given as a feedback to the input of the master J-K flip flop. The
clock pulse [Clk] is given to the master J-K flip flop and it is sent through
a NOT Gate and thus inverted before passing it to the slave J-K flip flop.

Working

When Clk=1, the master J-K flip flop gets disabled. The Clk input of the
master input will be the opposite of the slave input. So the master flip
flop output will be recognized by the slave flip flop only when the Clk
value becomes 0. Thus, when the clock pulse males a transition from 1
to 0, the locked outputs of the master flip flop are fed through to the
inputs of the slave flip-flop making this flip flop edge or pulse-triggered.
To understand better take a look at the timing diagram illustrated .
Thus, the circuit accepts the value in the input when the clock is HIGH,
and passes the data to the output on the falling-edge of the clock
signal. This makes the Master-Slave J-K flip flop a Synchronous device
as it only passes data with the timing of the clock signal.