Lecture

Lecture 9
9
Combinational
Combinational Automatic
Automatic
Test-Pattern
Test-Pattern Generation
Generation
(ATPG)
(ATPG) Basics
Basics
 Algorithms and representations
 Structural vs. functional test
 Definitions
 Search spaces
 Completeness
 Algebras
 Types of Algorithms
Copyright 2001, Agraw VLSI Test: Lecture 9 1
al & Bushnell
 Origins
Origins of
of Stuck-Faults
Stuck-Faults
 Eldred (1959) – First use of structural
testing for the Honeywell Datamatic
1000 computer
 Galey, Norby, Roth (1961) – First
publication of stuck-at-0 and stuck-at-1
faults
 Seshu & Freeman (1962) – Use of stuck-
faults for parallel fault simulation
 Poage (1963) – Theoretical analysis of
stuck-at faults

Copyright 2001, Agraw VLSI Test: Lecture 9 2

al & Bushnell
 Functional
Functional vs.
vs.
Structural
Structural ATPG
ATPG

Copyright 2001, Agraw VLSI Test: Lecture 9 3

al & Bushnell
 Carry
Carry Circuit
Circuit

Copyright 2001, Agraw VLSI Test: Lecture 9 4

al & Bushnell
Functional
Functional vs.
vs. Structural
Structural
(Continued)
(Continued)
 Functional ATPG – generate complete set of tests for
circuit input-output combinations
 129 inputs, 65 outputs:
 2129 = 680,564,733,841,876,926,926,749,
214,863,536,422,912 patterns
 Using 1 GHz ATE, would take 2.15 x 1022 years
 Structural test:
 No redundant adder hardware, 64 bit slices
 Each with 27 faults (using fault equivalence)
 At most 64 x 27 = 1728 faults (tests)
 Takes 0.000001728 s on 1 GHz ATE
 Designer gives small set of functional tests – augment
with structural tests to boost coverage to 98+ %
Copyright 2001, Agraw VLSI Test: Lecture 9 5
al & Bushnell
 Definition
Definition of
of Automatic
Automatic
Test-Pattern
Test-Pattern Generator
Generator
 Operations on digital hardware:
 Inject fault into circuit modeled in computer
 Use various ways to activate and propagate fault
effect through hardware to circuit output
 Output flips from expected to faulty signal
 Electron-beam (E-beam) test observes internal signals –
“picture” of nodes charged to 0 and 1 in different colors
 Too expensive
 Scan design – add test hardware to all flip-flops to make
them a giant shift register in test mode
 Can shift state in, scan state out
 Widely used – makes sequential test combinational
 Costs: 5 to 20% chip area, circuit delay, extra pin,
longer test sequence
Copyright 2001, Agraw VLSI Test: Lecture 9 6
al & Bushnell
 Circuit
Circuit and
and Binary
Binary
Decision
Decision Tree
Tree

Copyright 2001, Agraw VLSI Test: Lecture 9 7

al & Bushnell
 Binary
Binary Decision
Decision
Diagram
Diagram
 BDD – Follow path from source to sink node –
product of literals along path gives Boolean
value at sink
 Rightmost path: A B C = 1
 Problem: Size varies greatly
with variable order

Copyright 2001, Agraw VLSI Test: Lecture 9 8

al & Bushnell
 Algorithm
Algorithm
Completeness
Completeness
 Definition: Algorithm is complete if it
ultimately can search entire binary
decision tree, as needed, to generate a
test
 Untestable fault – no test for it even
after entire tree searched
 Combinational circuits only – untestable
faults are redundant, showing the
presence of unnecessary hardware

Copyright 2001, Agraw VLSI Test: Lecture 9 9

al & Bushnell
 Valued
Valued and
and Muth’s
Muth’s 9-
9-
Valued
Valued
Good Failing
Symbol Meaning Machine Machine
D 1/0 1 0
D 0/1 0 1 Roth’s
0 0/0 0 0 Algebra
1 1/1 1 1
X X/X X X
G0 0/X 0 X
G1 1/X 1 X Muth’s
F0 X/0 X 0 Additions
F1 X/1 X 1

Copyright 2001, Agraw VLSI Test: Lecture 9 10

al & Bushnell
 Roth’s
Roth’s and
and Muth’s
Muth’s
Higher-Order
Higher-Order Algebras
Algebras
 Represent two machines, which are simulated
simultaneously by a computer program:
 Good circuit machine (1st value)
 Bad circuit machine (2nd value)
 Better to represent both in the algebra:
 Need only 1 pass of ATPG to solve both
 Good machine values that preclude bad machine
values become obvious sooner & vice versa
 Needed for complete ATPG:
 Combinational: Multi-path sensitization, Roth Algebra
 Sequential: Muth Algebra -- good and bad machines
may have different initial values due to fault

Copyright 2001, Agraw VLSI Test: Lecture 9 11

al & Bushnell
 Exhaustive
Exhaustive Algorithm
Algorithm


For n-input circuit, generate all 2n input
patterns
 Infeasible, unless circuit is partitioned

into cones of logic, with 15 inputs
 Perform exhaustive ATPG for each cone
 Misses faults that require specific
activation patterns for multiple cones
to be tested

Copyright 2001, Agraw VLSI Test: Lecture 9 12

al & Bushnell
 Random-Pattern
Random-Pattern
Generation
Generation
 Flow chart
for method
 Use to get
tests for 60-
80% of faults,
then switch
to D-
algorithm or
other ATPG
for rest

Copyright 2001, Agraw VLSI Test: Lecture 9 13

al & Bushnell
Boolean
Boolean Difference
Difference Symbolic
Symbolic
Method
Method (Sellers
(Sellers et
et al.)
al.)

g = G (X1, X2, …, Xn) for the fault site

fj = Fj (g, X1, X2, …, Xn)
1  
j m
Xi = 0 or 1 for 1  
i n

Copyright 2001, Agraw VLSI Test: Lecture 9 14
al & Bushnell
 Boolean
Boolean Difference
Difference
(Sellers,
(Sellers, Hsiao,
Hsiao, Bearnson)
Bearnson)
 Shannon’s Expansion Theorem:
F (X1, X2, …, Xn) = X2 F (X1, 1, …, Xn) + X2 F (X1, 0, …, Xn)
 
 Boolean Difference (partial derivative):

 Fj = Fj (1, X1, X2, …, Xn) Fj (0, X1, …, Xn)

g
 Fault Detection Requirements:
G (X1, X2, …, Xn) = 1
 Fj = Fj (1, X1, X2, …, Xn)  Fj (0, X1, …, Xn) = 1
g
Copyright 2001, Agraw VLSI Test: Lecture 9 15
al & Bushnell
 Path
Path Sensitization
Sensitization
Method
Method Circuit
Circuit Example
Example
1 Fault Sensitization
2 Fault Propagation
3 Line Justification

Copyright 2001, Agraw VLSI Test: Lecture 9 16

al & Bushnell
 Path
Path Sensitization
Sensitization
Method
Method Circuit
Circuit Example
Example
 Try path f – h – k – L blocked at j, since
there is no way to justify the 1 on i

1 D

D D
1 D
D 1 0

Copyright 2001, Agraw VLSI Test: Lecture 9 17

al & Bushnell
 Path
Path Sensitization
Sensitization
Method
Method Circuit
Circuit Example
Example
 Try simultaneous paths f – h – k – L and
g – i – j – k – L blocked at k because
D-frontier (chain of D or D) disappears
1 D
D
1 1
D D D
1

Copyright 2001, Agraw VLSI Test: Lecture 9 18

al & Bushnell
 Path
Path Sensitization
Sensitization
Method
Method Circuit
Circuit Example
Example
 Final try: path g – i – j – k – L – test found!

0
0 D
1 D
D D D
1
1

Copyright 2001, Agraw VLSI Test: Lecture 9 19

al & Bushnell
 Boolean
Boolean Satisfiability
Satisfiability
 2SAT: xi xj + xj xk + xl xm … = 0
.
.
xp xy + xr xs + xt xu … = 0
.

 3SAT: xi xj xk + xj xk xl + xl xm xn … = 0
.
.
xp xy + xr xs x.t + xt xu xv … = 0

Copyright 2001, Agraw VLSI Test: Lecture 9 20

al & Bushnell
 Satisfiability
Satisfiability Example
Example
for
for AND
AND Gate
Gate
  ak bk ck = 0 (non-tautology) or
 (ak + bk + ck) = 1 (satisfiability)

 AND gate signal relationships: Cube:

 If a = 0, then z = 0 az
 If b = 0, then z = 0 bz
 If z = 1, then a = 1 AND b = 1 z ab
 If a = 1 AND b = 1, then z = 1 abz
 Sum to get: a z + b z + a b z = 0
(third relationship is redundant with 1st two)
Copyright 2001, Agraw VLSI Test: Lecture 9 21
al & Bushnell
 Pseudo-Boolean
Pseudo-Boolean and
and
Boolean
Boolean False
False
Functions
Functions
 Pseudo-Boolean function: use ordinary + --
integer arithmetic operators
 Complementation of x represented by 1 – x
 Fpseudo—Bool = 2 z + a b – a z – b z – a b z = 0
 Energy function representation: let any variable
be in the range (0, 1) in pseudo-Boolean
function
 Boolean false expression:
fAND (a, b, z) = z
 (ab) = a z + b z + a b z

Copyright 2001, Agraw VLSI Test: Lecture 9 22

al & Bushnell
AND
AND Gate
Gate Implication
Implication Graph
Graph
 Really efficient
 Each variable has 2 nodes, one for each literal
 If … then clause represented by edge from if
literal to then literal
 Transform into transitive closure graph
 When node true, all reachable states are true
 ANDing operator used for 3SAT relations



Copyright 2001, Agraw VLSI Test: Lecture 9 23

al & Bushnell
Computational
Computational Complexity
Complexity
 Ibarra and Sahni analysis – NP-Complete
(no polynomial expression found for compute
time, presumed to be exponential)
 Worst case:
no_pi inputs, 2 no_pi input combinations
no_ff flip-flops, 4 no_ff initial flip-flop states

(good machine 0 or 1 bad machine 0 or 1)
work to forward or reverse simulate n logic
gates  n
 Complexity: O (n x 2 no_pi x 4 no_ff)

Copyright 2001, Agraw VLSI Test: Lecture 9 24

al & Bushnell
 History
History of
of Algorithm
Algorithm
Speedups
Speedups
Algorithm Est. speedup over D-ALG Year
(normalized to D-ALG time)
D-ALG 1 1966
PODEM 7 1981
FAN 23 1983
TOPS 292 1987
SOCRATES 1574 † ATPG System 1988
Waicukauski et al. 2189 † ATPG System 1990
EST 8765 † ATPG System 1991
TRAN 3005 † ATPG System 1993
Recursive learning 485 1995
Tafertshofer et al. 25057 1997

Copyright 2001, Agraw VLSI Test: Lecture 9 25

al & Bushnell
 Analog
Analog Fault
Fault Modeling
Modeling
Impractical
Impractical for
for Logic
Logic ATPG
ATPG
 Huge # of different possible analog faults
in digital circuit
 Exponential complexity of ATPG
algorithm – a 20 flip-flop circuit can take
days of computing
 Cannot afford to go to a lower-level
model
 Most test-pattern generators for digital
circuits cannot even model at the
transistor switch level (see textbook for 5
examples of switch-level ATPG)

Copyright 2001, Agraw VLSI Test: Lecture 9 26

al & Bushnell