Chapter Contents

Combinational Circuits
Analysis Procedure
Design Procedure
Binary Adder-Subtractor
Decimal Adder
Binary Multiplier
Magnitude Comparator
Decoders
Encoders
Priority Encoder
Multiplexers
Tri-state gates
Combinational Circuits
• Logic circuits for digital system may be combinational
or sequential
– A combinational circuit consists of logic gates whose outputs are a
function of the current inputs
– Sequential circuits
» contain storage elements in addition to logic gates
» the outputs are a function of the current inputs and 1

the state of the memory (storage) elements 7

3
» The state of storage elements, in turn, is a function of
previous inputs so outputs also depend on past inputs
» They have feedback connection
Combinational Circuits
• For n input variables there are 2n possible binary
input combinations
• For each possible input combination there is one
possible output value
• The most important standard MSI combinational
circuits (discussed in this chapter) are adders, sub
tractors, comparators, decoders/ demultiplexers,
encoders, multiplexers, and tri-state gates.
• If the storage registers are included with the
combinational gates then this circuit is considered as
sequential circuit
Analysis Procedure
• The analysis of a combinational circuit requires that
we determine function that the circuit implements
• The first step in analysis procedure is to make sure
that the given circuit is combinational and not
sequential (No feedback path)
• To obtain the output Boolean function from a logic
diagram we proceed as follows
– Label all gate outputs that are a function of input variables with
arbitrary symbols. Determine the Boolean function for each gate
output
– Label the gates that are a function of input variables and previously
labeled gates with other arbitrary symbols. Find the Boolean function
of these gates
– Repeat the above process (step 2) until the outputs of the circuit are
obtained
– By repeated substitution of previously defined functions, obtain the
output Boolean functions in terms of input variables
Analysis Procedure-Example
Analysis Procedure Example
• The circuit has three binary inputs- A, B and C and
two binary outputs- F1 and F2
• The outputs of various gates are labeled with
intermediate symbols
• The output of gates that are a function of input
variables are T1 and T2
• Output F2 can be easily derived from the input
variables
• The Boolean function for these three outputs are:
– F2 = AB + AC + BC
– T1 = A + B + C
– T2 = ABC
• Next we consider output of gates that are a function of
already defined symbols
– T3 = F’2T1
– F1 = T3+T2
Analysis Procedure Example Cont…
• To obtain F1 as a function of A,B and C, from a series
of substitutions proceed as follows
F1 = T3+T2
= F2'T1+ABC
=(AB+AC+BC)'(A+B+C)+ABC
=(A'+B')(A'+C')(B'+C')(A+B+C)+ABC
=(A'+B'C')(AB'+AC'+BC'+B'C)+ABC
=A'BC'+A'B'C+AB'C'+ABC
• These functions F1 and F2 implement circuit of a Full-
Adder (FA). Where:
– F1 is the sum
– F2 is the carry
Derivation of the Truth Table
• The derivation of the truth table for the circuit is a
straight forward process once the output Boolean
functions are known
• To obtain the truth table directly from the logic
diagram without going through the derivations of the
Boolean functions, we proceed as follows:
– Determine the number of input variables in the circuit. For n inputs,
form the 2n possible input combinations and list binary numbers
from 0 to 2n – 1 in a table
– Label the outputs of selected gates with arbitrary symbols
– Obtain the truth table for the outputs of those gates that are a
function of the input variables only
– Proceed to obtain the truth table for the outputs of those gates that
are function of previously defined values until the columns for all
outputs are determined
Truth Table for Figure 4-2
• F2 equal to 1 for any combination that has 2 or 3 inputs equal to 1
• F2' is the complement of F2
• T1 and T2 are the OR and AND functions of input variables respectively
• T3 = 1, when T1 and F2' are equal to 1
• F1 = 1, when either T2 or T3 or both are equal to 1
Design Procedure
• The design procedure of combinational circuits
involves following steps
– State the problem (Circuit specifications)
– From the circuit specifications determine the inputs and outputs for
the circuit design
– The input and output variables are assigned alphabetic symbols
– Derive the truth table that gives the relationship between inputs and
outputs
– Derive the simplified Boolean functions (simplify by algebraic
manipulation or K-map method) for each output variable as a
function of input variables
– Draw the logic diagram and verify the correctness of the design
• The design should be optimized i.e use minimum
gates and lesser propagation delay. This will result in
low cost but fast design.
Code conversion example
• Different digital systems use different types of codes
• It is sometimes necessary to use the output of one
system as the input to another
• A conversion circuit must be inserted between the two
systems if each uses different codes for the same
information
• A code converter is a circuit that makes the two
systems compatible even though each uses a
different binary code
• To convert from binary code A to binary code B, the
input lines (of combinational circuit) must supply the
bit combination of elements as specified by code A
and the output lines must generate the corresponding
bit combination of code B
Code conversion Example: BCD to
Excess-3 Code
• Each code uses four bits to represent a decimal digit,
there must be four input variables and four output
variables
• Designate the four input binary variables by the
symbols A,B,C,D and the four output variables by w,
x, y and z.
• The truth table relating the input and output variable is
made (shown in next slide)
• Four binary variables have 16 bit combinations but
only 10 are listed in the truth table as 6 bit
combinations not listed are don’t care conditions.
These have no meaning in BCD
Code conversion Example :Truth Table
Input Output
BCD Excess-3 Code
A B C D w x y z
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
Map Simplification of Output Functions
• There are four outputs, each as a function of four input
variables.
• There are four maps, each representing one of the
outputs, to obtain simplified Boolean functions.
• The 1’s marked inside the squares are obtained from
the minterms that make the output equal to 1
• The 1’s are obtained from the truth table by going over
the output columns one at a time.
• The 6 don’t care minterms 10 through 15 are marked
with an X or d.
BCD to Excess-3 Code Converter
• The simplified functions
– z = D'
– y = CD +C'D‘
– x = B'C + B'D+BC'D'
– w = A+BC+BD
• A two-level logic diagram may be obtained directly
from the above Boolean expressions but there are
various other possibilities for logic diagram that
implements this circuit
• Another implementation
– z = D'
– y = CD +C’D’ = CD + (C+D)'
– x = B'C + B'D+BC’D’ = B'(C+D) +B(C+D)'
– w = A+BC+BD
BCD-to-Excess Code Converter
• The purpose this manipulation is to use common
gates for two or more outputs
• This is implemented with three levels of gates
• OR gate with output C+D is used to implement
partially each of three outputs
• Implementation with original sum of products require
seven AND gates and three OR gates whereas after
manipulation we require four AND gates and four OR
gates
• In this way the logical circuit has been implemented in
a much economical way.
Binary Adder-Subtractor
• Digital computers perform various arithmetic
operations
• The most basic arithmetic operation is the addition of
two binary digits
• When both augend and addend bits to be added are
equal to 1, the binary sum consists of two digits
(1+1=10). The higher significant bit of this result is
called a carry. This carry is added to the next higher
order pair of significant bits.
• A combinational circuit that performs the addition of
two bits and produces SUM and Carry is called a half
adder (HA).
Half Adder
• Half adder adds two binary bits and produces SUM
and Carry so it requires two inputs and two outputs
– 0+0=0 ; 0+1=1 ; 1+0=1 ; 1+1=10
• The input variables designate the augend and addend
bit, the output variables produce the sum (S) and
carry (C)
• The truth table for half adder is shown. The C output
is 1 only when both inputs are 1. The S output
represents the least significant bit of the sum
x y C S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
Half Adder Output Expressions
• The simplified sum of products expressions are:
– S = x'y+xy'
– C = xy
• It can be implemented in sum of products. It can also
be implemented with an exclusive-OR and an AND
gate
– S=xy
– S = (x+y)(x'+y')
– S' = xy+x'y'
– S' = C+ x'y'
– S = (C+x'y')'
– C = xy
– C = (x'+y')'
Full Adder
• A Full-Adder (FA) is a combinational circuit that forms
the arithmetic sum of three bits (three input bits).
– Two of the input variables x, y represents the two significant bits to
be added
– The third input z represents the carry bit from the previous lower
significant position
– Two output bits are necessary designated by the symbol S for sum
and C for carry
x y z c s
• When all input bits are 0, the 0 0 0 0 0
output is 0 0 0 1 0 1
• The S output is equal to 1 when 0 1 0 0 1
0 1 1 1 0
only one input is equal to 1 or
1 0 0 0 1
when all three inputs are equal 1 0 1 1 0
to 1 1 1 0 1 0
• The C output has a carry of 1 if 1 1 1 1 1
two or three inputs are equal to 1
Simplified Output Expressions for Full
Adder
• The simplified expressions for full adder are
– S = x' y' z + x' y z' + x y' z' + x y z
– C = xy + xz + yz
Full Adder with Two Half Adders
• Full adder can also be implemented with two half adders and
an OR gate. The S output from the second half adder is the
exclusive-OR of z and the output of the first half adder giving
– S = z  (x y)
= z'(xy'+x'y)+z(xy'+x'y)'
=z'(xy'+x'y)+z(xy+x'y')
= xy'z'+x'yz'+xyz+x'y'z
– C = z(xy'+x'y)+xy
= xy'z+x'yz+ xy

Half adder
Binary Adder
• A binary adder is a digital circuit that produces the
arithmetic sum of two binary numbers.
• A binary adder can be implemented using multiple full
adders (FA) connected in cascade with the output
carry from each full adder to the input carry of the
next full adder in the chain
Binary Adder
• The augend bits of A and the addend bits of B are
designated by subscript numbers from right to left,
with subscript 0 denoting the least significant bit
• The carries are connected in a chain through the full
adders
• The S outputs generate the required sum bits
Binary Adder
• Consider the two binary numbers, A= 1011 and B= 0011
• Their sum S= 1110 is formed with four-bit adders
• The bits are added with full adders, starting from the
least significant position (subscript 0), to form the sum
bit and carry bit
• The input carry C0 in the least significant position must
be 0
• The value of Ci+1 in a significant position is the output
carry of the full adder Subscript i 3 2 1 0

• This value is transferred into the Input carry 0 1 1 0 C i

Augend 1 0 1 1 A
input carry of the full adder that Addend i

0 0 1 1 B
i

adds the bits one higher significant Sum 1 1 1 0 S

i

Output carry 0 0 1 1 C
position to the left i+1
Binary Adder
• The sum bits are thus generated starting from the
rightmost position and are available as soon as the
corresponding previous carry bit is generated
• All the carries must be generated for the correct sum
bits to appear at the outputs
Subscript i 3 2 1 0
Input carry 0 1 1 0 Ci
Augend 1 0 1 1 Ai
Addend 0 0 1 1 Bi
Sum 1 1 1 0 Si
Output carry 0 0 1 1 Ci+1
Carry Propagation
• The addition of two binary numbers in parallel implies
that all the bits of the augend and addend are
available for computation at the same time
• In any combinational circuit, the signal must
propagate through the gates before the correct output
is available in the output terminals.
• The Total propagation time = propagation delay of a
typical gate X the number of gate levels
• The longest propagation delay time in a binary adder
is the time it takes the carry to propagate through the
full adders.
• This is because each bit of the sum output depends
on the value of the input carry. This makes the binary
adder very slow.
Carry Propagation
• Since each bit of the sum output depends on the value
of input carry, the value of Si in any given stage in the
adder will be in its steady state final value only after
the input carry to the stage has been propagated
• Consider output S3 in Figure 4-9. Inputs A3 and B3 are
available as soon as input signals are applied to the
adder, however input carry C3 doesn’t settle to its final
value until C2 is available from the previous stage
• Similarly C2 has to wait for C1 and so on down to C0
• In this way only after the carry propagates and ripples
through all stages will the last output S3 and carry C4
settle to their final correct value
Carry Propagation
• The number of gate levels for the carry propagation
can be found from the circuit of the full adder
• The input and output variables use the subscript i to
denote a typical stage in the adder
• The signals at Pi and Gi settle to their steady state
values after they propagate through their respective
gates
Carry Propagation
• These two signals are common to all full adders and
depend only on the augend and addend bits
• The signal from the input carry Ci to the output carry
Ci+1 propagates through an AND gate and an OR gate,
which constitutes two gate levels
• If there are four full adders in the adder, the output
carry C4 would have 2 x 4 = 8 gate levels from C0 to C4.
• For an n-bit adder, there are 2n gate levels for the
carry to propagate from input to output
• The outputs of a combinational circuit will not be
correct unless the signals are given enough time to
propagate through the gates connected from inputs to
outputs
• All other arithmetic operations are implemented by
successive additions, the time consumed during the
addition process is very critical.
Carry Propagation
• One choice to reduce the carry propagation delay is to
employ faster gates but the most widely used
technique for reducing the carry propagation time in
parallel adder is principle of carry lookahead
• Consider the circuit of full adder shown in fig 4-10
• If we define two binary variables
– carry propagate: Pi = AiBi (Term associated with the propagation of
carry from Ci to Ci+1)
– carry generate: Gi = AiBi (Produces 1 when both Ai and Bi are 1)
• Output sum and carry can be expressed as
– sum: Si = PiCi
– carry: Ci+1 = Gi+PiCi
Carry Propagation
• We now write the Boolean functions for the carry
outputs of each stage and substitute for each Ci, its
value from the previous equation
– Co= input carry
– C1 = G0+P0C0
– C2 = G1+P1C1
– = G1+P1(G0+P0C0)
– = G1+P1G0+P1P0C0
– C3 = G2+P2C2
– = G2+P2G1+P2P1G0+ P2P1P0C0
– C4 = G3+P3C3
– =G3+P3G2+P3P2G1+P3P2P1G0+P3P2P1P0C0
• Since the Boolean function for each output carry is
expressed in sum of products, each function can be
implemented with one level of AND gates followed by
an OR gate (or by two-level NAND )
Carry Look ahead Generator
• The four Boolean functions for C1, C2, C3 ,and C4 are
implemented in the carry look ahead generator shown
in Figure 4-11
• Here C4 doesn’t have to wait for C3, C2 and C1 to
propagate and C4 is propagated at the same time as
C1, C2, and C3.
Carry Look ahead Generator

Fig 4-11 Logic Diagram of Carry Look ahead

Generator
4-Bit Adder with Carry Look ahead
• The construction of 4-bit adder with a carry lookahead
generator is shown in Figure 4-12
• Each sum output requires two exclusive-OR gates.
• The output of first exclusive-OR gate generates the Pi
variable and the AND gate generates the Gi variable
• The carries are propagated through the carry look
ahead generator and applied as inputs to the second
exclusive-OR gate
• All outputs carries are generated after a delay through
two levels of gates
• Outputs S1 through S3 have equal propagation delay
times
4-Bit Adder with Carry Look ahead
Binary Subtractor
• The subtraction of unsigned binary numbers can
be easily done by means of complements.(section
1-5)
• A-B = A+(2’s complement of B)
• The 2’s complement can be obtained by taking
the 1’s complement and adding 1 to least
significant pair of bits
• To obtain 2’s complement, the 1’s complement
can be implemented with inverters and one can be
added to the sum through the input carry
Binary Subtractor
• The circuit for subtracting A – B consists of an adder
with inverters placed between each data input B and
the corresponding input of full adder
• The input carry C0 must be equal to 1 when
performing subtraction
• The operation thus performed becomes A, plus the
1’s complement of B, plus 1 (A+1’s complement of
B+1). This is equal to A plus 2’s complement of B
(A+2’s complement of B)
• For unsigned numbers this gives A – B if A B or the
2’s complement of (B – A) if A<B
Binary Subtractor
• The addition and subtraction operation can be
combined into one circuit with one common binary
adder
• This is done by including an exclusive-OR gate with
each full adder
• The mode input M controls the operation. When M=0,
we have B0= B. The full adder receives the value of
B, the input carry is 0 and the circuit performs A+B
• When M=1, we have B1= B’. The full adder receives
the value of B’, the input carry C0 is 1 and the circuit
performs A plus the 2’s complement of B. (A+1’s
complement of B+1).
• The exclusive-OR with output V is for detecting an
overflow (detail later, in overflow)
Overflow
• When two numbers of n digits are added and sum
occupies n+1 digits we say that an overflow occurred
• Overflow is problem in digital computers because the
number of bits that hold the number (limited storage)
is finite and a result that contains n+1 can’t be
accommodated.
• The detection of an overflow after the addition of two
binary numbers depends on whether the numbers are
considered to be signed or unsigned
• When two unsigned numbers are added an overflow is
detected from the end carry out of the most significant
position
• In the case of signed numbers, the leftmost bit always
represent the sign and negative numbers are in 2’s
complement form
Overflow
• When two signed numbers are added, the sign bit is
treated as part of the number and end carry doesn’t
indicate an overflow
• An overflow can’t occur after an addition if one
number is positive and the other is negative, since
adding a positive number to a negative number
produces a result which is smaller than the larger of
the two original numbers.
• An overflow may occur if the two numbers added are
both positive or both negative
• For n-bit registers, the range of numbers (signed
numbers) that each register can accommodate is from
binary 2n-1-1 to binary –2n-1.
Overflow
• For 8-bit registers, the range of numbers that each
register can accommodate is from binary +127 to binary
–128
• Consider two signed numbers +70 and +80 stored in two
8-bit registers. The sum of two numbers is +150 which
exceeds the capacity of eight bit register

Note: Negative numbers are in 2’s complement form

Overflow
• If we just consider the 8-bit result from the last
example, we go wrong as we
– Add two positive numbers and obtain a negative number
– Add two negative numbers and obtain a positive number
• The carry out of sign bit position is taken as the sign
bit of the result, then the 9-bit answer so obtained will
be correct. This answer can’t be accommodated
within 8-bits we say that an overflow has occurred
• An overflow has occurred if carry into the sign bit
position and carry out of the sign bit position are not
equal. This can be found by applying the two carries
to an exclusive-OR gate. 1 at the output of the gate
indicates overflow
– V=0, no overflow; V=1, overflow
Decimal Adder
• Computers or calculators that perform arithmetic
operations directly in the decimal number system
represent decimal number in binary coded form
(BCD).
• An adder for such a computer must employ arithmetic
circuits that accept binary coded decimal numbers
and present results in the same code
• To add two BCD digits, we require
– 9 inputs: eight inputs for two BCDs and one carry-in. Since four bits
are required to code each decimal digit
– 5 outputs: four outputs for one BCD and one carry-out
BCD Adder
• To design a BCD adder we require a truth table with 2^9
entries (since 9 inputs). This may become too difficult to
work with so we device some easy alternative to design
a BCD adder. This is shown in table 4-5
• Each digit doesn’t exceed 9 and so the output sum can’t
exceed, 9+9+1 = 19 (two BCD digits and input carry)
• Suppose we apply two BCD digits to a 4-bit binary adder
• The adder will form the sum in binary and produces a
result that ranges from 0 through 19
• These binary numbers are listed in table 4-5 and are
labeled by symbols K, Z8, Z4, Z2 and Z1. (K is the output
carry). But the output sum must be represented in BCD
(not binary) and should appear in the form listed in the
columns C, S8, S4, S2 and S1 under BCD sum
• The problem is to find a rule by which binary sum is
converted to corresponding BCD sum
Correction for BCD Adder
• From the table it is apparent that when binary sum is
equal to or less than 1001 (decimal 9), the
corresponding BCD number is identical and therefore
no correction is needed.
• Modifications are needed if the sum is greater than
1001 as we get non-valid BCD representation. The
addition of binary 6 (0110) to binary sum converts it to
the correct BCD representation and also produces an
output carry as required (refer to section 1-7)
• The logic circuit that detects the necessary correction
can be derived from the table entries. Correction
(adding decimal 6 or binary 0110) is needed when the
binary sum has an output
– K=1
– Z8Z4 = 1
– Z8Z2 = 1
Correction for BCD Adder
• This condition for correction and an output carry can
be expressed as
– C = K + Z8Z4 + Z8Z2
• In figure 4-14, the output carry generated from the
bottom adder can be ignored since this is already
available at the output carry terminal
• A decimal parallel adder that adds n decimal digits (in
BCD form) needs n BCD adder stages with output
carry from one stage connected to the input carry of
next higher-order stage
BCD Adder
Numbers that need correction (add 6) are:
01010 (10)
01011 (11)
01100 (12)
01101 (13)
01110 (14)
01111 (15)
10000 (16)
10001 (17)
10010 (18)
10011 (19)

Decides to add 6

Adds 6
BCD Adder
Numbers that need correction (add 6) are:
K Z8 Z4 Z2 Z1
0 1 0 1 0 (10)
0 1 0 1 1 (11)
0 1 1 0 0 (12)
0 1 1 0 1 (13)
0 1 1 1 0 (14)
0 1 1 1 1 (15)
1 0 0 0 0 (16)
1 0 0 0 1 (17)
1 0 0 1 0 (18)
1 0 0 1 1 (19)

C = K + Z8Z4 +Z8Z2
Binary Multiplier
• Multiplication of the binary number is performed in
the same way as in decimal numbers. The
multiplicand is multiplied by each bit of the multiplier
starting from the least significant bit
• Each such such multiplication forms a partial product.
Successive partial products are shifted one position
to the left. The final product is obtained from the sum
of the partial products
• Consider the binary multiplication of 2-bit numbers
where B1 and B2 are multiplicand bits and A1 and A0
are multiplier bits. C3 C2 C1 C0 are the product bits
Binary Multiplier
• The first partial product is formed by multiplying A0
by B1 B0. The multiplication of any two bits produces a
1 if both bits are 1, otherwise it produces a 0. This is
identical to AND operation. Therefore partial product
can be implemented with an AND gates as shown in
figure 4-15
• The second partial product is formed by multiplying
A1 by B1 B0 and shifted one position to the left
• The two partial products are added with two half adder
(HA) circuits. If there are more bits in the partial
products then we use full adders to produce the sum
of the partial products
• The least significant bit of the partial product doesn’t
have to go through an adder since it is formed by the
output of the first AND gate
K-bit by J-bit Binary Multiplier
• A combinational circuit for binary multiplier with
more bits can be constructed in a similar way. A bit
of the multiplier is ANDed with each bit of the
multiplicand in as many levels as there are bits in the
multiplier
• The binary output in each level of AND gate is added
with the partial product of the previous level to form
a new partial product. The last level produces the
product
• For J multiplier bits and K multiplicand bits we need
(J x K) AND gates and (J – 1) K bit adders to produce
a product of J + K bits
4-bit by 3-bit binary multiplier
• Consider a multiplier circuit that multiplies a binary
number of four bits by a number of three bits.
• Let the multiplicand is represented by B3 B2 B1 B0
and the multiplier by A2 A1 A0
• Since K = 4 and J = 3, we need 12 AND gates and
two 4 – bit adders to produce a product of seven
bits
B3 B2 B1 B0 Multiplicand
X A2 A 1 A0 Multiplier

0 A0B3 A0B2 A0B1 A0B0 Partial Product 0

A1B3 A1B2 A1B1 A1B0 Partial Product 1
Cout S3 S 2 S1 S0
A2B3 A2B2 A2B1 A2B0 Partial Product 2

C6 C5 C4 C3 C2 C1 C0 Final Product
Magnitude Comparator
• The comparison of two numbers is an operation that
determines if one number is greater than, less than or
equal to the other number
• A magnitude comparator is a combinational circuit
that compares two numbers, A and B and determines
their relative magnitudes
• The outcome of the comparison is specified by three
binary variables that indicates whether A>B, A=B or
A<B
Magnitude Comparator
• If we follow the traditional design approach of truth
table then comparing two n-bit numbers will have 22n
entries in the truth table and becomes too
complicated for large values of n.
• However, a comparator circuit possess a certain
amount of regularity. Digital functions that possess an
inherent well defined regularity can usually be
designed by means of algorithmic procedure. This
reduce design efforts and reduce human errors
• An algorithm is a procedure that specifies a finite set
of steps, if followed, give the solution to a problem.
The algorithm is direct application of the procedure a
person uses to compare the relative magnitude of two
numbers
Developing Algorithm
• Consider the two numbers A and B, with four digits
each, the coefficients of numbers with descending
significance can be written as:
– A = A3A2A1A0 and B = B3B2B1B0
• The two numbers are equal if all pairs of significant
digits are equal:
– A=B if A3=B3, A2=B2, A1=B1and A0=B0
• For binary (either 1 or 0) digits the equality relation of
each pair of bits can be expressed logically with
exclusive-NOR function to test if Ai = Bi as
– xi = (Ai  Bi)' = (AiBi'+Ai'Bi)' = AiBi+Ai'Bi' for i = 0,1,2,3
– xi = 1 only if the pair of bits in position i are equal otherwise x i = 0
• Therefore we can can check if A = B by
– (A=B) = x3x2x1x0
• The symbol (A=B) is binary output variable that is equal
to 1 only if all pair of digits of the two numbers are equal
Developing Algorithm
• To determine if A>B or A<B, we inspect the relative
magnitudes of pairs of significant digits starting from the
most significant position. If the two digits are equal, we
compare the next lower significant pair of digits. This
comparison continues until a pair of unequal digits is
reached
• If the corresponding digit of A is 1 and that of B is 0, we
conclude that A>B. If the corresponding digit of A is 0
and that of B is 1, we conclude that A<B
• The sequential comparison can be expressed logically by
the two Boolean functions
– (A>B) = A3B3'+x3A2B2'+x3x2A1B1'+x3x2x1 A0B0'
– (A<B) = A3'B3+x3A2'B2+x3x2A1'B1+x3x2x1 A0'B0
• The symbols (A>B) and (A<B) are binary output variables
that are equal to 1when A>B or A<B respectively
Developing Algorithm
• The gate implementation for a magnitude comparator
involves a certain amount of repetition so it is
simpler than it seems.
• The unequal outputs can use the same gates that are
needed to generate the equal output
• The logic diagram of the 4-bit magnitude comparator
is shown in Figure 4 – 17
• The four x outputs are generated with exclusive-NOR
circuits and applied to an AND gate to give the
output binary variable (A=B)
• The other two outputs use the x variable to generate
the Boolean functions
• The procedure for obtaining magnitude comparator
circuits for binary numbers with more than four bits
is obvious from the above steps
 Decides if A3=B3
x3 = (A3B3'+A3'B3)'
=(A3  B3)'

x3A2'B2

= A3'B3+x3A2'B2+x3x2A1'B1+x3x2x1 A0'B0

= A3B3'+x3A2B2'+x3x2A1B1'+x3x2x1 A0B0'
Decoders
• A decoder is a combinational circuit that converts binary
information from n input lines to a maximum of 2n unique
output lines. Only one output can be active (high) at any time.
• Decoders are a class of combinational logic circuits that
convert a set of input variables representing a code into a set
of output variables representing a different code. The
relationship between the input and output codes can be
expressed in a truth table i.e 4-to-10-lines decoder circuit.
• If the n-bit coded information has unused combinations, the
decoder has fewer than 2n outputs
Decoder Applications
• Generate minterms/complement of minterms and are used for
functions implementation.
• Memory addressing- Decoders are widely used in the memory
system of a computer where they respond to the address code
generated by the central processor to activate a particular memory
location.
• Code Conversion. Example is BCD-to-7-segment decoder.
• DeMUX function.
• Used in conjunction with counters to decode (detect) counter
states and provide timing or sequencing signals.
• Provide enabling inputs when used in the design of MUXs with tri-
state gates.
• Computers communicate with peripheral devices (printers,
modems, scanners, keyboards, video monitors, external disk
drives and other computers) by sending and/or receiving data
through I/O ports. Decoders are used to select I/O as determined
by the computer to receive or send data.
Decoder Example (Code Converter)
• BCD-to-seven-segment display converter is one
common example of code converters, which converts
one BCD digit into information suitable for driving a
digit-oriented display.
3-to-8-Line Decoder
• A 3-to-8-Line Decoder is a decoder in which three
inputs are decoded into eight outputs, each
representing one of the minterms of the three
input variables.
• Each one of the eight AND gates generates one
of the minterms.
• A particular application of this decoder is binary-
to-octal conversion, however 3-to-8-line decoder
can be used for decoding any 3-bit code to
provide eight outputs, one for each element of
the code
3-to-8-Line Decoder Truth Table

Inputs Outputs
X Y Z D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
Decoders with NAND gates
• Some decoders are constructed with NAND gates.
Since a NAND gate produces the AND operation with
inverted output, it becomes more economical to
generate the decoder minterms in their complemented
form. Decoder include one or more enable inputs to
control the circuit operation
• A 2-to4-line decoder with an enable input is shown
next. (see Fig).
– The circuit operates with complement outputs and a complement
enable input.
– The decoder is enabled when E is equal to 0 and disabled when E = 1
– The output whose value is equal to 0 represents the minterm selected
by inputs A and B.
– Only one output can be zero at any given time, all other outputs are 1
• Some decoders have two or more enable inputs that
must satisfy a given logic condition
Decoders with NAND gates
Demultiplexer
• A demultiplexer is a circuit that receives information
from a single line and directs it to one of 2n possible
output lines.
• The selection of a specific output is controlled by the
bit combination of n selection lines.
Demultiplexer
• A decoder with an enable input (Figure 4-19) can
function as demultiplexer (1-to-4-line demultiplexer)
– E is taken as data input line and A and B are takes as selection inputs
Constructing large Decoders
• Decoders with enable inputs can be connected
together to form a larger decoder circuit.
– two 3-to-8 decoder can be connected to form a 4-to-16 decoder
– The top decoder outputs generates minterms 0000 to 0111 and
the bottom decoder outputs generate minterms 1000 to 1111.

Generates from
0000 to 0111

Generates from
1000 to 1111
Encoders
• An encoder is a digital circuit that performs the
inverse operation of a decoder.
• An encoder has 2n (or fewer) input lines and n output
lines.
• The output lines generate the binary code
corresponding to the input value
Encoder Design Example
• An example of encoder is octal-to-binary encoder
• It has eight inputs (one for each octal digits) and three
outputs that generate the corresponding binary
number
• It is assumed that only one input has a value of 1 at
any given time
• The encoder can be implemented with OR gates
whose inputs are determined directly from the truth
table
• Output z is equal to 1 when the input octal digit is
1,3,5 or 7. Output y is 1 for octal digits 2,3,6 or 7 and
output x is 1 for digits 4,5,6 or 7. These conditions can
be expressed as by the Boolean functions as shown
in the next slide.
Truth Table: Octal to Binary Encoder

Outputs Inputs
X Y Z D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1

z=D1+D3+D5+D7 y=D2+D3+D6+D7 x=D4+D5+D6+D7

Octal-to-Binary Encoder
Implementation

z=D1+D3+D5+D7 y=D2+D3+D6+D7 x=D4+D5+D6+D7

Previous Encoder Limitations
• The encoder defined in the last slide has the
limitation that only one input can be active at any
given time. If two inputs are active simultaneously,
the output produces an undefined combination.
• For example
– If input D3 and D6 are 1 simultaneously the output of the encoder will
be 111 (see truth table and Boolean function for outputs). Since
z=D1+D3+D5+D7 y=D2+D3+D6+D7 x=D4+D5+D6+D7
– This 111 doesn’t represent either binary 3 or binary 6
• To resolve this ambiguity, encoder circuit must
establish an input priority to ensure that only one
input is encoded.
• Another ambiguity is that when all inputs are zero,
output with all zeros is generated. This is same as
when D0 is equal to 1. This discrepancy can be
resolved by providing an output to indicate that at
least one input is equal to 1
Priority Encoder
• A priority encoder is an encoder circuit that includes
the priority function.
• The operation of the priority encoder is such that if
two or more inputs are equal to 1 at the same time,
the input having the highest priority will take
precedence
– D3 has the highest priority
– D0 has the lowest priority
• Valid bit indicator (V) is set to 1 when one or more
inputs are equal to 1. If all inputs are 0, there is no
valid inputs and V is equal to 0. The other two
outputs are not inspected when V equals 0 and are
specified as don’t care conditions
Priority Encoder: Truth Table
Input Output
D0 D1 D2 D3 X y V

0 0 0 0 x x 0

1 0 0 0 0 0 1

x 1 0 0 0 1 1

x x 1 0 1 0 1

x x x 1 1 1 1

x: don't-care conditions in the output, used in the inputs to

condense truth table, replaced by both 0 and then 1
V: valid output indication, implemented by OR function
Priority Encoder: Expanded Truth
Table
Decoders and Encoders
Multiplexers
• A multiplexer is a combinational circuit that selects
binary information from one of 2n input lines and
directs it to a single line. There are n selection lines.
Applications
• Data Selection and Routing: Select data from one of many
sources and route it to a single destination.
• Parallel-to-Serial Conversion of binary data.
• Operation Sequencing: When used with control
sequencers in physical systems.
• Logic Function Generation: Muxes can be used to
implement the logic functions directly from the truth
tables without the need for simplification.
• Multiple-bit Selection Logic: Used in arithmetic circuits.
• Synchronous data transmission system to serially
transmit four-bit data words from a XMTR to a remote
RCVR. These data are said to time-division-multiplexed
because four different sets of data are appearing on the
same output line at different times.
• Signal routing, data communications, and multiplexed
bus control.
Data Selection
Parallel to Serial Conversion
Functions Implementation using
Multiplexers
Synchronous Data Transmission
2-to-1-line Multiplexer
• 2-to-1-line multiplexer connects one of two 1-bit
sources to a common destination.
• There are two data input lines, one output line and one
selection line s. when s=0 the upper AND gate is
enabled and I0 has path to the output. when s=1 the
lower AND gate is enabled and I1 has path to the
output
4-to-1-line Multiplexer
• 4-to-1-line multiplexer connects one of four 1-bit
sources to a common destination.
• There are four data input lines, one output line and
two selection line s1 and s0. Selection lines s1 and s0
are decoded to select a particular AND gate
• The outputs of the AND gates are applied to a single
OR gate that provides the 1-line output
• When s1s0=10. The AND gate associated with input I2
has two of inputs equal to 1 and the third input I2
connected to output of AND gate. The other three
AND gates have at least one input equal to 0, which
makes their output equal to 0. The OR gate output is
now equal to value of I2, providing a path from the
selected input to the output
Quadruple 2-to-1-Line Multiplexer
• Multiplexer circuits can be combined with common selection
inputs to provide multiple-bit selection logic
• Quadruple 2-to-1-line multiplexer has four multiplexers, each
capable of selecting one of two input lines
• Output Y0 can be selected to come from either input A 0 or B0.
Output Y1 may have the value A1 or B1 and so on
• Input selection line S selects one of the lines in each of the four
multiplexers. The enable input E must be active for normal
operation
• The circuit contains four 2-to-1 line multiplexers and it selects
one of two 4-bit sets of data lines
• The unit is enabled when E=0. Then if s=0, the four A inputs have
a path to the four outputs, if s=1 the four B inputs are applied to
the outputs.
Boolean function implementation
• MUX: A decoder + an OR gate
n
• 2 -to-1 MUX can implement any Boolean function of
n input variables with n selection inputs.
n-1
• We can also use smaller size decoders like 2 -to-1
MUX to implement n variable function. In this case
n-1 will be selection inputs and a single data input.
• Any of the variables can be taken as data and
select inputs and implementation will vary.
• Smaller MUXes can be combined to design a larger
Mux. Under such designs the most significant
select variables should be connected to select
inputs of last MUX in the hierarchy.
• Three-state buffers can also be used to construct
larger MUX.
Function implementation using MUX
An Example: F(A,B,C)=S(1,2,6,7)
Function Implementation using MUX
Procedure: The following steps should be followed to implement
given function:
• assign an ordering sequence of the input variable
• the rightmost variable (D) will be used for the input lines
• assign the remaining n-1 variables to the selection lines w.r.t.
their corresponding sequence
• construct the truth table
• consider a pair of consecutive minterms starting from m0
• determine the input lines

Note: Alternately we can also use implementation Table method to

realize a given function using MUXes of any size.
Multiplexers used in Functions
Implementation
Cascading Multiplexers
Three-state gates
• Logic gates have limited driving capability. A gate output can only
drive a limited number of other gate inputs without degrading
circuit performance. Buffers can be inserted to increase the driving
capability of a gate output.

• Direct connection of two or more gate outputs together is

dangerous. Use of three-state (tri-state) buffers permits such
connections.
Three-state gates
• A three-state gate is a digital circuit that exhibits three
states: 0, 1, and high-impedance (high z state). The high-
impedance state behaves as an open circuit.

• Because of this feature (high z state), a large number of

three-state gate outputs can be connected to form a
common line without endangering loading effects.
• The Figure below shows a three-state gate and its logical
equivalent.
Four Kinds of Tri-State Buffers
Three-state gates Applications
• Data selection/communication over a shared
channel(bus).
• Integrated circuits with bidirectional input/output pins.
• Used in the design of multiplexers.
• Data isolation.
• Output state: 0, 1, and high-impedance(Hi-Z)
Data Selection over a Shared Bus
Integrated circuits with Bi-Directional
Input-Output Pins
Design of Multiplexers using
Three-State Gates
MUX Design using Tri-State gates
End of Chapter4