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Minimum and maximum mode

The document describes the minimum and maximum mode configurations of the 8086 microprocessor. In minimum mode, the 8086 operates as the sole processor with specific control signals generated internally, while in maximum mode, it can connect with additional processors, requiring a bus controller for resource allocation. Key components and their functions, such as clock generators, latches, and transceivers, are detailed for both configurations.

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mohsin shaikh
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11 views

Minimum and maximum mode

The document describes the minimum and maximum mode configurations of the 8086 microprocessor. In minimum mode, the 8086 operates as the sole processor with specific control signals generated internally, while in maximum mode, it can connect with additional processors, requiring a bus controller for resource allocation. Key components and their functions, such as clock generators, latches, and transceivers, are detailed for both configurations.

Uploaded by

mohsin shaikh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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Minimum mode configuration of 8086 microprocessor (Min mode)

• 8086 works in
Minimum Mode, when MN/
MX’ = 1.
• Minimum Mode, 8086
is the only processor in the
system.

The Minimum Mode circuit of


8086 is as shown below:
• Clock is provided by the
8284 clock generator, it
provides CLK, RESET and READY
input to 8086.
•Address from the
address bus is latched into
8282 8-bit latch.
• Three such latches
are needed, as address
bus is 20-bit.
• The ALE of 8086 is
connected to STB of the
latch.
• The ALE for this latch
is given by 8086 itself.
•The data bus is driven
through 8286 8-bit trans-
receiver.
•Two such trans-receivers
are
needed, as the data bus is 16-
bit.
• The trans-receivers
are enabled through the DEN
signal, while the direction of
data is controlled by the
DT/R’ signal.
• DEN’ is connected to
OE’ and DT/R’ is connected to
T. Both DEN’ and DT/R’ are
given by 8086 itself.
•Contr signals for
ol
operations allare generated
by decoding M/IO’ , RD’
and WR’ signals.
• M/IO’ , RD’ and WR’
are decoded by a 3:8
decoder like IC 74138.
• Bus Request (DMA) is
done using the HOLD and
HLDA signals.
• INTA’ is given by
8086, in response to an
interrupt on INTR line.
• At T1 state ALE =1 ,this indicates that
a valid address is latched on
the address bus and also M /
IO’= 1, which indicates
the memory operation is in
progress.
• In T2, the address is removed from
the local bus and is sent to
the addressed device. Then the
bus is tristated.
• When RD’ = 0 , the valid data is
present on the data bus.
• During T2 DEN’ =0, which enables
transceivers and DT/R’ =
0 ,which indicates that the
data is received.
• During T3, data is put on the data
bus and the processor reads it.
• The output device makes the READY
transfer
line process.
high. This When the
means the
processor
output makes has
device the read signal to
performed
1, then
the the output device will again
data
tristate its bus drivers.
• At T1 state ALE =1 ,this indicates that a
valid address is latched on the address
bus and also M / IO’= 1, which
indicates the memory operation is in
progress.
• In T2, the processor sends the data
to be written to the addressed location.
• The data is buffered on the bus until
the middle of T4 state.
• The WR’=0 becomes at the beginning
of T2.
• The BHE’ and A0 signals are used to
select the byte or bytes of memory or
I/O word.
• During T2 DEN’ =0, which
transceivers and DT/R’ = 1 ,which
enables,
indicates that the data is transferred
by the processor to the addressed
device.
Maximum mode configuration of 8086 microprocessor (Max mode)

• In this we can connect more processors to 8086 (8087/8089).


• 8086 max mode is basically for implementation of allocation
of global resources and passing bus control to
other coprocessor(i.e. second processor in the system),
because two processors can not access system bus at
same instant.
• All processors execute their own program.
• The resources which are common to all processors are known
as global resources.
• The resources which are allocated to a particular processor
are known as local or private
resources.
•When MN/ MX’ = 0 ,
8086 works in max mode.
•Clock is provided by
clock
8284generator.
•8288 bus Address
from
controller-
the address bus
latched into 8282 8-bit latch.
is
• Three such latches
are required because
address bus is 20 bit.
• The ALE(Address
latch enable) is
connected to STB(Strobe) of
the latch.
• The ALE for latch is
given by 8288 bus controller.
• The data bus is
operated through 8286 8-bit
transceiver. Two such
transceivers are required,
because data bus is 16-bit.
• The are
transceivers
theenabled
DEN signal, while
the direction of data is
controlled by the DT/R signal.
DEN is connected
to OE’ and DT/ R’ is connected
to T. Both DEN and DT/ R’ are
given by 8288 bus controller.
• Control signals for all operations
are generated by decoding S’2, S’1 and S’0
using 8288 bus controller.
• Bus request is done using
RQ’ / GT’ lines interfaced with
8086. RQ0/GT0 has more
priority than RQ1/GT1.
•INTA’ is given by 8288,
in response to an interrupt on
INTR line of 8086.
•In max mode, the
advanced write signals get
enabled one T- state in advance
as compared to normal write
signals. This gives slower
devices more time to get ready
to accept the data,
therefore it reduces the number
of cycles.
• S0,S1,S2 are set at the
beginning of bus cycle.
•On detecting the change
on passive state S0 = S1 = S2 = 1,
the 8288 bus controller will
output a pulse on its ALE and
apply a required signal to its
DT/R pin during T1.
•In T2, 8288 will set DEN =
1 thus enabling transceiver.
•For an input, 8288 it
will activates MRDC or IORC.
•These signals are
activated until T4.
•For an output, the
AMWC or AIOWC is
activated from T2 to T4 and
MWTC or IOWC is activated
from T3 to T4.
•The status bits S0
to S2 remain active until T3,
and become passive during T3
and T4.
•If ready input is
not activated before T3, wait
state will be inserted
between T3 and T4.

Sonal Hutke

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