MODULE II

MODULE II
Boolean Laws and theorems

Sum of Products method, Product of Sum method – K

map representation and simplification (up to four
variables) - Pairs, Quads, Octets, Don’t care conditions.

Combinational Circuits:

Adders - Full adder and half adder, Subtractors - half

subtractor and full subtractor, 4 bit parallel binary
adder/subtractor, Carry Look Ahead Adders.
 BOOLEAN ALGEBRA
• In mathematics, Boolean algebra is the branch
of algebra in which the values of the variables are the
truth values true and false, usually denoted 1 and 0,
respectively.
• Boolean Algebra is used to analyze and simplify the
digital (logic) circuits.
• Uses only the binary numbers i.e. 0 and 1.
• Also called as Logical Algebra.
• Invented by George Boole in 1854.
TERMS
• Variable: The symbol which represent an arbitrary elements
of Boolean Algebra is known as variable.
• Constant: The Value which remains same in Boolean
Algebra is known as constant
• Complement: A complement of a variable is represented by
“bar” over the letter.
• Literal:Each occurrence of a variable in Boolean function
either in a complemented or an uncomplemented form
 BOOLEAN EXPRESSION
• Boolean Expressions are constructed by connecting
Boolean constants ad variables with Boolean operations.
• Boolean expressions are used to describe switching
function or Boolean function.
 HOW TO PROVE TWO BOOLEAN
EXPRESSIONS ARE EQUIVALENT?
• Truth Table: Formulate the truth table of two
expressions. If they are identical, the two expressions
are equal.
• Deduction: Derive one expression into the other by
applying proper axioms and theorems in a proper order.
• Venn Diagram: Draw the Venn Diagrams of two
expressions. If they are identical, the two expressions
are equal.
 PROBLEMS
Q) Prove that the following expressions are same:
A+ (B.C) = (A+B).(A+C)
A B C B.C A+B.C A+B A+C (A+B)
(A+C)
0 0 0 0 0 0 0 0
0 0 1 0 0 0 1 0
0 1 0 0 0 1 0 0
0 1 1 1 1 1 1 1
1 0 0 0 1 1 1 1
1 0 1 0 1 1 1 1
1 1 0 0 1 1 1 1
1 1 1 1 1 1 1 1
POSTULATES, LAWS AND THEOREMS
 DE MORGAN’S THEOREM
• Most important logic theorem for digital electronics
• As per Demorgan’s Theorem, any logical binary expression
remains unchanged if we
1. Change all variables to their complements.
2. Change all AND operations to ORs.
3. Change all OR operations to ANDs.
4. Take the complement of the entire expression.
PROOF
A B A’ B’ A’ + AB (AB)
B’ ’
0 0 1 1 1 0 1
0 1 1 0 1 0 1
1 0 0 1 1 0 1
1 1 0 0 0 1 0

A B A’ B’ A’B’ A+B (A+

B)’
0 0 1 1 1 0 1
0 1 1 0 0 1 0
1 0 0 1 0 1 0
1 1 0 0 0 1 0
Application:
DeMorgan's Theorem is useful in the implementation of
the basic gate operations with alternative gates,
particularly with NAND and NOR gates which are readily
available in IC form.
EXAMPLE
 PRINCIPLE OF DUALITY

• Principle of Duality states that any algebraic equality

derived from Boolean Algebra axioms will still be valid
whenever the OR and AND operators, and identity
elements 0 and 1, have been interchanged. i.e. changing
every OR into AND and vice versa, and every 0 into 1 and
vice versa.
EXAMPLE
 PROBLEMS
Q) Simplify the Boolean Expressions
a) A’BCD’ + BCD’ + BC’D’ + BC’D
b) AB + + AB’C (AB + C)
c) X’ + XY + XZ’ + XY’Z’

Q) Prove the following:

d) (X+Y)(X’Z’ + Z)(Y’ + XZ)’ = X’Y
e) AB+CD =
f) (A+B)(C+D) =
g) ((A+B+C)D)’ = A’B’C’ + D’
h) (AB’(C+BD) + (AB)’)C = A’C + B’C
 IMPLEMENTATION OF A BOOLEAN
EXPRESSION

Using any gate

Using only NAND Gate
Using only NOR Gate
 PROBLEMS
Q) Implement the following expression
a) F = ABC + ABC’ + A’BC’ using any gates, NAND gates
only, NOR gates only
b) F = (A+B+C)(A’+B’+C)(A+B’+C) using any gates,
NAND gates only, NOR gates only
 STANDARD FORMS OF BOOLEAN
EXPRESSION
• All
Boolean expressions regardless of their form can be
converted into either of the two standard forms.
• Sum of Products Form
• Product of Sums Form
• Standardisationmakes the evaluation, simplification and
implementation of Boolean expressions much more
systematic and easier
 SUM OF PRODUCTS
• Sum of products is a Boolean expression one in which
two or more product terms are summed by Boolean
addition
• In
an SOP, a single overbar cannot be extended over
more than one variable.
IMPLEMENTATION OF SOP

AND / OR IMPLEMENTATION
 STANDARD SOP / CANONICAL SOP
• A standard SOP expression is one in which all the variables
in the domain appear in each product term in the expression

• Each individual term in the standard SOP is called MINTERM

(m)
• Symbol used for SOP is Σ
• Standard SOP expressions are important for constructing
truth tables and Karnaugh Map Simplification
 HOW TO CONVERT TO STANDARD SOP

1. Multiply
each non standard product term by a term
made up of the sum of a missing variable and its
complement
2. Repeat step 1 until all resulting product term
contains all the variables in the domain in either
complemented or uncomplemented form
Convert ab’c+a’b’+abc’d into standard SOP form
a b c d Minterms Output
(F)
0 0 0 0 m0 = x
a’b’c’d’ F = m0+m1+m2+m3+m10+m11+m13
0 0 0 1 m1 = x
a’b’c’d F=
0 0 1 0 m2 = x
a’b’cd’
0 0 1 1 m3 = x
a’b’cd
0 1 0 0 m4 =
a’bc’d’
0 1 0 1 m5 =
a’bc’d
0 1 1 0 m6 =
a’bcd’
0 1 1 1 m7 = a’bcd
1 0 0 0 m8 =
ab’c’d’
1 0 0 1 m9 =
ab’c’d
 PRODUCT OF SUMS
• Product of sums is a Boolean expression one in which two or
more product terms are summed by Boolean multiplication
• In POS form a single overbar cannot extend over more than
one variable
IMPLEMENTATION OF POS
OR / AND IMPLEMENTATION
 STANDARD POS / CANONICAL POS
• A standard POS expression is one in which all the variables
in the domain appear in each sum term in the expression

• Each individual term in the standard POS is called

MAXTERM (M)
• Symbol used for POS is Π
• Standard POS expressions are important for constructing
truth tables and Karnaugh Map Simplification
 HOW TO CONVERT TO STANDARD SOP

1. Add to each non standard product term a term made up of

the product of a missing variable and its complement
2. Apply distributive law
3. Repeat step 1 until all resulting sum term contains all the
variables in the domain in either complemented or
uncomplemented form
Convert (a+b’+c)(b’+c+d’)(a+b’+c’+d) into standard POS form
a b c d Maxterms Output
(F)
0 0 0 0 M0 =
a’+b’+c’+d’
F = M2M9M10M11
0 0 0 1 M1 =
a’+b’+c’+d F =(2,9,10,11)
0 0 1 0 M2 = x
a’+b’+c+d’
0 0 1 1 M3 =
a’+b’+c+d
0 1 0 0 M4 =
a’+b+c’+d’
0 1 0 1 M5 =
a’+b+c’+d
0 1 1 0 M6 =
a’+b+c+d’
0 1 1 1 M7 =
a’+b+c+d
1 0 0 0 M8 =
a+b’+c’+d’
1 0 0 1 M9 = x
Convert the following into standard SOP
• Convert the following into standard POS
 SIMPLIFICATION USING BOOLEAN
ALGEBRA
• A simplified Boolean expression uses fewest possible
gates to implement a given expression
Example
 KARNAUGH MAP MINIMISATION
• Simplifying the Boolean functions using Boolean postulates
and theorems is a time consuming process

• To overcome this difficulty, Karnaugh map

method or K-map method can be used
• Graphical method, which consists of 2n cells
for ‘n’ variables.
• Adjacent cells are differed only in single bit
position.
 STEPS FOR MINIMISATION USING K-MAP
1. Select K-map according to the number of variables.
2. Identify minterms or maxterms as given in problem.
3. For SOP put 1’s in blocks of K-map respective to the
minterms (0’s elsewhere). For POS put 0’s in blocks of K-
map respective to the maxterms(1’s elsewhere).
4. Make rectangular groups containing total terms in power of
two like 2,4,8 ..(except 1) and try to cover as many
elements as you can in one group.
5. From the groups made in step 5 find the product terms and
sum them up for SOP form.
 RULES OF SIMPLIFICATION
K map uses the following rules for the simplification of expressions
by grouping together adjacent cells containing ones
In short,
1. No zeros allowed.
2. No diagonals.
3. Only power of 2 number of cells in each group.
4. Groups should be as large as possible.
5. Every one must be in at least one group.
6. Overlapping allowed.
7. Wrap around allowed.
8. Fewest number of groups possible.
EXAMPLE PROBLEM SOP
EXAMPLE PROBLEM POS
Don’t Care Condition
• “Don’t Care” conditions allow us to replace the empty cell
of a K-Map to form a grouping of the variables which is
larger than that of forming groups without don’t cares.
• Whileforming groups of cells, we can consider a “Don’t
Care” cell as 1 or 0 or we can also ignore that cell.
• Therefore,“Don’t Care” condition can help us to form a
larger group of cells.
•ADon’t Care cell can be represented by a cross(X) in K-
Maps representing a invalid combination.
EXAMPLE SOP WITH DON’T CARE
EXAMPLE POS WITH DON’T CARE
Q) Reduce the following to its minimum SOP
Y=
Q) Minimise the following expression in POS form
Y = (++C+D) (+++D) (+++) (+B+C+D) (A+++D) (A+++)
(A+B+C+D) (++C+)
Q) Reduce the following function using K-map technique
f(A,B,C,D) =
Q) Obtain the minimal POS for
F = d (8,10,11,15)
 LOGIC CIRCUITS
Circuits that operates on a definite set of logic rules is known
as Logic Circuits.
Has voltage levels to be switched from one value to another
but has a finite number of distinct values (generally 0 for
false and 1 for true).
Basic circuits which are used in mobile phones, calculators,
computers, etc.
2 types of digital circuits depends on their output and
memory used:
1. Combinational Circuits
 COMBINATIONAL CIRCUITS
• Output of combinational circuit at any instant of time,
depends only on the levels present at input terminals.
• Does not use any memory.
• Previous state of input does not have any effect on the
present state of the circuit.
• Combinational circuit can have an n number of inputs and
m number of outputs.
 SEQUENTIAL CIRCUITS
• A sequential circuit is specified by a time sequence of inputs,
outputs, and internal states.
• Output of a sequential circuit depends not only the combination
of present inputs but also on the previous outputs.
• Include memory elements with combinational circuits.
• Memory elements are circuits capable of storing binary
information.
• Binary information stored in these memory elements at any
given time defines the state of the sequential circuit at that
time.
• Externaloutput of a sequential circuit depends both on the
present input and previous output state.
• Nextstate of the memory elements also depends on the
external input and present state of external output.
• Some sequential circuits may not contain combinational
circuits, but only memory elements.
 COMBINATIONAL CIRCUITS SEQUENTIAL CIRCUITS
Output variables are all time Output variables depend not only on
dependent on the combination of input the present variables but also
variables depend on the past history of these
input variables
Memory circuits not required Memory circuit is required to store
the past history of input variables
Faster in speed because delay Slower than combinational circuits
between input and output is due to
propagation delay of gates
Easy to design Harder to design
Building block Logic Gates Building block Flip Flops
Used for arithmetic and Boolean Used for storing data
operations
No feedback Feedback is required
 HALF ADDER
Half adder is a combinational logic circuit with two inputs
and two outputs.
Designed to add two single bit binary number A and B.
Two outputs carry and sum.
 FULL ADDER

Can add two one-bit

numbers A and B, and
carry c.
Three input and two
output combinational
circuit.
Overcomes the drawback
of Half Adder circuit.
Full adder is implemented using two Half adders and one
OR gate. If C in is zero, then the full adder becomes Half-
adder.

AB
 N-BIT PARALLEL ADDER

• Full
Adder is capable of adding only two single digit binary
number along with a carry input.
• Toadd two n-bit binary numbers we need to use the n-bit
parallel adder.
• Uses a number of full adders in cascade.
• Carry output of the previous full adder is connected to carry
input of the next full adder.
 4 BIT PARALLEL ADDER
• 4 bit parallel adder is a very common logic circuit.
• In the block diagram, A0 and B0 represent the LSB of the four bit words A and
B. Hence Full Adder-0 is the lowest stage. Hence its Cin has been
permanently made 0.
• Rest of the connections are exactly same as those of n-bit parallel adder is
shown in fig.
 HALF SUBTRACTOR
• Half subtractor is a combination circuit with two inputs and two outputs
(difference and borrow).
• Produces the difference between the two binary bits at the input and also
produces an output (Borrow) to indicate if a 1 has been borrowed.
• In the subtraction (A-B), A is called as Minuend bit and B is called as
Subtrahend bit.
 FULL SUBTRACTOR
• Disadvantage of a half subtractor is overcome by full subtractor.
• Full subtractor is a combinational circuit with three inputs A, B,
Bin and two output D and Bout.

• A is the 'minuend', B is 'subtrahend', B in is the 'borrow'

produced by the previous stage, D is the difference output and
Bout is the borrow output.
• Full Subtractor can be implemented with half subtractors with
OR gate as shown in figure below.
 N-BIT PARALLEL SUBTRACTOR
• Subtraction can be carried out by taking the 1's or 2's complement of the
number to be subtracted.
• For example we can perform the subtraction (A-B) by adding either 1's or
2's complement of B to A.
• Use a binary adder to perform the binary subtraction.
 4 BIT PARALLEL SUBTRACTOR
• Parallel binary subtractor is formed by combination of all full adders with
subtrahend complement input.
• Firstly the 1’s complement of B is obtained by the NOT gate
• To add 1 at LSB, one can make use of the first adder in the sequence of
n full adders used in the circuit just by providing logic high at its carry
in (Ci1) and thereby find out 2’s complement of B.

• This is further added to A to carry out the arithmetic subtraction.

• Process continues till the last full adder uses the carry bit C3 to add with
its input A3 and 2’s complement of B3 to generate the last bit of the
output along last carry bit Cout.
• S3 S2 S1 S0 represents the result of binary subtraction (A-B)
and carry output Cout represents the polarity of the result.
 PARALLEL BINARY ADDER / SUBTRACTOR

• Addition and subtraction can be combined into one

circuit with one common binary adder
• Also known as Ripple Carry Adder
• Done by adding an XOR with each full adder
• Mode M controls the operation of the circuit
• Each XOR gets input M and one of the inputs B
ADDER
• When M=0, B + 0 = B, the circuit is adder
• It receives B and input carry 0 and circuit performs
SUBTRACTOR
• When M=1, B + 1= B, the circuit is subtractor
• It receives B and input carry is 1, circuit performs A +
2’s complement of B , A-B
• Carry output of each full adder stage is connected to the
carry input of next higher order stage.
• Sum and Carry Outputs of any stage cannot be produced
until input carry occurs, this leads to time delay know as
“Carry Propagation Delay”
• Eliminated using Carry Look Ahead Adder
Example of Carry Propagation Delay
0101
+0011
1000

• Addition of LSB produces a carry into second position

• This carry when added to the bits of second position
produces a carry into third position
• Sum bit generated in the last position depends on the carry
that was generated by addition in the previous positions
• Adder will not produce correct result until LSB carry has
propagated through the intermediate full adders
• Therefore there is a time delay that depends on the
propagation delay produced in each full adder
• Ifeach full adder has a delay of 30ns, total time required
for 4-bit addition is 120ns
 CARRY LOOK AHEAD ADDER / FAST
ADDER
• CarryLook Ahead Adder is made of a number of full
adders cascaded together.
• Used to add together two binary numbers using only
simple logic gates
• Similar to Ripple Adder
• Able to calculate the Carry bit before the Full Adder is
done with its operation.
• Faster but takes more logic.
Principle:
Consider the full adder circuit shown above with
corresponding truth table.
Let 2 variables be carry generate Gi & carry propagate Pi then,
Pi = Ai ⊕ Bi
G i = Ai B i
Sum output and carry output can be expressed as
Si = Pi ⊕ C i
C i +1 = Gi + Pi Ci
where
Gi is a carry generate which produces the carry when both
Ai, Bi are one regardless of the input carry.
Pi is a carry propagate and it is associate with the
propagation of carry from Ci to Ci +1.
Carry output Boolean function of each stage in a 4 stage carry-
Lookahead adder can be expressed as
C1 = G0 + P0 C 0

C 2 = G 1 + P 1 C 1 = G 1 + P 1 G0 + P 1 P 0 C 0

C3 = G2 + P2 C2 = G2 + P2 G1+ P2 P1 G0 + P2 P1 P0 C0

C4 = G3 + P3 C3 = G3 + P3 G2+ P3 P2 G1 + P3 P2 P1 G0 + P3 P2 P1 P0 C0

From the above Boolean equations, observe that C 4 does not have

to wait for C3 and C2 to propagate but actually C4 is propagated at

the same time as C3 and C2.

Implementation of three Boolean functions for each carry
output (C2, C3 and C4) is shown
16 bit Carry-Look Ahead Adder is constructed by cascading the four
4 bit adders with two more gate delays
Advantages
• Propagation delay is reduced - provides the fastest addition
logic.
Disadvantages
• Complicated as the number of variables increase.
• Costlier as it involves more number of hardware.
THANK YOU !!!!