UNIT 4

Memory, I/O and Peripheral Interfacing:

1.Address decoding,
2.memory interfacing for 8086,
3.I/O port address decoding,
4.Study of 8255 PPI and related programs
5.Interrupts: Basic Interrupt Processing, Hardware
Interrupts
SELECTION CONNECTION
RAM has CS’ and ROM has CE’ these 2 pins are low memory device performs a reads and
write operation.
Control inputs :
ROM :  OUTPUT ENABLE OC’ OR GATE G:which allows data to flow output pins of ROM .
If OE’ AND CE’ ARE ACTIVE ,, THE OUTPUT IS ENABLE
IF OE’ IS INACTIVE , THEN OUTPUT PINS ARE DISABLED
RAM has three control signal
•The output enable signal OE’ allows the selected data value be driven on
the data bus.
•Chip Enable CE’ which is used to address or select this particular memory
chip
•The WRITE ENABLE signal WE’, which, when set low, indicates that you are
writing to the RAM chip.
•OE’ must be active to perform read operation

Memory devices have address inputs to

1.Select a memory location within the device.
2.Almost always labeled from A0, the least significant address input, to
An
1.where subscript n can be any value
2.always labeled as one less than total number of address pins
3.A memory device with 10 address pins has its address pins labeled
from A0 to A9.
• Address bus:10 bit Address Space:1 Kbytes (210)
• Address bus:11 bit Address Space:2 Kbytes (211)
• Address bus:16 bit Address Space:64 KBytes (216)
• Address bus:20 bit Address Space:1 Mbytes
• Address bus:32 bit Address Space:4 GBytes
• Address bus:34 bit Address Space:16GBytes
• Address bus:36 bit Address Space:64GBytes
• Address bus:38 bit Address Space:256GBytes

If 64kbyte EPROM

• Then 2^6 1Kbyte= 2^6 x 2^10 = 2^16 byte
• therefore for 64KB= address line is 16
If 32kbyte EPROM
• Then 2^5 1Kbyte= 2^5 x 2^10 = 2^15 byte
• Therefore for 32KB= address line is 15
• An 8-bit-wide memory device is often called a byte-wide memory.
• most devices are currently 8 bits wide
• Memory devices often refer to memory locations times bits per
location.
A memory device with 1K memory locations and
8 bits in each location
• It is often listed as a 1K  8

1K

8 bits
1. With a neat diagram, illustrate simple NAND gate address decoding logic.
2. Illustrate how a 3-8 line decoder could be used to interface eight 8K memory
chips.
3. Design an 8086 based system to interface with 2K byte EPROM. Assume
EPROM is connected at FF800h. Use NANG gate for address decoding
4. Design an 8086 based system to interface with 64K byte EPROM. Assume
EPROM is connected at 30000h. Use 74LS138 for address decoding.
5. Interface four 8 KB RAMS starting with an address of 6000H. Draw the
address decoder table and memory map. Use 74LS138 for address decoding.
6. Explain the memory bank selection in 8086.
7. Develop an I/O port decoder, using a 74ALS138 that generates low-bank I/O
strobes, for 8086, for the following 8-bit I/O port addresses: 10H, 12H, 14H,
16H, 18H, 1AH, 1CH, and 1EH.
8. Develop an I/O port decoder, using a 74ALS138 that generates high-bank I/O
strobes, for an 8086, for the following 8-bit I/O port addresses: 11H, 13H,
15H, 17H, 19H, 1BH, 1DH, and 1FH.
9. Differentiate between Memory mapped I/O and I/O mapped I/O.
 ADDRESS DECODING
• WHY Decoding of address is necessary
― to attach a memory device to the microprocessor.
― It allows the microprocessor to address a single address within a
block of Memory or Input/ Output.
―It can access the data stored in the memory by specifying its address

―In 8086 has 20 address lines connections and the 2716 EPROM has
11 connections.
―The 8086 sends out a 20-bit memory address whenever it reads or
writes data
―Because the 2716 has only 11 address pins,
there is a mismatch that must be corrected
―The decoder corrects the mismatch by decoding address pins that
do not connect to the memory component.
00000H RAM

FFFFFH EROM
1. Design an 8086 based system to interface with 2K byte EPROM.
Use NAND gate for address decoding.
C B A
Memory Map 2K x 8 EPROM
A A A A A A A A A A A A A A A A A A A A
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0
FF800H -TO
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
FFFFFH

( using calc to find no. of lines ln2000/ln2 = 10.9 =11 address lines)
i.e A10 to A0
The remaining nine address pins (A19–A11).
The decoder selects the EPROM from one of the 2K-byte sections of
 Cont’d simple NAND gate decoder
When the 2K × 8 EPROM is used,
• address connections A10 to A1 of the 8086 are connected to address
inputs A10 to A0 of the EPROM.
• Decoding
• The remaining nine address pins (A19–A11) are connected to the inputs
of a NAND gate decoder
• In this circuit a NAND gate decodes the memory address
In this circuit , whenever the 8086 address pins attached to its input
are logic are’1’.
Output of NAND gate is logic ‘0’
The active low output of NAND gate decoder is connected to Chip
enable(CE) input pin  enables the EPROM
The output enable OE pin is activated by the 8086 RD signal
When chip enable pin and output enable pin is logic 0
Then EPROM will read the data
 Cont’d simple NAND gate decoder
• If the 20-bit binary address, decoded by the NAND
gate, is written so that the leftmost nine bits( A19-
A11) are 1s
• and the rightmost 11 bits (A0- A10) are don’t cares
(X), the actual address range of the EPROM can be
determined.
• a don’t care is a logic 1 or a logic 0, whichever is appropriate
• Example:
• 1111 1111 1xxx xxxx xxxx
• Or
• 1111 1111 1000 0000 0000 (FF800H) to
• 1111 1111 1111 1111 1111(FFFFFH)--
• The(211 ) 2K EPROM is decoded at memory address locations
FF800H–FFFFFH
The 3-to-8 Line Decoder Knowledge of IC
(74LS138)
a common integrated
circuit decoder found in
many systems is the
74LS138 3-to-8 line
decoder.
 Knowledge of IC
• The truth table shows that only one of the eight outputs ever
goes low at any time.
• To be active, the G2A and G2B inputs must both be low (logic
0), and G1 must be high (logic 1).

• For any of the decoder’s outputs to go low, the three enable

inputs (G2A ,G2B , and G1) must all be active.

• Once the 74LS138 is enabled, the address inputs (C, B, and A)

select which output pin goes low.
 2. Design an 8086 based system to
interface that uses eight 2764 EPROMs
(8K x 8)for a 64K  8 section of memory .
Sample Decoder Circuit: illustrated in Figure 10–15
•The outputs of the decoder are connected to eight different 2764
EPROM memory devices.
•Here, the decoder selects eight 8Kbyte blocks of memory for a total
memory capacity of 64K bytes
 It is know the EPROM ends at FFFFFH
 find the starting address
When the 8K × 8 EPROM is used
= 23 x 1K = 23 x 210 = 213 B
Required EPROM is 64KB hence 8KB eight is required
Therefore address lines required is13 line i.e A12 to A0
A19 toA13 are connected to 3-8 line decoder.
 CBA=000 Frist 8K × 8 EPROM is used
C B A
A A A A A A A A A A A A A A A A A A A A
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1
F0000H -TO F1FFFH
1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
F2000H to F3FFFH
 ABC are input select lines which are connected to A13,A14,A15
 G1= Input G1 is connected directly to A16.
 G2B: When all three address inputs (A17 A18 A19) are high, the output of this
NAND gate goes low and enables input G2B of the 74LS138.
 G2A is grounded.
 EPROM

DECODER

Select lines

Enable
Inputs
 Design
When the 8K × 8 EPROM is used,
• Address connections A12–A0 of the 8086 are connected to address
inputs A12–A0 of the EPROM.
• The remaining nine address pins (A19–A13) are connected to the
inputs of 3-8 line decoder
8K x 8 EPROM.
 = 23 x 1K = 23 x 210 = 213 B
Required EPROM is 64KB hence 8KB eight is required
Therefore address lines required is13 line i.e A12 to A0
A19 toA13 are connected to 3-8 line decoder 74138
ABC are input select lines which are connected to A13,A14,A15
G1= Input G1 is connected directly to A16.
G2B: When all three address inputs (A17 A18 A19) are high, the
output of this NAND gate goes low and enables input G2B of the
74LS138.
G2A is grounded.
Basic 8086 Memory Interface
Physical Memory System
Example (16 bit microprocessor)
High Bank Low Bank
(odd bank) (even bank)

FFFFFF FFFFFE
FFFFFD FFFFFC
FFFFFA

ECE291
FFFFFB

8 bits
8 bits

000005 000004
000003 000002
000001 000000
D15 - D8 D7- D0

January 18, 2001

10–4 8086 (16-Bit) MEMORY
INTERFACE
8086 has data bus is 16 bits
M/IO pin is used.
 Separate Bank Write Strobes
• The effective way to handle bank selection
is a separate write strobe for each bank.
• this requires only one decoder to select a 16-bit-
wide memory, which saves money
• Fig 10–29 depicts generation of separate
8086 write strobes.
• Separate read strobes for each bank are usually
unnecessary because 8086 read only the byte of data
they need at any given time from half of the data bus.
 Figure 10–29 The memory bank write
selection input signals: HWR (high bank
write) and LWR (low bank write).

Memory in a system using separate write strobes is decoded as 16-

bit-wide
Figure 10–29 depicts the generation of separate 8086 write strobes for
the memory.
a 74LS32 OR gate combines A0 with WR’ for the low bank selection
signal ( LWR’). ,
BHE’ combines with WR’ for the high bank selection signal ( HWR’).
 Two 4K x 8 EPROM= 23 x 210 = 213 = A12 to A0
A A A A A A A A A A A A A A A A A A A A
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

two 4K x 8 EPROM= 23 x 210 = 213 = A12 to A0

two 4K x 8 RAM= 23 x 210 = 213 = A12 to A0

A A A A A A A A A A A A A A A A A A A A
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

two 4K x 8 RAM= 23 x 210 = 213 = A12 to A0

A13 is used to select ROM or RAM
 Interfacing RAM to the 8086.
• Interface four 8KB RAMS starting with an address of 6000H to 8086
processor. Draw the address decoder table and memory map. Use
74LS138 for address decoding.
Given : 4 8Kb RAM; Starting address: 6000H
Solution: Memory Map
Address lines= 23 x 210 = 213 i.e A 12 to A0
i.e A 19 to A13 are connected to 3-8 line decoder.
A A A A A A A A A A A A A A A A A A A A
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
06000H -TO 07FFFH 1st chip select
0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
• Memory Map
06000H – 07FFFH----------- 1st chip select
08000H – 09FFFH----------- 2nd chip select
0A000H – 0BFFFH----------- 3rd chip select
0C000H – 0DFFFH----------- 4th chip select

Decoder

C(A15 ) B(A14 ) A(A13 ) CHIP SELECT

0 1 1 1st chip select
1 0 0 2nd chip select
1 0 1 3rd chip select
1 1 0 4th chip select
 • Interfacing RAM to the 8086.

A12- A1
Decoder 74134
MRD
CS2
Y4 CS1 RD
MWR
WR
Y3 MRD A12- A0
RD A12- A0 A12- A1
MWR WR
A13 A
D15- D0
A14 B
A12- A1
A15 C Y6
y5 CS4 MRD
CS3 RD
MRD WR MWR
y0 A12- A0 A12- A1 A12- A0
A16 G1 MWR
RD
GND GA Y1 WR

y2
D15- D0
GB y7

A17
A18
A19
 D9-D15

A1-A16

A1-A16

A0
I/O Port Address Decoding
 I/O INTERFACE
The I/O Instructions
•The instruction set contains a type of instruction that transfers
information to an I/O device (OUT) from microprocessor ( write
operation)
•Another to read information from an I/O device to microprocessor
(IN).

•Instructions that transfer data between an I/O device and the

microprocessor’s accumulator (AL, AX, ) are called IN and OUT.
•The I/O address is stored in register DX as a 16-bit address or in the
byte (p8) immediately following the opcode as an 8-bit address.
• Intel calls the 8-bit form (p8) a fixed address because it is stored
with the instruction
•The 16-bit address is called a variable address because it is stored in a
DX, and then used to address the I/O device.
I/O Instructions , Address, Ports
• I/O Instructions: transfer data between an I/O device and
the MP’s accumulator (AL, AX ):
• OUT : transfer information from MP to an I/O device.
• IN : read from an I/O device to MP .
• The I/O address is stored as:
• 16-bit Variable address: stored in a DX, and then
used to address the I/O device.
• 8-bit fixed address : stored with the instruction,
immediately following the opcode as an 8-bit address.
• I/O ports: are 8-bits width, a 16-bit I/O port is accessed as
two consecutive 8-bit ports.
How data are transferred using the IN or OUT

 I/O address ( called port number) appears on the address bus.

 The external I/O interface decodes the port number.
1. The 8-bit fixed port number (p8) appears on address bus
connections A0–A7 with bits A8–A15 equal to 000000002 . The
address A16-A19 are undefined for an I/O instruction.
2. The 16-bit variable port number (DX) appears on address connections
A0–A15.
 The first 256 I/O port addresses (00H–FFH) are accessed by both the
fixed and variable I/O instructions.
 0100H (256, 28 ) to FFFFH (65535, 216 ) is only accessed by the
variable I/O address.
 In dedicated systems only 8 bits of the address are decoded, thus
reducing the decoding circuits required.
 In a PC computer, all 16 address bus bits are decoded with locations
0000H–03FFH, which are the I/O addresses used for I/O inside the PC
on the ISA (industry standard architecture) bus
• Work out
• IN AL, p8 ; byte is input into AL from port p8
• IN AX, p8 ; A word is input into AX from port p8
• IN AL, DX ; A byte is input into AL from the port addressed by DX
• IN AX, DX ; A word is input into AX from the port addressed by DX

• OUT p8, AL ; A byte is output from AL into port p8

• OUT p8, AX ;16 A word is output from AL into port p8
• OUT DX, AL 8 A byte is output from AL into the port addressed by
DX
• OUT DX, AX 16 A word is output from AX into the port addressed
by DX
 Interfacing Methods

• There are two different methods of interfacing I/O to

the MP:
• Isolated I/O: the IN, and OUT instructions transfer data
between the MP’s accumulator or memory and the I/O
device.16 bit address, memory space 64Kb
• Memory-mapped I/O: any instruction that references
memory can accomplish the transfer.
• Both isolated and memory-mapped I/O are in use, The
PC does not use memory-mapped I/O.
Sl.No Isolated or I/O-Mapped I/O Memory-Mapped I/O
1 16 bits address lines , memory space is 64KB 20 bits address lines , memory space is 1MB

2 IN and OUT transfer data between the Memory-mapped I/O does not use the IN, or
microprocessor’s accumulator or memory OUTS instructions, but it uses All memory
and the I/O device. instructions are use Eg: MOV AX, N1

3 Register used is AX All registers are used

4 Addresses for isolated I/O devices, called memory transfer instruction can access the
ports, are separate from memory I/O device
5 Separate control signals for the I/O space , No need of any control signal
which indicate an I/O read (IORC) or an I/O
write (IOWC) operation
6 isolated means how I/O locations are Disadvantage is a portion of memory system
isolated from memory in a separate I/O is used as the I/O map.
address space reduces memory available to applications

7 A disadvantage of isolated I/O is that data

transferred between I/O and
microprocessor must be accessed by the IN,
and OUT instructions
Disadvantage of Isolated or I/O-Mapped I/O
: • The data transferred between I/O and the MP must be accessed by the IN and
OUT instructions.
• Separate control signals for the I/O space are developed (using M/IO and R/W ),
which indicate an I/O read ( IORC) or an I/O write (IOWC) operation
Decoding 8-Bit I/O Port Addresses
• Fixed I/O instruction uses an 8-bit I/O port address that on A15–A0 as
(0000 0000 0000 0000)2 to (0000 0000 1111 1111)2 or 0000H–00FFH.
• If a system will never contain more than 256 I/O devices,
we often decode only address connections A0– A7 for an 8-bit I/O port
address, Address from A8-A15 are ignored.
• The DX register can also address I/O ports 00H–FFH.
• If the address is decoded as an 8-bit address, we can never include I/O
devices using a 16-bit address.
• the PC never uses or decodes an 8-bit address
Q1.Develop an I/O port decoder, using a 74ALS138 that generates low-bank I/O
strobes, for 8086, for the following 8-bit I/O port addresses: F0H TO F7H.
Sol.
The address at Y4 will be F4H according to the following table.

Connected To NAND to GB2 G1 GA2 gnd C B A

A7 A6 A5 A4 A3 A2 A1 A0
1 1 1 1 0 1 0 0

The address at Y1 will be F1H according to the following table.

Connected To NAND to GB2 G1 GA2 gnd C B A

A7 A6 A5 A4 A3 A2 A1 A0
1 1 1 1 0 0 0 1
Figure 11–10
shows a 74ALS138 decoder that decodes 8-bit I/O ports F0H - F7H.
Identical to a memory address decoder except it is only connect address
bits A7–A0
to the inputs of the decoder

Logic 0
Q2.Develop an I/O port decoder, using a 74ALS138 that generates low-bank I/O strobes, for
8086, for the following 8-bit I/O port addresses: 10H, 12H, 14H, 16H, 18H, 1AH, 1CH, and 1EH.
Sol.
1EH:

Connected To NAND to GB2 G1 GA2 gnd C B A

A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 1 1 1 1 0

1CH :

Connected To NAND to GB2 G1 GA2 gnd C B A

A7 A6 A5 A4 A3 A2 A1 A0

0 0 0 1 1 1 0 0
 1AH:

Connected To NAND to GB2 G1 GA2 gnd C B A

A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 1 1 0 1 0

18H
Connected To NAND to GB2 G1 GA2 gnd C B A
A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 1 1 0 0 0

16H

14H:Connected To NAND to GB2 G1 GA2 gnd C B A

A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 1 0 1 1 0
 14H:

Connected To NAND to GB2 G1 GA2 gnd C B A

A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 1 0 1 0 0

12H:

14H:Connected To NAND to GB2 G1 GA2 gnd C B A

A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 1 0 0 1 0

11H:

14H:Connected To NAND to GB2 G1 GA2 gnd C B A

A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 1 0 0 0 1
A7 A6 A5 A4 A3 A2 A1 A0 Output Address of
G1 G2A C B A numbe the port.
G2B r
0 0 0 1 0 0 0 1 1 11H

0 0 0 1 0 0 1 0 2 12H

0 0 0 1 0 1 0 0 4 14H

0 0 0 1 0 1 1 0 6 16H

G2A
0 0 0 1 0 0 0 0 18H
1

G2A
0 0 0 1 0 1 0 2 1AH
1

G2A
0 0 0 1 1 0 0 4 1CH
1

G2A
0 0 0 1 1 1 0 6 1EH
A0 A1 A2 A3 A4 A5 A6 A7
A
11H
Y1
B 12H
C Y2
Y4
14H
Y6 16H
GA2

GB2
G1

G1
18H
Y0
GB2 Y2 1AH
GA2 1CH
Y4
Y6 1EH
A
B