Synchronous Sequential Circuit Design

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 Motivation

 Analysis of a few simple circuits

 Generalizes to Synchronous Sequential Circuits (SSC)

 Outputs are Function of State (and Inputs)
 Next States are Functions of State and Inputs
 Used to implement circuits that control other circuits
 "Decision Making" logic

 Application of Sequential Logic Design Techniques

 Word Problems
 Mapping into formal representations of SSC behavior
 Case Studies

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 Overview
 Concept of the Synchronous Sequential Circuits
 Partitioning into Datapath and Control
 When Inputs are Sampled and Outputs Asserted
 Basic Design Approach
 Six Step Design Process
 Alternative SSC Representations
 State Diagram, VHDL
 Moore and Mealy Machines
 Definitions, Implementation Examples
 Word Problems
 Case Studies
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 Concept of the Synchronous Sequential Circuit
Complex Digital System = Datapath + Control

Status
Registers SSC generating sequences
Combinational Functional of control signals
Units (e.g., ALU) Instructs datapath what to
Busses do next
Control

Control The “Supervisor”

State

Status Control
Inputs Outputs

The worker Datapath

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 Concept of the Synchronous Sequential Circuit
 Timing: When are inputs sampled, next state computed,
outputs asserted?
 State Time: Time between clocking events
 Clocking event causes state/outputs to transition, based on
inputs
 For set-up/hold time considerations:
 Inputs should be stable before clocking event
 After propagation delay, Next State entered, Outputs are
stable
 NOTE: Asynchronous output (Mealy) take effect immediately
 Synchronous outputs (Moore) take effect at the next clocking event
 E.g., tri-state enable: effective immediately
 sync. counter clear: effective at next clock event

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 Concept of the Synchronous Sequential Circuit
Example: Positive Edge Triggered Synchronous System

 On rising edge, inputs sampled;

State T ime outputs, next state computed
 After propagation delay, outputs
and next state are stable
 Immediate Outputs:
 affect datapath immediately
Clock  could cause inputs from datapath
to change
 Delayed Outputs:
 take effect on next clock edge
Inputs  propagation delays must exceed
hold times

Outputs

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 Sequential Circuit Analysis

 Start with schematic diagram

 Need to determine how circuit works
 Trace schematic, determine equations of operation
 FF input equations
 sequential circuit output equations
 Create State transition table
 Sequential circuit inputs, FFs are comb. logic inputs
 Organize truth table as current state (FFs) and inputs
 Create FF input, seq. Circuit output columns
 From FF char. Tables, determine FF next state values

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 Sequential Circuit Analysis (cont.)

 Generate State Diagram

 Circles (nodes) represent current or present state values
 Lines (arcs) represent how state and output values change
– Given the current state and current inputs, the next state and
output values are indicated by the associated arc
 State diagram can have different forms depending on the
type of sequential circuit output.

Inputs/outputs
Next
State
Present Value
State
Value

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 Basic Design Approach
 Six Step Process

1. Understand the statement of the Specification

2. Obtain an abstract specification of the SSC
3. Generate State Table
4. Perform state assignment
5. Choose FF types to implement SSC state register
6. Implement the SSC

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 Basic Design Approach
Example: Vending Machine SSC
General Machine Concept:
deliver package of gum after 15 cents deposited

single coin slot for dimes, nickels

no change

Step 1. Understand the problem:

Draw a picture!

Block Diagram N
Coin
Vending Open Gum
Sensor D
Machine Release
Reset SSC Mechanism

Clk

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 Vending Machine Example
Step 2. Map into more suitable abstract representation

Tabulate typical input sequences: Reset

three nickels S0
nickel, dime
dime, nickel N D
two dimes
two nickels, dime S1 S2

Draw state diagram:

N D
D N
Inputs: N, D, reset
S3 S4 S5 S6
Output: open
[open] [open] [open]
N D

S7 S8
[open] [open]

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 Vending Machine Example
Step 3: State Minimization
Present Inputs Next Output
Reset
0¢
State D N State Open
0¢ 0 0 0¢ 0
N 0 1 5¢ 0
5¢
1 0 10¢ 0
D 1 1 X X
5¢ 0 0 5¢ 0
N 0 1 10¢ 0
10¢ 1 0 15¢ 0
D 1 1 X X
N, D 10¢ 0 0 10¢ 0
15¢
0 1 15¢ 0
1 0 15¢ 0
[open]
1 1 X X
15¢ X X 15¢ 1
reuse states
whenever Symbolic State Table
possible

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 Vending Machine Example
Step 4: State Encoding D1 D0

Present State Inputs Next State Output

State Q1 Q0 D N Q 1+ Q+0 Open
0 0 0 0 0 0 0 NOTE!
0 1 0 1 0 For D-FFs the next
0¢ 1 0 1 0 0 state will be what
1 1 X X X is at the D input.
0 1 0 0 0 1 0 So each FF’s next
0 1 1 0 0 state values in the
5¢ state table must be
1 0 1 1 0 the D inputs for
1 1 X X X that FF.
1 0 0 0 1 0 0
0 1 1 1 0
10¢ 1 0 1 1 0
1 1 X X X
1 1 0 0 1 1 1
0 1 1 1 1
15¢ 1 0 1 1 1
1 1 X X X

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 Vending Machine Example
Step 5. Choose FFs for implementation D FF easiest to use
Q1 Q0 Q1 Q1 Q0 Q1 Q1 Q0 Q1
DN 00 01 11 10 DN 00 01 11 10 DN 00 01 11 10
00 0 0 1 1 00 0 1 1 0 00 0 0 1 0
01 0 1 1 1 N
01 1 0 1 1 N
01 0 0 1 0 N
11 X X X X 11 X X X X 11 X X X X
D D D
10 1 1 1 1 10 0 1 1 1 10 0 0 1 0

Q0 Q0 Q0
Q1
D D1 Q1
D Q
CLK \ Q1
Q0 RQ
N

N
\reset D1 = Q1 + D + Q0 N
\ Q0 OPEN

Q0
\N
D0 = N Q0 + Q0 N + Q1 N + Q1 D
D0 Q0
D Q
Q1
N
CLK
R
Q \ Q0 OPEN = Q1 Q0
Q1 \reset 8 Gates
D

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 Designing with SR, JK, and T Flip-Flops

 Sequential design with D-FFs is easy; next state

depends on D input only
 We can use other FFs but the process is a little
more involved
 State table defines set of present state to next state
transitions
 What we need to design the next state combinational
logic is the FF input values needed for each Q  Q+
transition
 This table is known as the FF excitation table
 Derived from the FF characteristic table

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 Derivation of JK Excitation Table

JK Characteristic Table JK Excitation Table

J K Q Q+ Q Q+ J K

0 0 0 0 0 0 0 X
0 0 1 1 0 1 1 X
0 1 0 0 1 0 X 1
0 1 1 0 1 1 X 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0

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 Flip-Flop Excitation Tables

Q Q+ J K S R T D

0 0 0 X 0 X 0 0
0 1 1 X 1 0 1 1
1 0 X 1 0 1 1 0
1 1 X 0 X 0 0 1

You can use any FF type for your implementation

FF types can be mixed; I.e. in vending machinge

you could use a JK FF for Q1 and a T FF for Q0

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 Vending Machine Example
Step 5. Choosing FF for Implementation
J-K FF Present State Inputs Next State J1 K1 J0 K 0
Q1 Q0 D N Q+1 Q+0
JK Excitation Table 0 0 0 0 0 0 0 X 0 X
0 1 0 1 0 X 1 X
1 0 1 0 1 X 0 X
Q Q+ J K 1 1 X X X X X X
0 1 0 0 0 1 0 X X 0
0 0 0 X 0 1 1 0 1 X X 1
0 1 1 X 1 1 1 X X 0
1 0 X 1 1 0
1 1 X 0 1 1 X X X X X X
1 0 0 0 1 0 X 0 0 X
0 1 1 1 X 0 1 X
1 0 1 1 X 0 1 X
1 1 X X X X X X
1 1 0 0 1 1 X 0 X 0
0 1 1 1 X 0 X 0
1 0 1 1 X 0 X 0
1 1 X X X X X X

Remapped encoded state transition table using JK excitation table

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 Vending Machine Example
Implementation:
Q1 Q1
Q1 Q0 Q1 Q0 J1 = D + Q0 N
DN 00 01 11 10 DN 00 01 11 10
00 0 0 X X 00 X X 0 0 K1 = 0
01 0 1 X X 01 X X 0 0
N N
11 X X X X 11 X X X X J0 = N + Q1 D
D D
10 1 1 X X 10 X X 0 0 K0 = Q1 N

Q0 Q0 N
Q1 Q0 Q1 Q1 Q0 Q1 Q0 J Q1
Q
00 01 11 10 00 01 11 10 D
DN DN CLK K RQ
\ Q1
\ Q0
00 0 X X 0 00 X 0 0 X N
OPEN
Q1
01 1 X X 1 01 X 1 0 X
N N D
J Q
Q0
CLK
11 X X X X 11 X X X X \ Q1
K Q
\ Q0
D D N R
10 0 X X 1 10 X 0 0 X
\reset 7 Gates
Q0 Q0

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 Moore vs. Mealy Machines
Definitions Moore Machine Mealy Machine

Outputs are function Outputs depend on

solely of the current state AND inputs
state
Input change causes
Outputs change an immediate
synchronously with (asynchronous)
state changes output change
Mealy only; no connection for Moore
X
Inputs
State
Register

Combinational
Comb.
Logic for Z
Logic for
Next State Outputs
Outputs)
(FF Inputs)

State
Feedback Clock

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 Moore and Mealy Machines
State Diagram Equivalents

Mealy (N D + Reset)/0
Reset
N D + Reset Moore
Machine Reset/0
0¢ 0¢ Machine
Reset/0 Reset [0]
N/0 N

5¢ 5¢
D/0 D
N D/0 ND [0]

N/0 N

10¢ 10¢
D/1 N D/0 [0] ND
N+D/1 N+D

15¢ 15¢
Reset/1 Reset
[1]

Outputs are associated Outputs are associated

with Transitions with State

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 Moore and Mealy Machines
States vs. Transitions
Mealy Machine typically has fewer states than Moore Machine
for same output sequence

0 0/0
0
0

[0]
Same I/O behavior 0 1
0/0 1/0
0 1
1
Different # of states
[0]
1 1/1
2

[1] 1

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 Moore and Mealy Machines
Synchronous Mealy Machine

X
Inputs
State Output
Register Register

Combinational
Comb.
Logic for Z
Logic for
Next State Outputs
Outputs)
(FF Inputs)

State
Feedback Clock Clock

Latched state AND outputs

Avoids glitchy outputs!
Outputs are delayed by up to 1 clock period
Usually equivalent to the Moore form

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 Synchronous Sequential Circuit Word Problems
Mapping English Language Description to Formal Specifications

Four Case Studies:

• Finite String Pattern Recognizer

• Complex Counter with Decision Making

• Traffic Light Controller

• Digital Combination Lock

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 Synchronous Sequential Circuit Word Problems
Finite String Pattern Recognizer

A finite string recognizer has one input (X) and one output (Z).
The output is asserted whenever the input sequence …010…
has been observed, as long as the sequence 100 has never been
seen.

Step 1. Understanding the problem statement

Sample input/output behavior:

X: 00101010010…
Z: 00010101000…

X: 11011010010…
Z: 00000001000…

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 Synchronous Sequential Circuit Word Problems
Finite String Recognizer
Step 2. Draw State Diagrams for the strings that must be
recognized. I.e., 010 and 100.
Reset
S0
/0
0 1 Moore State Diagram
Reset signal places
S1 S4 SSC in S0
/0 /0

1 0
S2 S5
/0 /0

0 0 0,1
S3 S6 Loops in State
Outputs 1 /1 /0

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 Synchronous Sequential Circuit Word Problems
Finite String Recognizer
Exit conditions from state S3: have recognized …010
if next input is 0 then have …0100!
if next input is 1 then have …0101 = …01 (state S2)

Reset
S0
/0
0 1

S1 S4
/0 /0

1 0
S2 S5
/0 /0

1 0 0 0,1
0
S3 S6 Loops in State
Outputs 1 /1 /0

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 Synchronous Sequential Circuit Word Problems
Finite String Recognizer
Exit conditions from S1: recognizes strings of form …0 (no 1 seen)
loop back to S1 if input is 0
Exit conditions from S4: recognizes strings of form …1 (no 0 seen)
loop back to S4 if input is 1
Reset
S0
/0
0 1
0 1
S1 S4
/0 /0

1 0
S2 S5
/0 /0

1 0 0 0,1
0
S3 S6 Loops in State
Outputs 1 /1 /0

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 Synchronous Sequential Circuit Word Problems
Finite String Recognizer
S2 = …01; If next input is 1, then string could be prefix of (01)1(00)
S4 handles just this case!
S5 = …10; If next input is 1, then string could be prefix of (10)1(0)
S2 handles just this case!
Reset
S0
/0
0 1
0 1
S1 S4
/0 /0

1 1 0 Final State Diagram

S2 1 S5
/0 /0

1 0 0 0,1
0
S3 S6 Loops in State
Outputs 1 /1 /0

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 Synchronous Sequential Circuit Word Problems
Finite String Recognizer
Review of Process:

• Write down sample inputs and outputs to understand specification

• Write down sequences of states and transitions for the sequences

to be recognized

• Add missing transitions; reuse states as much as possible

• Verify I/O behavior of your state diagram to insure it functions

like the specification

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 Synchronous Sequential Circuit Word Problems
Complex Counter
A sync. 3 bit counter has a mode control M. When M = 0, the counter
counts up in the binary sequence. When M = 1, the counter advances
through the Gray code sequence.

Binary: 000, 001, 010, 011, 100, 101, 110, 111

Gray: 000, 001, 011, 010, 110, 111, 101, 100

Valid I/O behavior:

Mode Input M Current State Next State (Z2 Z1 Z0)

0 000 001
0 001 010
1 010 110
1 110 111
1 111 101
0 101 110
0 110 111

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 Synchronous Sequential Circuit Word Problems
Complex Counter
One state for each output combination
Add appropriate arcs for the mode control

S0 0,1
0 /000
S7 S1
/111 /001
1 0
0,1 1
1
S6 1 S2
/110 /010

0 0 1
1
S5 S3
/101 /011
0 S4 0
/100

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 Synchronous Sequential Circuit Word Problems
Traffic Light Controller

A busy highway is intersected by a little used farmroad. Detectors

C sense the presence of cars waiting on the farmroad. With no car
on farmroad, light remain green in highway direction. If vehicle on
farmroad, highway lights go from Green to Yellow to Red, allowing
the farmroad lights to become green. These stay green only as long
as a farmroad car is detected but never longer than a set interval.
When these are met, farm lights transition from Green to Yellow to
Red, allowing highway to return to green. Even if farmroad vehicles
are waiting, highway gets at least a set interval as green.

Assume you have an interval timer that generates a short time pulse
(TS) and a long time pulse (TL) in response to a set (ST) signal. TS
is to be used for timing yellow lights and TL for green lights.

Note: The interval timer is just another sequential circuit!

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 Synchronous Sequential Circuit Word Problems
Traffic Light Controller
Picture of Highway/Farmroad Intersection:

Farmroad

C
HL
FL
Highway

Highway

FL
HL C

Farmroad

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 Synchronous Sequential Circuit Word Problems
Traffic Light Controller
• Tabulation of Inputs and Outputs:
Input Signal Description
reset place SSC in initial state
C detect vehicle on farmroad
TS short time interval expired
TL long time interval expired

Output Signal Description

HG, HY, HR assert green/yellow/red highway lights
FG, FY, FR assert green/yellow/red farmroad lights
ST start timing a short or long interval

• Tabulation of Unique States: Some light configuration imply others

State Description
S0 Highway green (farmroad red)
S1 Highway yellow (farmroad red)
S2 Farmroad green (highway red)
S3 Farmroad yellow (highway red)

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 Synchronous Sequential Circuit Word
Problems
Traffic Light Controller
Compare with state diagram:

TL + C
Reset
S0 S0: HG, FR
TL•C/ST TS/ST
S1: HY, FR
TS S1 S3 TS S2: FG, HR

TS/ST S3: FY, HR

TL + C/ST
S2

TL • C

Note: This sequential circuit has both Mealy and Moore outputs!

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 Synchronous Sequential Circuit Word
Problems
Digital Combination Lock

"3 bit serial lock controls entry to locked room. Inputs are RESET,
ENTER, 2 position switch for bit of key data. Locks generates an
UNLOCK signal when key matches internal combination. ERROR
light illuminated if key does not match combination. Sequence is:
(1) Press RESET, (2) enter key bit, (3) Press ENTER, (4) repeat (2) &
(3) two more times."

Problem specification is incomplete:

• how do you set the internal combination?
• exactly when is the ERROR light asserted?

Make reasonable assumptions:

• hardwired into next state logic vs. stored in internal register
• assert as soon as error is detected vs. wait until full combination
has been entered

Our design: registered combination plus error after full combination

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 Synchronous Sequential Circuit Word
Problems
Digital Combination Lock
Understanding the problem: draw a block diagram …
RESET

Operator Data ENTER UNLOCK

KEY-IN
Combination
Lock FSM ERROR
L0
Internal
Combination L1
L2

Inputs: Outputs:
Reset Unlock
Enter Error
Key-In
L0, L1, L2

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 Synchronous Sequential Circuit Word Problems

Note that each key entry is really a two-step process

1. Wait for the enter key
2. Check if correct key was selected

Enter=‘0’
Si

Enter=‘1’

Sj
KI /= Li
KI = Li
Check To error
next key sequence

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 Synchronous Sequential Circuit Word
Problems Reset + Enter
Digital Combination Lock Reset
Start

State Diagram Reset • Enter

Comp0
KI = L0 KI ≠ L0

Enter
Idle0 Idle0a Enter

Enter Enter

Comp1 Error1
KI ≠ L1
KI = L1

Enter
Enter Idle1 Idle1a

Enter Enter

Comp2 Error2

KI = L2 KI ≠ L2

Reset
Done Error3
Reset
[Unlock] [Error]

Reset
Reset

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