Data Path

&
Arithmetic Hardware
1

W H AT I S D ATA - PAT H ?
H Y P O T H E T I C A L D ATA - PAT H D E S I G N
C O N T R O L U N I T F O R H Y P O T H E T I C A L D ATA - PAT H
INSTRUCTION FOR HYPOTHETICAL PROCESSOR
ADDITION & SUBTRACTION
M U LT I P L I C AT I O N
DIVISION
ALU
CONTROL DESIGN
HARD-WIRED CONTROL
MICROPROGRAMED CONTROL

DATAPATH AND CONTROL UNIT

 What is data-path
2

 Data path provides the way (path) around various processing

components of a processor.

 ALU, Bank of Registers and various Multiplexers form the data

path.

 Control unit together with the data path is responsible for

movement and processing of the data as intended by the
Instruction given by the user.

DATAPATH AND CONTROL UNIT

 Components of Data path
3

 Bank of Registers ALU MUX

R1
R2
A

RJ

Control

CLK @ 1 @ 2 DATA
R/W’

DATAPATH AND CONTROL UNIT

 Hypothetical data path design
(ref: https://www.youtube.com/watch?v=ibYYqvp9FmU)
4

Register Bank
R1
MUX O
R2 uO
tU
T
r
R
e
ALU G
gI
iS
sT
tE
er
R
MUX

RJ

CLK @ 1 @ 2 DATA
R/W’ CLK
Control
Signals m1 m0
ALU
CONT
DATAPATH AND CONTROL UNIT
 5

Control Signals are R/, @1, @2, m1, m2, OP, CLK
The above string of Signals are called CONTROL WORD

Operation to be performed : R3 = R1 + R2
Clock Control Signal Activation
1 R/ = READ; @1 = @R1, @2 = @R2; m1 = m2 = RB;
OP = ADD;
2 OUT REG = R1 + R2 (STATUS);
R/ = WRITE; @1 = R3;

DATAPATH AND CONTROL UNIT

 6

OPERATION TO BE PERFORMED : R3 = 2R1 + R2

R3 = (R1 + R2) + R1
CLOCK
PULSE CONTROL SIGNAL ACTIVATION
(T-STATE ??)
1 R/ = READ; @1 = @R1, @2 = @R2; m1 = m2 = RB;
OP = ADD;
2 OUT REG = R1 + R2 (STATUS);
m1 = RB, m2 = OUT REG, R/ = READ, OP = ADD
@1 = R1;
3 OUT REG = (R1 + R2) + R1 = 2R1 + R2;
R/ = WRITE; @1 = R3;
DATA = OUT REG;

DATAPATH AND CONTROL UNIT

 7

Hypothetical data path design

(ref: https://www.youtube.com/watch?v=ibYYqvp9FmU)

THE VIDEO AVAILABLE AT ABOVE LINK OF YOUTUB

E

DATAPATH AND CONTROL UNIT

 Bus driven processors:
8

A MODIFICATION OF
VON-NEUMANN
MACHINE

DATAPATH AND CONTROL UNIT

 Data path in 8085
9

DATAPATH AND CONTROL UNIT

 Data path in 8086
10

DATAPATH AND CONTROL UNIT

 ACTUAL WIRE CONNECTIONS

DATAPATH AND CONTROL UNIT 11

 BUS NOTATION
12

DATAPATH AND CONTROL UNIT

 Design of our own
processor
13

S I M P L E AS P O S S I B L E
A RC H I T E C T U RE

SAP
( S O U R C E : D I G I TA L C O M P U T E R E L E C T R O N I C S
BY
A . P. M A LV I N O ( P H I )

DATAPATH AND CONTROL UNIT

 14
𝑪 𝑷 𝑬 𝑷 𝑳 𝑴 𝑪𝑬 𝑳 𝑰 𝑬 𝑰 𝑳 𝑨 𝑬 𝑨 𝑺𝒖 𝑬 𝒖 𝑳 𝑩 𝑳 𝟎
CLR
CP CLR CLK CLR
CLK L’ CLK L’ CLK E’I CLK’ CLR’
EP M CE’ I

PROGRAM INPUT AND

4 16 X 8 INSTRUCTION CONTROLLER/
REGISTER
4 SEQUENCER
COUNTER MAR RAM
4
4 4 8 8 4
INTERNAL BUS
8 8 8 8 8

ACCUMULATOR ADDER / REGISTER OUTPUT BINARY

A 4 4 8
SUBTRACTOR B REGISTER DISPLAY

L’ CLK E E S L’ L’
A U U B O
A
CLK CLK

DATAPATH AND CONTROL UNIT

 Description of the hypothetical instructions
15

 LDA : LDA stands for “Load the Accumulator” and it contains

HEX address from where the data is to be loaded in the
Accumulator. Example: LDA 8H
 ADD: Adds the content of Accumulator with contents of memory
location, in HEX specified with ADD. Example: ADD 9H.
Contents of 9H is first transferred to B. A and B are then added
up in ALU. Result will be loaded in the Accumulator.
 SUB: Subtracts the contents of memory location specified with
SUB from the contents of Accumulator. Example: SUB CH.
Result will be loaded in the Accumulator.

CONTROL UNIT
 Description of the hypothetical instructions
16

OUT: OUT instruction transfers the contents of the

Accumulator to the OUTPUT Register. (implicit)
HLT: HALT the execution. Marks the end of the
program.
FORMATION (DESIGN) OF THE
OPCODE
Mnemonic OPCODE
LDA 0000
ADD 0001
SUB 0010
OUT 1110
HLT 1111

CONTROL UNIT
 Simple As Possible (SAP) Architecture -4
17

Control Matrix for Fetch Cycle of SAP

CONTROL WORD:

T State Control Sq. Active Bits

T1 5E3H EP , M
T2 BE3H CP
T3 263H I

OPERATION #1: LOAD

OPEARTION #2: ADD
OPERATION #3: SUB
OPERATION #4: OUT
OPERATION #5: HLT
CONTROL UNIT
 Simple As Possible (SAP) Architecture -5
18

Complete Control Matrix of SAP Architecture

T State Control Sq. Active Bits Routine
T1 5E3H EP , M
FETCH
T2 BE3H CP
T3 263H I

T4 1A3H M ,I
LDA
T5 2C3H ,A
T6 3E3H ---
T4 1A3H M ,I
ADD
T5 2E1H ,B
T6 3C7H A , U , EU

CONTROL UNIT
 Simple As Possible (SAP) Architecture -6
19

Complete Control Matrix of SAP Architecture -- CONTD.

T State Control Sq. Active Bits Routine
T4 1A3H M ,I
SUB
T5 2E1H ,B
T6 3C7H A , SU , EU
T4 3F2H EA , O
OUT
T5 3E3H ---
T6 3E3H ---

CONTROL UNIT
 Control Unit
 The purpose of Control Unit is to issue CONTROL
SIGNALS to the Data Path for execution of the instruction.

 The control Unit logically reconfigures the DATA Path to

implement some specified instruction.

 Control Unit Design (two methods)

 Hardwired control unit

 Microprogrammed control unit

DATAPATH AND CONTROL UNIT 20

 Control Unit
Status Control
signals signals
Sequential
Logic
Circuit

Instruction
Register

Schematic Hardwired Control Unit

The sequential circuit is normally a Moore Machine in contrast to a
Mealy Machine.

DATAPATH AND CONTROL UNIT 21

 Hardwired Control Unit
22

 Control unit design is a tread-off among ‘amount of

hardware’, ‘Speed of operation’, and ‘cost of design
process’.
 Methods of Hardwired Design
 Classical Design: - In this method the hardware is
optimized and efforts are made to use log P flip-flops to
2
realize a P. state circuit.
 One-Hot Method: - Hardware is not optimized and one
flip-flop can be used to realize one state.

DATAPATH AND CONTROL UNIT

 Classical Design (J P Hayes)
Step 1: Formulate the general method (Algorithm)
23

Problem Statement: The GCD gcd (in: X, Y; out : z)

Processor register XR, YR, TEMPR;
begin
It is a special purpose processor XR:= X; YR:= Y;
which calculates the greatest while (XR> 0) do
common divisor gcd(X, Y) of begin
if (XR<=YR) then
two variables X, and Y, begin
respectively. TEMPR:= XR;
XR:= YR;
It is customary to assume that YR:= TEMPR;
gcd(0, 0) = 0. end
The shown algorithm, which is a XR:= XR – YR;
end
variant of Euclid’s Algorithm is Z:= YR;
used. end (gcd)

DATAPATH AND CONTROL UNIT

 CLASSICAL DESIGN
Greatest Common Divisor (gcd) Processor
24

gcd(in: X, Y; out: Z);

register XR, TR, TEMPR;
XR:= X; /*Input the data
YR:= Y;
while (XR > 0) do begin
if (XR <= YR) then begin /*swap XR with YR
TEMPR:= YR;
YR:= XR;
XR:= TEMPR; end (if)
XR:= XR – YR; /*subtract YR from XR
end (while)
Z:= YR; /* output the result
end (gcd);
DATAPATH AND CONTROL UNIT
 Classical Design
Step 2: Draw the flow-chart/state diagram
25 Start

 Since the operation XR:=X; YR:=Y;

swap requires the
No
steps which can be Is XR>=0
performed in a
single clock cycle Yes
Yes IS
hence ‘swap’ can be
XR>=YR
taken as an atomic
Z:= YR No
operation.
SWAP (XR, YR)
 The resulting flow
chart is shown End
XR:= XR – YR

DATAPATH AND CONTROL UNIT

 Classical Design
step 3: The state diagram
26

10
S S C1 = (Is XR>=0)
0 1
C0 = (Is XR > = YR)
0d/ C1 C0
0d 11 10/1 10 0 0
1 d
0 1
1 0
S S 1 1
0d/10/11 3 0d 2
11

DATAPATH AND CONTROL UNIT

 27

PRESENT Next S+- Inputs are c1c0 Subtract Swap Select Load Load
STATE XY XR YR
0d 10 11

Begin S0 S3 S1 S2 0 0 1 1 1
Swap S1 S2 S2 S2 0 1 0 1 1
Sub S2 S3 S1 s2 1 0 0 1 0
End S3 S3 S3 S3 0 0 0 0 0
Table 2: State table drawn with the help of the state diagram of the fig. 2

 Control signals required are also listed

 State reduction may be carried out if required
 It is always better to have an idea of the hardware required for the
implementation of the above (reduced, if reqd.) State- Table.
DATAPATH AND CONTROL UNIT
 Approximate Hardware
28

Select XY
MUX SWAP
SUBTRACT

XR YR Load YR

Load XR

SUBTRACT COMPARE
(XR >= YR)

(XR > 0)

DATAPATH AND CONTROL UNIT

 STATE ASSIGNMENT
29

STATE Assigned
States  Once the States are assigned: -
 Decide the type of Flip-flops will
S0 00
be used for implementation of
S1 01
the states (or it may be given by
S2 10
the user)
S3 11  Derive the next state using the
excitation required for each flip-
Table 3: State –
assignment table flop, i.e., formulate the excitation
table for the given flip-flops

DATAPATH AND CONTROL UNIT

 Excitation equations
30

For RS Flip-flop
provided
For JK Flip-flop

For T Flip-flop

For D Flip-flop

DATAPATH AND CONTROL UNIT

 C1 C0 D1 D0 D+ 1 D+ 0 SUB SWAP Select XY Load XR Load YR
0 0 0 0 1 1
0 0 0 1 1 0 31
0 0 1 0 1 1
0 0 1 1 1 1
0 1 0 0 1 1
0 1 0 1 1 0
0 1 1 0 1 1
0 1 1 1 1 1
1 0 0 0 0 1
1 0 0 1 1 0
1 0 1 0 0 1
1 0 1 1 1 1
1 1 0 0 1 0
1 1 0 1 1 0
1 1 1 0 1 0
1 1 1 1 1 1
DATAPATH AND CONTROL UNIT
 Minimization for D +
and D +
0 1
32

DoD1 DoD1
00 01 11 10 00 01 11 10
CoC1 CoC1

00 1 0 1 1 00 1 1 1 1

01 1 0 1 1 01 1 1 1 1

11 0 0 1 0 11 1 1 1 1

10 1 0 1 1 10 1 0 1 1

Solving for D0+

DATAPATH AND CONTROL UNIT

 The Minimized Boolean Expressions For The
States And Control Signals
33

DATAPATH AND CONTROL UNIT

 One hot design steps
34

Prepare the optimized state-diagram (state-table) with

the details of control signals;

Assign one Flip-flop for each state;

Write the next-state Boolean expressions as per the

incident inputs and previous state

Implement the Boolean Expressions in hardware

DATAPATH AND CONTROL UNIT

 The Minimized Boolean Expressions For The
States And Control Signals
35

10
S S
0 1 =
0d/
0d 11 10/ 10
11
SWAP = D1
SUB = D2
0d/10/11

S S SELECTXY = D0
3 0d 2
11
LOAD XR = D0 + D1 + D2
LOAD YR = D0 + D1

DATAPATH AND CONTROL UNIT

 Control Unit
Schematic of microprogrammed Control Unit

Address Control
Logic Memory

Microinstruction
Decoder
Register

Instruction
Register

Schematic microprogrammed Control Unit

DATAPATH AND CONTROL UNIT 36
 Simple As Possible (SAP) Architecture -5
37

Complete Control Matrix of SAP Architecture

T State Control Sq. Active Bits Routine
T1 5E3H EP , M
FETCH
T2 BE3H CP
T3 263H I

T4 1A3H M ,I
LDA
T5 2C3H ,A
T6 3E3H ---
T4 1A3H M ,I
ADD
T5 2E1H ,B
T6 3C7H A , U , EU

CONTROL UNIT
 Simple As Possible (SAP) Architecture -6
38

Complete Control Matrix of SAP Architecture -- CONTD.

T State Control Sq. Active Bits Routine
T4 1A3H M ,I
SUB
T5 2E1H ,B
T6 3C7H A , SU , EU
T4 3F2H EA , O
OUT
T5 3E3H ---
T6 3E3H ---

CONTROL UNIT
 SAMPLE INTUITIVE DESIGN OF

HARDWIRED CONTROL UNIT FOR L FOR

M

SAP – 1

ARCHITECTURE

ONE HOT METHOD

DATAPATH AND CONTROL UNIT 39

 RING COUNTER: GENERATION OF TIMING STATE
(T – STATE)

DATAPATH AND CONTROL UNIT 40

 RING COUNTER: GENERATION OF TIMING STATE
(T – STATE)

DATAPATH AND CONTROL UNIT 41

 Microprogrammed -1
ADDRESS T State Control Sq. Active Bits Routine
00 T1 5E3H EP , M
FETCH
01 T2 BE3H CP
02 T3 263H I

03 T4 1A3H M ,I
LDA
04 T5 2C3H ,A
05 T6 3E3H ---
06 T4 1A3H M ,I
ADD
07 T5 2E1H ,B
08 T6 3C7H A , U , EU
09 T4 1A3H M ,I
SUB
0A T5 2E1H ,B
0B T6 3C7H A , SU , EU
0C T4 3F2H EA , O
OUT
0D T5 3E3H ---
0E T6 3E3H ---
 Control Unit

DATAPATH AND CONTROL UNIT 43

 CLASSICAL DESIGN: GCD Processor

DATAPATH AND CONTROL UNIT 44

 MICROPROGRAMMED IMPLEMENTATION OF SAP ARCHITECTURE
45

The hardwired implementation for even SAP is fairly

complicated and cumbersome to implement.

For larger systems, hardwired control may require

hundreds of thousands of gates with many levels.

No flexibility is available afterwards.

The designer opted for alternate implementation,

Microprogramed (ROM) implementation of control Unit.
CONTROL UNIT
DATAPATH AND CONTROL UNIT 46
DATAPATH AND CONTROL UNIT 47
 48

DATAPATH AND CONTROL UNIT

 ADDITION
49

Addition
Parallel Adders

A3 B 3 A2 B 2 A1 B 1 A0 B 0

Cout

S3 S2 S1 S0

DATAPATH AND CONTROL UNIT

 Basic Signals
50

Generate signal: gi = xi y i
Propagate signal: pi = xi  y i

Anihilate (absorb) signal: a i = xi y i = xi + yi

Carry recurrence

ci+1 = gi + cipi

DATAPATH AND CONTROL UNIT

 4-bit Carry-Lookahead Adder (1)
51

c4 = g3 + c3p3 = g3 + g2 p3 + g1 p2p3 + g0p1p2p3 + c0p0p1p2p3

c3 = g2 + g1 p2 + g0 p1p2 + c0p0p1p2
c2 = g1 + g0 p1 + c0p0p1
c1 = g0 + c0 p0
s0 = x0  y0  c0 = p0  c0
s1 = p1  c1
s2 = p2  c2
s3 = p3  c3
DATAPATH AND CONTROL UNIT
4-bit Carry Network with Full Lookahead
52

DATAPATH AND CONTROL UNIT

 Negative Numbers
53

Representation of Negative Numbers in Computers

Sign Magnitude Notation: A =
 Disadvantages ????

 Two’s Complement representation: 1

A= -
If an-1 is zero then the number is positive.
If an-1 is one then the resulting number
2 is negative and
obtained by subtraction as shown in 2 above.

DATAPATH AND CONTROL UNIT

 Negative Numbers
Ref: William Stallings
54

 Four bit representations of positive and negative numbers in Sign-Mag Form

 +7 = 0111
 -7 = 1111
 Four bit representations in Two’s Complement representation
 +7 = 0111
 -7 = 1001
 Eight bit representations of positive and negative numbers in Sign-Mag Form
 +7 = 00000111
 -7 = 10000111
 Eight bit representations in Two’s Complement representation
 +7 = 00000111
 -7 = 11111001 = -128 +64+32+16+8+1 (=121) = -7

DATAPATH AND CONTROL UNIT

 Parallel Subtractor
55

Controlled Adder/ Subtractor:-

 OP is the control input such that if OP =0 addition is performed. If
OP=1 then two’s complement subtraction (A – B) is performed.
 C4 is the final carry / borrow.

DATAPATH AND CONTROL UNIT

 Shift/Add Multiplication Algorithms
ref : Behrooz Perhami
56

Notation for our discussion of multiplication algorithms:

a Multiplicand ak–1ak–2 . . . a1a0
x Multiplier xk–1xk–2 . . . x1x0
p Product (a  x) p2k–1p2k–2 . . . p3p2p1p0
Initially, we assume unsigned operands
a Multiplicand
 x Multiplier
x 0 a 20
Partial
x 1 a 21
products
x 2 a 22 bit-matrix
x 3 a 23
p Product
Multiplication of two 4-bit unsigned binary numbers in dot notation.
DATAPATH AND CONTROL UNIT
 HARDWIRED VS CONTROL ROM
57

 Pros of Hardwired Control Unit

• Hardwired Control Unit is quick due to the usage of combinational
circuits to generate signals.
• The amount of delay that can occur in the creation of control signals
is dependent on the number of gates.
• It can be tweaked to get the fastest mode of operation.
• Quicker than a micro-programmed control unit.
 Cons of Hardwired Control Unit
• As we require additional control signals to be created, the design
becomes more complex (need for more encoders or decoders).
• Changes to control signals are challenging since they necessitate
rearranging wires in the hardware circuit.
• It’s difficult and time-consuming to add a new feature.
• It’s difficult to evaluate and fix flaws in the initial design.
• It’s a bit pricey.

DATAPATH AND CONTROL UNIT

 58

DATAPATH AND CONTROL UNIT

 59

DATAPATH AND CONTROL UNIT

 60

DATAPATH AND CONTROL UNIT

 61

DATAPATH AND CONTROL UNIT

 62

DATAPATH AND CONTROL UNIT

 63

DATAPATH AND CONTROL UNIT

 64

DATAPATH AND CONTROL UNIT

 65

DATAPATH AND CONTROL UNIT

 66

DATAPATH AND CONTROL UNIT

 67

DATAPATH AND CONTROL UNIT

 68

DATAPATH AND CONTROL UNIT

 Example
ref : Behrooz Perhami
69
Right-shift algorithm Left-shift algorithm
======================== =======================
a 1 0 1 0 a 1 0 1 0
x 1 0 1 1 x 1 0 1 1
======================== =======================
p(0) 0 0 0 0 p(0) 0 0 0 0
+x0a 1 0 1 0 2p(0) 0 0 0 0 0
––––––––––––––––––––––––– +x3a 1 0 1 0
2p(1) 0 1 0 1 0 ––––––––––––––––––––––––
p(1) 0 1 0 1 0 p(1) 0 1 0 1 0
+x1a 1 0 1 0 2p(1) 0 1 0 1 0 0
––––––––––––––––––––––––– +x2a 0 0 0 0
2p(2) 0 1 1 1 1 0 ––––––––––––––––––––––––
p (2)
0 1 1 1 1 0 p(2) 0 1 0 1 0 0
+x2a 0 0 0 0 2p (2)
0 1 0 1 0 0 0
––––––––––––––––––––––––– +x1a 1 0 1 0
2p(3) 0 0 1 1 1 1 0 ––––––––––––––––––––––––
p (3)
0 0 1 1 1 1 0 p(3) 0 1 1 0 0 1 0
+x3a 1 0 1 0 2p(3) 0 1 1 0 0 1 0 0
––––––––––––––––––––––––– +x0a 1 0 1 0
2p(4) 0 1 1 0 1 1 1 0 ––––––––––––––––––––––––
pAND CONTROL0UNIT
DATAPATH
(4)
1 1 0 1 1 1 0 p(4) 0 1 1 0 1 1 1 0
======================== =======================
 How would the 8085 program look like for
multiplication
70

LXI H 2000 DAD D

MOV E, M LB1: DCR C
INX H JNZ LB2
MOV A, M LXI D 2003
LXI H 0000 MOV A, H
MOV D, H STAX D
MVI C 08 INX D
LB2: DAD H MOV A, L
RAL STAX D
JNC LB1 HLT
DATAPATH AND CONTROL UNIT
 Basic Hardware Multipliers
ref : Behrooz Perhami
71 Shift

Multiplier x

(j)
Doublewidth partial product p

Shift

Multiplicand a
0
k xj
0 1
Mux
xj a k

Adder
cout
k
Fig. 9.4 Hardware realization of the sequential multiplication algorithm with
additions and right shifts.
DATAPATH AND CONTROL UNIT
 72

Bs

Register B Sequence Counter SC

Complementer and
Parallel Adder

As Qs

E Register A Register Q Qn

DATAPATH AND CONTROL UNIT

 73

DATAPATH AND CONTROL UNIT

 Hardware implementation
(Ref: Morris Mano)
74

DATAPATH AND CONTROL UNIT

 Signed Magnitude Multiplication
(Ref: Morris Mano)
75

DATAPATH AND CONTROL UNIT

 76

DATAPATH AND CONTROL UNIT

Time Complexity of Programmed Multiplication
ref : Behrooz Perhami
77

Assume k-bit words

k iterations of the main loop

6-7 instructions per iteration, depending on the multiplier bit

Thus, 6k + 3 to 7k + 3 machine instructions,

ignoring operand loads and result store

k = 32 implies 200+ instructions on average

This is too slow for many modern applications!

Microprogrammed multiply would be somewhat better

DATAPATH AND CONTROL UNIT

 Hardware requirement (Booth’s Algo)
(Ref: Morris Mano)
78

DATAPATH AND CONTROL UNIT

 Booth’s Multiplier
79

DATAPATH AND CONTROL UNIT

 Booths Multiplication Algorithm
80

 The multiplicand and multiplier are placed in the m and Q

registers respectively.
 A 1 bit register is placed logically to the right of the LSB (least
significant bit) Q0 of Q register. This is denoted by Q-1.
 A and Q-1 are initially set to 0. Control logic checks the two bits
Q0 and Q-1.
 If the two bits are same (00 or 11) then all of the bits of A, Q, Q-1
are shifted 1 bit to the right.
 If they are not the same and if the combination is 10 then the
multiplicand is subtracted from A and if the combination is 01
then the multiplicand is added with A.

DATAPATH AND CONTROL UNIT

 Booths Multiplication Algorithm
81

In both the cases results are stored in A, and after the
addition or subtraction operation, A, Q, Q-1 are right
shifted.
The shifting is the arithmetic right shift operation where
the left most bit namely, An-1 is not only shifted into An-2
but also remains in An-1.
This is to preserve the sign of the number in A and Q. The
result of the multiplication will appear in the A and Q.

DATAPATH AND CONTROL UNIT

 82

DATAPATH AND CONTROL UNIT

 Number of Partial Products
83

Examining 2 or more bits of multiplier at a time

Requires generating A (multiplicand), 2A, 3A
Reduces number of partial products to n/2 - each step
more complex
Several algorithm which do not increase complexity
proposed - one is Booth's algorithm
Fewer partial products generated for groups of
consecutive 0’s and 1’s

DATAPATH AND CONTROL UNIT

 Binary Division
84

More complex than multiplication

Negative numbers are really bad!
Based on long division method

DATAPATH AND CONTROL UNIT

 Example -1
85

 Divisor B = 10001, 2’s comp of B = 01111

 Dividend A = 0111000000, Let quotient be Q

 B= 10001 A= 0111000000
 B’+1 =01111 01110 A<B, hence shift B to left
011100 A>B, subtract B and Q=1
Add - 01111
- 010110 A>B, subtract B and Q=11
- - 01111
448/17 - - 001010 A<B, hence shift B left and Q=110
Quotient= 26 - - -010100 A>B, subtract B and Q=1101
Remainder = 6
- - - 001111
- - - 0000110 Remainder < B; Q=11010

DATAPATH AND CONTROL UNIT

 Binary Division in Computers
86

Instead of shifting the Divisor to the right, shift the

Dividend (A) and quotient (Q) (Partial remainder) one bit
left.
Subtraction is performed by adding 2’s Complement of
Divisor (B) to A.
Division Overflow Problems……

DATAPATH AND CONTROL UNIT

 Signed Binary Division
87

DATAPATH AND CONTROL UNIT

 Signed binary division
88

If E = 1, then A>=B. A quotient bit Qn =1 is inserted and

the ‘partial remainder’ is shifted one bit left (SHL).
If E = 0, then A<B. The quotient bit remains 0 (inserted
during the SHL).
The value of B is then added to restore the partial
remainder in A to its previous value. The Partial
remainder is shifted one bit left.
The process is then repeated again until the SC counter
does not become zero.

DATAPATH AND CONTROL UNIT

 Signed binary division
89

Sign of the Quotient

If the sign of both dividend and divisor is the same - then
sign of the quotient is Positive
If the sign of divisor is different from dividend – then the
sign of the quotient will be Negative

Sign of the Remainder

The sign of the remainder will always be the same as that
of the dividend.

DATAPATH AND CONTROL UNIT

 Overflow in Division
90

The size of every register in a processor is fixed hence

size of register (Q) storing the quotient too is finite,

Normally occurs when the dividend, A >= 2n bits and the

divisor is B=<n bits
OR
Divide by zero, i.e., when B = 0.

A divide overflow (DVF) condition takes place if the higher

order half bits of the dividend constitute a number greater than
or equal to the divisor

DATAPATH AND CONTROL UNIT

 Handling the Divide Overflow (DVF)
91

Provision of a Special Flip-flop DVF. If set, DVF

occurred
1. IF DVF = 1, STOP computing; Write DIVIDE ERROR
2. IF DVF =1, Let the programmer take care of Overflow
by scaling or any other method.
3. Generate an Interrupt when DVF =1, suspend current
program and take corrective action.
Best way
Use floating point numbers for arithmetic
operations

DATAPATH AND CONTROL UNIT

 92

DATAPATH AND CONTROL UNIT

 Hardware required
93

B Register Sequence Counter (SC)

No, decrement
Is = 0
Complementer and
parallel Adder

Yes, STOP

Qn =E

E A Register Q Register

DATAPATH AND CONTROL UNIT

 FP Arithmetic algorithms
94

Reference: PPT by Eduardo Sanchez

DATAPATH AND CONTROL UNIT

 Floating point addition and subtraction
95

Check for zeros

Equalize the exponents
Align the mantissas (significands)
Add or subtract the mantissas
Normalize the mantissa
 Let the FP numbers be A and B and the operation A+B or A-B is to be
performed
Sign field Exponent Mantissa
field field
As a A
Bs b B

DATAPATH AND CONTROL UNIT

 Floating point addition and subtraction
96

If either or both of the operands is/are zero, it is to be

checked at this stage only to avoid normalization
problems later.
The addition and subtraction of the mantissa is the
same as that for fixed point numbers.
When the mantissas are added and a overflow occurs:-
 Overflow is transferred to FF ‘E’.
 If E is equal to 1, the bit is transferred to A 1 and all other bits are
shifted to right.
 The exponent must be shifted to maintain the correct number.

DATAPATH AND CONTROL UNIT

 Floating point addition and subtraction
97

When mantissas are subtracted:-

 The result may be a zero, the entire result (in AC) becomes zero.
 The mantissa has a underflow then the mantissa is shifted left
until A1 does not become a 1 and for every left shift the exponent
is decremented by one.

DATAPATH AND CONTROL UNIT

 Flow for FP Addition / Subtraction
98

DATAPATH AND CONTROL UNIT

 Floating point addition and subtraction
99

Flowchart for FP addition and subtraction

Reference : Morris Mano 3rd Edition

DATAPATH AND CONTROL UNIT

 FP Multiplication algorithm
100

DATAPATH AND CONTROL UNIT

 FP Multiplication algorithm
101

Reference: PPT by Eduardo Sanchez

DATAPATH AND CONTROL UNIT

 Example of FP Multiplication
102

DATAPATH AND CONTROL UNIT

 Example of FP Multiplication
103

DATAPATH AND CONTROL UNIT

 Example of FP Multiplication
104

DATAPATH AND CONTROL UNIT

 Example of FP Multiplication
105

DATAPATH AND CONTROL UNIT

 FP Multiplication Flow Chart
106

DATAPATH AND CONTROL UNIT