16nm Complex ASIC Physical design

and design for Test for

networking/Consumer IPs/blocks.

B. Tech. (EC) Semester VIII - Industrial Training

April 2025
Table of Content
• Basics of Linux
• Perl Scripting
• Verilog
• Design for testability
• Conclusion

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Motivation
This project is driven by the goal of building a solid
foundation in VLSI design through practical
experience with Linux, Perl, and Verilog, while also
exploring advanced 16nm ASIC physical design and
DFT. It aims to bridge academic concepts with real-
world semiconductor practices, enhancing skills in
automation, digital design, and testability for
industry-ready chip development.

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Activity 1: Basic Introduction of Linux
What is Linux ?
 Linux is a Operating System. It is similar to Unix, and
it is built upon the Linux Kernel.
 Linux is an open-source operating system.
 It is written in C & C++ languages.

Why Linux ?
 Linux is free to use for everyone.
 Linux is more flexible.
 Linux is more secure.
 It support CLI and GUI modes.
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Basic Commands
 File Management related :- ls,
cat,wc,echo,touch,cp,mv,rm etc
 Directory Management related :- pwd,mkdir, rmdir etc
 File Permission / Access Mode related :- chmod
(numeric, symbolic) etc
 User related :- su,passwd,useradd,whoami etc
 Environment Variable related :- cal, date etc
 General commands :- head, tail etc

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Activity 2: Perl Scripting
What is Perl?
 Perl is a high-level, general-purpose programming
language.
 It is used for scripting, automation, and handling
complex text processing tasks.
Why Perl ?
 It support for regular expressions and extensive
module library, also offers exceptional flexibility and
efficiency in handling text and data.
• Perl Match - m
• Perl Substitute - s
• Perl Transliterate - tr 6
Perl Variable
Data type/variable

Scaler array hashe

s s s
“dollar” sign ($) “at” sign (@) “modulo” sign (%)
It should be It will store Without
either a ordered lists remembering
number, a index, directly
of scalars.
string, or a store values with
reference Contain keys for large
Contain one more than number of index.
value at a time one.(set of Contain more
ordered than one.(set of
value) unordered value) 7
Activity 3: Verilog
 Verilog is a hardware description language (HDL).
 It is a language used for describing a digital system like
a network switch or a microprocessor or a memory or a
flip−flop.
 By using a HDL we can describe any digital hardware at
any level.
 Verilog supports a design at many levels of abstraction.
The major three are :
• Behavioral level
• Register-transfer level
• Gate level
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Activity 4: Design for Testibility
What is DFT?
Design for Testability (DFT) is a set of design techniques
used during the hardware design process (especially digital
circuits and ICs) to make sure the final chip or system can
be easily and thoroughly tested after manufacturing.
Why DFT?
Ensures high Fault Coverage
Efficient defect diagnosis and isolation
Reduced manufacturing test time
Enhanced yield and reliability.

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Fault Models
Here are some basic types of fault models:
1. Stuck at Faults
2. Bridging Faults
3. Transition Faults
4. Delay Faults

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Ad-Hoc Approach
Test point insertion:
Control Point Insertion Observation
Point Insertion

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Structuted Approach
Example for structure approach:
Assume that a stuck-at fault f in the
combinational logic requires the
primary input X3, flip-flop FF2, and
flip-flop FF3 to be set to 1 and 0
respectively, to capture the fault
effect into FF1.
From this example, we understood
that main difficulty in testing a
sequential circuit stems from the
fact that it is difficult to control and
observe the internal state of the
circuit.
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Scan cell design
Muxed-D scan cell
Structure: Contains a D flip-flop
and a multiplexer controlled by SE .
Capture Mode: When SE = 0, the
data input (DI) is captured into the
D flip-flop on a rising clock edge.
Shift Mode: When SE = 1, the scan
input (SI) shifts new data into the D
flip-flop while its current content
shifts out.

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Scan cell design
Clocked scan cell
Utilizes two independent clocks —
Data Clock (DCK) and Shift Clock
(SCK).
Normal/Capture Mode: DCK
captures data from the data input
(DI) into the clocked-scan cell.
Shift Mode: SCK shifts new data
from the scan input (SI) into the
clocked-scan cell while shifting out
the existing content.

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Scan cell design
LSSD scan cell
Designed for level-sensitive, latch-based
designs.
Contains two latches — Master D latch (L1) and
Slave D latch (L2).
Clock Functions:
Clock C → Captures functional data.
Clock A → Captures scan data.
Clock B → Transfers data from L1 to L2.
Capture Mode → Uses Clock C (for L1) and
Clock B (for L2) to output system data onto +L2.
Shift Mode (Scan Mode) → Uses Clock A to load
scan data into Latch L1, and Clock B transfers
this scan data from L1 to +L2, which drives the 15
Scan Architecture
Full Scan Design:
Muxed-D full scan design Clocked Full
scan design

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Scan Architecture
Full Scan Design:
LSSD full scan design

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Scan Architecture
Partial Scan design:
• Partial Scan is a testability technique where only a subset
of flip-flops is included in the scan chain, unlike Full
Scan, where all sequential elements are included.
• The three main techniques used in Partial Scan are:
1. Functional Approach
2. Pipelined or Feed-Forward Partial Scan
3. Balanced Partial Scan

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Functional Partitioning Approach:
Divides the circuit into:
Data Path Portion: Performance-critical; storage elements
here are often not replaced with scan cells to avoid delays.
Control Portion: Less timing-sensitive; storage elements
here can be replaced with scan cells.
Advantage: Balances fault coverage improvement while
minimizing performance degradation.

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Pipelined or feed-forward partial-scan design
Focuses on eliminating sequential feedback loops by
selectively replacing specific storage elements with scan
cells.
The goal is to create a feedback-free sequential circuit
for simpler Automatic Test Pattern Generation (ATPG).

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Balanced Partial-Scan Design
Targets a specific sequential depth (e.g., 3 to 5 clock
cycles).
In this approach, additional vertices are removed from
the structure graph by replacing their corresponding
storage elements with scan cells so the target sequential
depth is met.

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 Conclusion
ASIC design focuses on reducing cost and size by integrating
circuit components into a single chip, with increasing gate
densities driving the need for precision at each design stage.
Synthesis plays a key role by converting RTL code into a gate-
level netlist. As technology scales down, the risk of defects
increases, making Design for Testability (DFT) essential. DFT
adds test logic and pins to improve chip controllability and
observability. Scan insertion, the first DFT step, introduces scan
chains and generates pre- and post-DRC reports along with scan
configuration details. The resulting netlist is used for ATPG.
Knowledge of scripting languages like Shell and Perl, along with
Linux proficiency, supports efficient tool usage. The training
provided in-depth understanding of the ASIC flow and DFT, along
with valuable scripting skills.
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References
BOOKS:
[1] Design For Testability: VLSI test principles And Architecture. Laung- Terng
Wang
[2] Verilog HDL: A guide to Digital Design and Synthesis. Samir Palnitkar
WEB RESOURCES:
[1] Linux commands
www.javatpoint.com/linux-commands
[2] Shell Scripting
www.geeksforgeeks.org/introduction-linux-shell-shell-scripting/
[3] Perl Scripting
www.geeksforgeeks.org/perl-tutorial-learn-perl-with-examples/
[4] DFT Basics https://youtube.com/playlist?
list=PLZjlBaHNchvOFBWBAtAP9exwQgYpKqsO4&si=eG mjvNY_-sYakG-A
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Q&A