Instruction Set of 8086

Microprocessor

1
Assignment of codes to Registers

2
Types of instruction set of 8086
microprocessor
(1). Data Copy/Transfer instructions.

(2). Arithmetic & Logical instructions.

(3). Branch instructions.

(4). Loop instructions.

(5). Machine Control instructions.

(6). Flag Manipulation instructions.

(7). Shift & Rotate instructions.

(8). String instructions.

3
(1). Data copy/transfer instructions.

 (1). MOV Destination, Source;

 There will be transfer of data from source to destination.
 Source can be register, memory location or immediate

data.
 Destination can be register or memory operand.
 Both Source and Destination cannot be memory location

or segment registers at the same time.

 E.g.
 (1). MOV CX, 037A H;
 (2). MOV AL, BL;
 (3). MOV BX, [0301 H]; 4
BEFORE AFTER
EXECUTION EXECUTION
AX 2000H MOV BX 2000H
BX,AX;

BEFORE AFTER
EXECUTION EXECUTION
A AL A AL
H H
B BL MOV B BL
H
40
CL,M; H
40
C CL C CL 40
H H
D D D D
H L H L 5
Stack Pointer
 It is a 16-bit register, contains the address of the data
item currently on top of the stack.

 Stack operation includes pushing (providing) data on to

the stack and popping (taking)data from the stack.

 Pushing operation decrements stack pointer and

Popping operation increments stack pointer. i.e. there
is a last in first out (LIFO) operation.

6
(1). Data copy/transfer instructions.

 (2). Push Source;

 Source can be register, segment register or memory.
 This instruction pushes the contents of specified source on to
the stack.
 In this stack pointer is decremented by 2.
 The higher byte data is pushed first (SP-1).
 Then lower byte data is pushed (SP-2).

 E.g.:
 (1). PUSH AX;
 (2). PUSH DS;
 (3). PUSH [5000H]; 7
 INITIAL POSITION

(1) STACK
POINTER
DECREMENTS SP & STORES HIGHER
BYTE

(2) STACK POINTER

HIGHER BYTE

DECREMENTS SP & STORES LOWER

BYTE
(3) STACK
POINTER LOWER BYTE
HIGHER BYTE

8
 BEFORE EXECUTION
SP 2002H
2000H
BH BL
2001H
CH 10 CL 50
DH DL 2002H

PUSH CX
AFTER
50
EXECUTION
SP 2000H 2000H
BH BL
2001H 10
CH 10 CL 50

DH DL 2002H

9
(1). Data copy/transfer instructions.

 (3). POP Destination;

 Destination can be register, segment register or memory.
 This instruction pops (takes) the contents of specified
destination.
 In this stack pointer is incremented by 2.
 The lower byte data is popped first (SP+1).
 Then higher byte data is popped (SP+2).

 E.g.
 (1). POP AX;
 (2). POP DS;
 (3). POP [5000H]; 10
 INITIAL POSITION AND READS LOWER
BYTE
(1) STACK
POINTER LOWER BYTE

INCREMENTS SP & READS HIGHER

BYTE
LOWER BYTE
(2) STACK POINTER
HIGHER BYTE

INCREMENTS SP

LOWER BYTE
HIGHER BYTE

(3) STACK
POINTER
11
 BEFORE
EXECUTION
2000H30
S 2000H
P 2001H50
B B
H L 2002H

POP BX
AFTER
EXECUTION 2000H30
SP 2002H 2001H50
B 5 B 3 2002H
H 0 L 0 12
(1). Data copy/transfer instructions.

 (4). XCHG Destination, source;

• This instruction exchanges contents of Source with
destination.

• It cannot exchange two memory locations directly.

•The contents of AL are exchanged with BL.

•The contents of AH are exchanged with BH.

•E.g.
(1). XCHG BX, AX;
(2). XCHG [5000H],AX;
13
BEFORE AFTER EXECUTION
EXECUTION
A 20 AL 40 AH 70 AL 80
H

B 70 BL 80 BH 20 BL 40
H

XCHG
AX,BX; 14
(1). Data copy/transfer instructions.

 (5). IN AL/AX, 8-bit/16-bit port

address

 It reads from the specified port address.

 It copies data to accumulator from a port with 8-

bit or 16-bit address.

 DX is the only register is allowed to carry port

address.
 E.g.

(1). IN AL, 80H;

(2). IN AX,DX; //DX contains address of 16-bit port.
15
 BEFORE EXECUTION

PORT 10 AL
80H

IN
AL,80H;
AFTER EXECUTION

PORT 10 AL 10
80H
16
(1). Data copy/transfer instructions.

 (6). OUT 8-bit/16-bit port address,

AL/AX;
 It writes to the specified port address.
 It copies contents of accumulator to the port with

8-bit or 16-bit address.

 DX is the only register is allowed to carry port

address.
 E.g.

(1). OUT 80H,AL;

(2). OUT DX,AX; //DX contains address of 16-bit
port. 17
 BEFORE EXECUTION

PORT 10 AL 40
50H

OUT
50H,AL;
AFTER EXECUTION

PORT 40 AL 40
50H
18
(1). Data copy/transfer instructions.

 (7). XLAT;
Mnemonic Meaning Format Operation Flags
XLAT Translate XLAT ((AL)+(BX)+(DS)0)  (AL) None

 Also known as translate instruction.

 It is used to find out codes in case of code
conversion.
 i.e. it translates code of the key pressed to the
corresponding 7-segment code.
 After execution this instruction contents of AL
register always gets replaced.
 E.g. XLAT;
19
(1). Data copy/transfer instructions.

Mnemo Meaning Format Operation Flags

nic affected
LEA Load LEA Reg16,EA EA  (Reg16) None
Effective
Address
LDS Load LDS Reg16,MEM32 (MEM32)  (Reg16) None
Register
And DS (Mem32+2)  (DS)

LES Load LES Reg16,MEM32 (MEM32)  (Reg16) None

Register
and ES (Mem32+2)  (DS)

20
(1). Data copy/transfer instructions.

 (8). LEA 16-bit register

(source), address (dest.);
 LEA Also known as Load Effective Address
(LEA).
 It loads effective address formed by the

destination into the source register.

 E.g.
(1). LEA BX,Address;
(2). LEA SI,Address[BX]; 21
(1). Data copy/transfer instructions.

 (9).LDS 16-bit register (source),

address (dest.);
 (10). LES 16-bit register (source),

address (dest.);
 LDS Also known as Load Data Segment (LDS).
 LES Also known as Load Extra Segment (LES).
 It loads the contents of DS (Data Segment) or ES (Extra
Segment) & contents of the destination to the contents of
source register.

 E.g.
(1). LDS BX,5000H;
(2). LES BX,5000H; 22
 (1). LDS BX,5000H;
(2). LES BX,5000H;

15 0 7 0
BX 20 10 10 5000H
20
5001H
30 5002H
DS/ 40 30
ES 40 5003H

23
(1). Data copy/transfer instructions.

 (11). LAHF:- This instruction loads the AH register

from the contents of lower byte of the flag register.
 This command is used to observe the status of the
all conditional flags of flag register.
 E.g. LAHF;

 (12). SAHF:- This instruction sets or resets all

conditional flags of flag register with respect to the
corresponding bit positions.
 If bit position in AH is 1 then related flag is set
otherwise flag will be reset.
 E.g. SAHF;
24
(1). Data copy/transfer instructions.

 (13). PUSH F:- This instruction decrements

the stack pointer by 2.
 It copies contents of flag register to the

memory location pointed by stack pointer.

 E.g. PUSH F;

 (14). POP F:- This instruction increments the

stack pointer by 2.
 It copies contents of memory location pointed

by stack pointer to the flag register.

 E.g. POP F;

25
 (2). Arithmetic
Instructions
 These instructions perform the operations like:

 Addition,
 Subtraction,
 Increment,
 Decrement.

26
(2). Arithmetic
Instructions
 (1). ADD destination, source;

 This instruction adds the contents of source

operand with the contents of destination operand.
 The source may be immediate data, memory
location or register.
 The destination may be memory location or
register.
 The result is stored in destination operand.
 AX is the default destination register.

 E.g. (1). ADD AX,2020H;

(2). ADD AX,BX;
27
BEFORE EXECUTION AFTER EXECUTION
A 1 A 1 ADD A 3 A 3
H 0 L 0 H 0 L 0
AX,2020H
1010
+2020
3030

BEFORE EXECUTION AFTER EXECUTION

A 1 A 1 A 3 A 3
H 0 L 0 ADD H 0 L 0
B 2 B 2 AX,BX B 2 B 2
H 0 L 0 H 0 L 0
2050 28
(2). Arithmetic
Instructions
 (2). ADC destination, source
 This instruction adds the contents of source
operand with the contents of destination operand
with carry flag bit.
 The source may be immediate data, memory
location or register.
 The destination may be memory location or register.
 The result is stored in destination operand.
 AX is the default destination register.

 E.g. (1). ADC AX,2020H;

(2). ADC AX,BX;
29
BEFORE EXECUTION AFTER EXECUTION
ADC
C 1
Y
AX,2020H
A 1 A 1 A 3 A 3
H 0 L 0 1010 H 0 L 1
+2020

BEFORE EXECUTION AFTER EXECUTION

3030+1=30
C 1 31
Y
A 1 A 1 A 3 A 3
H 0 L 0 ADC H 0 L 1
B 2 B 2 AX,BX B 2 B 2
H 0 L 0 H 0 L 0
2050 30
(2). Arithmetic
Instructions
 (3). INC source
 This instruction increases the contents of
source operand by 1.
 The source may be memory location or
register.
 The source can not be immediate data.
 The result is stored in the same place.

 E.g. (1). INC AX;

(2). INC [5000H]; 31
BEFORE EXECUTION AFTER EXECUTION

AH 10 AL 10 INC AH 10 AL 11

AX

BEFORE EXECUTION AFTER EXECUTION

5000 1010 INC 5000

H
1011
H
[5000H] 32
(2). Arithmetic
Instructions
 (4). DEC source;
 This instruction decreases the contents of
source operand by 1.
 The source may be memory location or
register.
 The source can not be immediate data.
 The result is stored in the same place.

 E.g. (1). DEC AX;

(2). DEC [5000H]; 33
BEFORE EXECUTION AFTER EXECUTION

AH 10 AL 10 DEC AH 10 AL 0F

AX

BEFORE EXECUTION AFTER EXECUTION

5000 1010 DEC 5000

H
100F
H
[5000H] 34
(2). Arithmetic
Instructions
 (5). SUB destination, source;
 This instruction subtracts the contents of
source operand from contents of destination.
 The source may be immediate data, memory
location or register.
 The destination may be memory location or
register.
 The result is stored in the destination place.

 E.g. (1). SUB AX,1000H;

(2). SUB AX,BX;
35
 BEFORE EXECUTION AFTER EXECUTION

A 20 AL 00 SUB A 10 AL 00
H H
AX,1000H
2000
-1000
=1000

BEFORE EXECUTION AFTER EXECUTION

A 20 AL 00 A 10 AL 00
H SUB H
B 10 BL 00 AX,BX B 10 BL 00
H H 36
(2). Arithmetic
Instructions
 (6). SBB destination, source;
 Also known as Subtract with Borrow.
 This instruction subtracts the contents of source
operand & borrow from contents of destination
operand.
 The source may be immediate data, memory
location or register.
 The destination may be memory location or register.
 The result is stored in the destination place.

 E.g. (1). SBB AX,1000H;

(2). SBB AX,BX;
37
BEFORE EXECUTION AFTER EXECUTION
SBB
B 1
AX,1000H
A 2 A 2 A 1 A 1
H 0 L 0 2020 H 0 L 9
- 1000
1020-
BEFORE EXECUTION 1=1019 AFTER EXECUTION
B 1
A 2 A 2 A 1 A 1
H 0 L 0 SBB H 0 L 9
B 1 B 1 AX,BX B 1 B 1
H 0 L 0 H 0 L 0
2050 38
(2). Arithmetic
Instructions
 (7). CMP destination, source
 Also known as Compare.
 This instruction compares the contents of source
operand with the contents of destination
operands.
 The source may be immediate data, memory
location or register.
 The destination may be memory location or
register.
 Then resulting carry & zero flag will be set or reset.

 E.g. (1). CMP AX,1000H;

(2). CMP AX,BX;
39
 D=S:
BEFORE EXECUTIONCY=0,Z=1 AFTER EXECUTION
D>S:
CY=0,Z=0
AH 10 AL 00 D<S:
CMP CY 0 Z 1
BH 10 BL 00 CY=1,Z=0
AX,BX
BEFORE EXECUTION AFTER EXECUTION
AH 10 AL 00
CMP AX,BX CY 0 Z 0
BH 00 BL 10

BEFORE EXECUTION AFTER EXECUTION

AH 10 AL 00
CMP CY 1 Z 0
BH 20 BL 00
AX,BXH
40
(2). Arithmetic
Instructions
(8). AAA
 Also known as ASCII Adjust After Addition.
 This instruction is executed after ADD instruction.

(1). IF lower bits of AL<=09 then,

 Higher bits of AL should loaded with zeroes.

 There should be no change in lower bits of AL.

 AH also must be cleared (AH=0000 0000).

(2). IF lower bits of AL>09 then,

 Bits of AL must be incremented by 06 (i.e. AL+0110).

 Bits of AH must be incremented by 01 (i.e. AH+0001).

 Then higher bits of AL should be loaded with 0000.

 E.g. (1). AAA;

41
 (1). FOR
AL AL<=09H
6 7 BEFORE
Hb Lb EXECUTION

AL 0 7 AFTER
EXECUTION
Hb Lb
Hb=Higher
bits,
(1). FOR Lb=Lower bits.
AL>09H
6 A
AL BEFORE
Hb Lb EXECUTION
(A)1010
HB LB
+(06)0110=0001
AL 0
0000 0 AFTER
Hb Lb EXECUTION

42
(2). Arithmetic
Instructions
(9). AAS
 Also known as ASCII Adjust After Subtraction.
 This instruction is executed after SUB instruction.

(1). IF lower bits of AL<=09 then,

 Higher bits of AL should loaded with zeroes.

 There should be no change in lower bits of AL.

 AH also must be cleared (AH=0000 0000).

(2). IF lower bits of AL>09 then,

 Bits of AL must be decremented by 06 (i.e. AL-0110).

 Bits of AH must be decremented by 01 (i.e. AH-0001).

 Then higher bits of AL should be loaded with 0000.

 E.g. (1). AAS;

43
 (1). FOR
AL AL<=09H
6 7 BEFORE
Hb Lb EXECUTION

AL 0 7 AFTER
EXECUTION
Hb Lb
Hb=Higher
bits,
(1). FOR Lb=Lower bits.
AL>09H
6 A
AL BEFORE
Hb Lb EXECUTION
(A)1010 -
Hb Lb
(06)0110=0000 0100
AL 0 4 AFTER
Hb Lb EXECUTION

44
(2). Arithmetic
Instructions
 (10). AAM
 Also known as ASCII Adjust After Multiplication.
 This instruction is executed after MUL
instruction.
 Then AH=AL/10 & AL=Remainder.

 E.g. MOV AL,04 // AL=04

 MOV BL,09 // BL=09
 MUL BL // 04*09=36 (i.e. BL*AL)
 AAM // AH=03 & AL=06

 E.g. (1). AAM;

45
(2). Arithmetic
Instructions
(11). AAD;

 Also known as ASCII Adjust before

Division.
 Then AL=AH*10 +AL & AH=0.

 E.g. MOV AX, 0105 // AH=01, AL=05

 AAD // AL=15 (i.e.0FH) &
AH=00

 E.g. (1). AAD;

46
(2). Arithmetic
Instructions
 (12). DAA;
 Decimal Adjust Accumulator.
 IF lower bits of AL>09.
 Then AL=AL+06.

 E.g. MOV AL,53H //AL=53H

 MOV CL,29H //CL=29H
 ADD AL,CL // AL=7CH (i.e. 12=C) & C>9.
 DAA // AL=7C+06=82H. (i.e. 0111 1100 +
0000 0110)=1000 0010 7 C +0 6 = 8 2


 E.g. (1). DAA;

47
(2). Arithmetic
Instructions
 (13). DAS
 Decimal Adjust after Subtraction.
 IF lower bits of AL>09.
 Then AL=AL-06.

 E.g. MOV AL,30H // AL=30H

 MOV CL,20H // CL=20H
 SUB AL,CL // AL=0AH (i.e. A=10) & C=10>9.
 DAS // AL=0A-06=04H. (i.e. 0000 1010 -
0000 0110)=0000 0100 0 A - 0 6= 0 4


 E.g. (1). DAS;

48
(2). Arithmetic
Instructions
 (14). MUL operand
 Unsigned Multiplication.
 Operand contents are positively signed.
 Operand may be general purpose register or memory
location.
 Result is stored in accumulator (AX).
 when operand is a byte:
◦ AX = AL * operand.
 when operand is a word:
◦ (DX AX) = AX * operand.

 E.g. (1). MUL BH // AX= AL*BH; // (+3) * (+4) = +12.

 (2). MUL CX // AX=AX*CX;

49
(2). Arithmetic
Instructions
 (15). IMUL operand
 Signed Multiplication.
 Operand contents are negatively signed.
 Operand may be general purpose register, memory
location or index register.
 If operand is of 8-bit then multiply it with contents of AL.
 If operand is of 16-bit then multiply it with contents of AX.
 Result is stored in accumulator (AX).

 E.g. (1). IMUL BH // AX= AL*BH; // (-3) * (-4) = 12.

 (2). IMUL CX // AX=AX*CX;

50
(2). Arithmetic
Instructions
 (16). DIV operand
 Unsigned Division.
 Operand may be register or memory.
 Operand contents are positively signed.
 Operand may be general purpose register or memory
location.
 AL=AX/Operand (8-bit/16-bit) & AH=Remainder.

 E.g. MOV AX, 0203 // AX=0203

 MOV BL, 04 // BL=04
 DIV BL // AX=0203/04=80 (i.e. AL=50 &
AH=00) 51
(2). Arithmetic
Instructions
 (17). IDIV operand
 Signed Division.
 Operand may be register or memory.
 Operand contents are negatively signed.
 Operand may be general purpose register or memory
location.
 when operand is a byte:
◦ AL = AX / operand
◦ AH = remainder (modulus)
 when operand is a word:
◦ AX = (DX AX) / operand
◦ DX = remainder (modulus)

 E.g. MOV AX, -0203 // AX=-0203

 MOV BL, 04 // BL=04
 DIV BL // AL=-0203/04=-50 (i.e. AL=-80 & AH=00)
52
(3). Logical Instructions
(1). AND destination, source
 Destination operand may be register, memory
location.
 Source operand may be register, immediate data
or memory location.
 Result is stored in destination operand.

 E.g. MOV AX, 3F0FH // AX=3F0FH

 MOV BX, 0008H // BX=0008H
AND AX,BX // AX=0008H
53
Follow the rules as given below:-
(1). 1 AND 1 = 1
(2). 1 AND 0 = 0
(3). 0 AND 1 = 0
(4). 0 AND 0 = 0

 3F0FH= 0011 1111 0000 1111

 0008H=0000 0000 0000 1000
 0000 0000 0000 1000
= 0008H
54
(3). Logical Instructions
(2). OR destination,source
 Destination operand may be register, memory
location.
 Source operand may be register, immediate
data or memory location.
 Result is stored in destination operand.

 E.g. MOV AX, 3F0FH // AX=3F0FH

 MOV BX, 0098H // BX=0098H
OR AX,BX // AX=3F9FH 55
Follow the rules as given below:-
(1). 1 OR 1 = 1
(2). 1 OR 0 = 1
(3). 0 OR 1 = 1
(4). 0 OR 0 = 0

 3F0FH= 0011 1111 0000 1111

 0098H=0000 0000 1001 1000
 0011 1111 1001 1111
= 3F9FH
56
(3). Logical Instructions
(3). NOT operand;
 Operand may be register, memory location.
 This instruction inverts (complements) the
contents of given operand.
 Result is stored in Accumulator (AX).

 E.g. MOV AX, 0200FH // AX=200FH

 NOT AX // AX=DFF0H
57
Follow the rules as given below:-
(1). 1 NOT = 0
(2). 0 NOT = 1

 200FH= 0010 0000 0000

1111
 1101 1111 1111
0000 = DFF0H

58
•
(3). Logical Instructions
 (4). TEST destination,source
 Both operands may be register, memory location or
immediate data.
 This instruction performs bit by bit logical AND
operation for flags only (i.e. only flags will be affected).
 If the corresponding 0th bit of result contains ‘1’ then
result will be non-zero & zero flag will be cleared/reset
(i.e. ZF=0).
 If the corresponding 0th bit of result contains ‘0’ then
result will be zero & zero flag will be set (i.e. ZF=1)..

 E.g. (1). TEST AX,BX

 (2). TEST [0500],06H

59
(3). Logical Instructions
(5).Shift and Rotate
Instructions
 SHL/SAL: shift logical left/shift arithmetic
left
 SHR: shift logical right
 SAR: shift arithmetic right
 ROL: rotate left
 ROR: rotate right
 RCL: rotate left through carry
 RCR: rotate right through carry

60
SHL Instruction
 The SHL (shift left) instruction performs a logical left shift on
the destination operand, filling the lowest bit with 0.

0
CF
• Operand types:
 SHL reg,imm8
 SHL mem,imm8
 SHL reg,CL
 SHL mem,CL
61
Fast Multiplication
 Shifting left 1 bit multiplies a number by 2

mov dl,5
Before: 00000101 =5
shl dl,1
0 0 0 0 1 0 1 0 = 10
After:
 Shifting left n bits multiplies the operand by 2n
◦ For example, 5 * 22 = 20
mov dl,5
shl dl,2 ; DL = 20

62
 Ex.; Multiply AX by 10

 SHL AX, 1
 MOV BX, AX
 MOV CL,2
 SHL AX,CL
 ADD AX, BX

63
SHR Instruction
 The SHR (shift right) instruction performs a logical right shift
on the destination operand. The highest bit position is filled
with a zero.
0
CF

 Shifting right n bits divides the operand by 2n

MOV DL,80
SHR DL,1 ; DL = 40
SHR DL,2 ; DL = 10
64
SAR Instruction
 SAR (shift arithmetic right) performs a right
arithmetic shift on the destination operand.

CF
 An arithmetic shift preserves the number's sign.

MOV DL,-80
SAR DL,1 ; DL = -40
SAR DL,2 ; DL = -10

65
(3). Logical Instructions
RCR
 Also known as Rotate Right through Carry.
 Each binary bit of the operand is rotated
towards right by one position through
Carry flag.
 Least Significant Bit (LSB) i.e. B0 is placed
in the Carry flag.
 Then carry flag bit is placed in the Most
Significant Bit (MSB) position B15.

66
 BEFORE EXECUTION

B B B B B B B B B B B B B B B B CF
1 1 0 1 0 0 1 0 0 0 0 1 0 0 0 1 0
15 7 0

AFTER EXECUTION

B B B B B B B B B B B B B B B B CF
0 1 1 0 1 0 0 1 0 0 0 0 1 0 0 0 1
15 7 0

67
(3). Logical Instructions
(6). RCL
 Also known as Rotate Left through Carry.
 Each binary bit of the operand is rotated

towards left by one position through

Carry flag.
 Least Significant Bit (LSB) of operand i.e.

B0 is placed in the B1.

 Then Most Significant Bit (MSB) of

operand is placed in carry flag bit.

68
 BEFORE EXECUTION

CF B B B B B B B B B B B B B B B B
0 1 0 0 1 0 0 1 0 0 0 0 1 0 0 0 1

AFTER EXECUTION

CF B B B B B B B B B B B B B B B B
1 0 0 1 0 0 1 0 0 0 0 1 0 0 0 1 0

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ROL Instruction
 ROL (rotate) shifts each bit to the left
 The highest bit is copied into both the Carry flag

and into the lowest bit

 No bits are lost

CF

MOV Al,11110000b
ROL Al,1 ; AL = 11100001b

MOV Dl,3Fh
ROL Dl,4 ; DL = F3h

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ROR Instruction
 ROR (rotate right) shifts each bit to the right
 The lowest bit is copied into both the Carry
flag and into the highest bit
 No bits are lost

CF

MOV AL,11110000b
ROR AL,1 ; AL = 01111000b

MOV DL,3Fh
ROR DL,4 ; DL = F3h

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String?

 An array of bytes or words

located in memory
 Supported String Operations

◦Copy (move, load)

◦Search (scan)
◦Store
◦Compare

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 String Instruction
Basics
 Source DS:SI, Destination ES:DI

◦ You must ensure DS and ES are correct

◦ You must ensure SI and DI are offsets into
DS and ES respectively

 Direction Flag (0 = Up, 1 = Down)

◦ CLD - Increment addresses (left to right)

◦ STD - Decrement addresses (right to left)
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String Instructions
Instruction prefixes

Prefix Used with Meaning

REP MOVS Repeat while not end of string

STOS CX ≠ 0

Repeat while not end of string

REPE/REPZ CMPS and strings are equal. CX ≠ 0
SCAS and ZF = 1

REPNE/ CMPS Repeat while not end of string

REPNZ and strings are not equal. CX ≠
SCAS
0 and ZF = 0
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Instructions

Mnemo- meaning format Operation Flags

Nic effect
-ed
MOVS Move string MOVSB/ ((ES)0+(DI))  ((DS)0+(SI)) none
DS:SI ES:DI MOVSW (SI)  (SI) ± 1 or 2
(DI)  (DI) ± 1 or 2

CMPS Compare CMPSB/ Set flags as per All

string CMPSW ((DS)0+(SI)) - ((ES)0+(DI)) status
DS:SI ES:DI (SI)  (SI) ± 1 or 2 flags
(DI)  (DI) ± 1 or 2

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 Mnemo- meaning format Operation
Nic
SCAS Scan string SCASB/ Set flags as per
AX – ES:DI SCASW (AL or AX) - ((ES)0+(DI))
(DI)  (DI) ± 1 or 2

LODS Load string LODSB/ (AL or AX)  ((DS)0+(SI))

DS:SI  AX LODSW (SI)  (SI) ± 1 or 2

STOS Store string STOSB/ ((ES)0+(DI))  (AL or A) ± 1 or 2

ES:DI  AX STOSW (DI)  (DI) ± 1 or 2

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(4). String Manipulation
Instructions
(1). REP

 Also known as Repeat instruction prefix.

 This instruction executed repeatedly until the
‘CX’ register becomes zero.
 When ‘CX’ becomes zero then program control
passes to next instruction.
 There are following sub types of ‘REP’
instruction,
 (i). REPE:- REPeat instruction while Equal.
 (ii). REPZ:- REPeat instruction while Zero.
 (iii). REPNE:- REPeat instruction while Not Equal.
 (iv). REPNZ:- REPeat instruction while Not Zero.
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(4). String Manipulation
Instructions
(2). CMPS

 Also known as Compare String Byte or String

Word.
 The length of the string must be stored in
register CX.
 If both the byte or word are equal then zero
flag will be set (i.e. ZF=1) otherwise it will be
reset (i.e. ZF=0).
 When zero flag will be set then ‘CX’=0.
 There are following sub types,
 (i). CMPSB:- Compare String Byte.
 (ii). CMPSW:- Compare String Word. 78
(5). Branching Instructions
(1). CALL
 Also known as unconditional call.
 Under unconditional call, the execution
control is transferred to the specified
location independent of any status or
condition.
 This instruction is used to call subroutine
from a main program.
 There are following sub types,
 (i). NEAR CALL:- It pushes only IP into the stack.
 (ii). FAR CALL:- It pushes IP & CS into the stack.
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(5). Branching Instructions
(2). JMP
 Also known as unconditional jump.
 Under unconditional jump, the execution control is
transferred to the specified location using 8-bit or 16-
bit displacement.
 There are following three formats of jump instruction,
8-bit
 (i). JMPDisplacement
16-bit Displacement (LB) 8-bit Displacement (UB)
 (ii). JMP
 (iii). JMP IP (LB) IP (UB) CS (LB) CS (UB)

80
Conditional Jump instructions

Conditional Jump instructions in 8086 are just 2 bytes long. 1-byte

opcode followed by 1-byte signed displacement (range of –128 to
+127).

Conditional Jump Instructions

Jumps based on Jumps based on

a single flag more than one flag

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Conditional Jump Instructions

Mnemonic : Jcc
Meaning : Conditional Jump
Format : Jcc operand
Operation : If condition is true jump to the address specified by operand.
Otherwise the next instruction is executed.
Flags affected : None

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TYPES

Mnemonic meaning condition

JA Above CF=0 and ZF=0

JB Above or Equal CF=0

JB Below CF=1

JBE Below or Equal CF=1 or ZF=1

JC Carry CF=1

JCXZ CX register is Zero (CF or ZF)=0

JE Equal ZF=1

JG Greater ZF=0 and SF=OF

JGE Greater or Equal SF=OF

JL Less (SF XOR OF) = 1

83
Mnemonic meaning condition

JLE Less or Equal ((SF XOR OF) or ZF) = 1

JNA Not Above CF =1 or Zf=1

JNAE Not Above nor Equal CF = 1

JNB Not Below CF = 0

JNBE Not Below nor Equal CF = 0 and ZF = 0

JNC Not Carry CF = 0

JNE Not Equal ZF = 0

JNG Not Greater ((SF XOR OF) or ZF)=1

JNGE Not Greater nor (SF XOR OF) = 1

Equal
JNL Not Less SF = OF

84
Mnemonic meaning condition
JNLE Not Less nor Equal ZF = 0 and SF = OF
JNO Not Overflow OF = 0
JNP Not Parity PF = 0
JNZ Not Zero ZF = 0
JNS Not Sign SF = 0
JO Overflow OF = 1
JP Parity PF = 1
JPE Parity Even PF = 1
JPO Parity Odd PF = 0
JS Sign SF = 1
JZ Zero ZF = 1

85
Jumps Based on a single flag
JZ r8 ;Jump if zero flag set to 1 (Jump if result is zero)
JNZ r8 ;Jump if Not Zero (Z flag = 0 i.e. result is nonzero)
JS r8 ;Jump if Sign flag set to 1 (result is negative)
JNS r8 ;Jump if Not Sign (result is positive)

JC r8 ;Jump if Carry flag set to 1

There is no jump
JNC r8 ;Jump if No Carry based on AC flag
JP r8 ;Jump if Parity flag set to 1 (Parity is even)
JNP r8 ;Jump if No Parity (Parity is odd)
JO r8 ;Jump if Overflow flag set to 1 (result is wrong)
JNO r8 ;Jump if No Overflow (result is correct)

86
JZ r8 ; JE (Jump if Equal) also means same.
JNZ r8 ; JNE (Jump if Not Equal) also means same.
JC r8 ;JB (Jump if below) and JNAE (Jump if Not
Above or Equal) also mean same.

JNC r8 ;JAE (Jump if Above or Equal) and JNB (Jump if

Not Above) also mean same.

JZ, JNZ, JC and JNC used after arithmetic operation

JE, JNE, JB, JNAE, JAE and JNB are used after a
compare operation.

JP r8 ; JPE (Jump if Parity Even) also means same.

JNP r8 ; JPO (Jump if Parity Odd) also means same.

87
(6). Flag Manipulation
Instructions
(1). CMC
 Also known as Complement Carry Flag.
 It inverts contents of carry flag.
 if CF = 1 then CF will be = 0.
 if CF = 0 then CF will be = 1.

 E.g. CMC

88
(6). Flag Manipulation
Instructions
(2). STC
 Also known as Set Carry Flag.
 It makes carry flag in set condition.
 After execution CF = 1.

 E.g. STC

89
(6). Flag Manipulation
Instructions
(3). CLI
 Also known as Clear Interrupt Flag.
 It makes interrupt flag in reset condition.
 After execution IF = 0.

 E.g. CLI

90
(6). Flag Manipulation
Instructions
(4). CLD
 Also known as Clear Direction Flag.
 It makes direction flag in reset condition.
 After execution DF = 0.

 E.g. CLD

91
(7). Machine Control
Instructions
(1). HLT
 Also known as Halt
 It makes the processor to be in stable

(do nothing) condition.

 E.g. HLT

92
(7). Machine Control
Instructions
(2). NOP
 Also known as No Operation.
 It tells about further there will be no

operation to be performed.

 E.g. NOP

93