SWITCH-LEVEL MODELING

In Part 1 of this book we explained digital design and simulation at a higher level of
abstraction such as gates, data flow, and behavior. However, in rare cases designers will
choose to design the leaf-level modules, using transistors. Verilog provides the ability to
design at a MOS-transistor level. Design at this level is becoming rare with the increasing
complexity of circuits (millions of transistors)and with the availability of sophisticated CAD
tools. Verilog HDL currently provides only digital design capability with logic values 0, 1, x, z,
and the drive strengths associated with them. There is no analog capability. Thus, in Verilog
HDL, transistors are also known switches that either conduct or are open. In this chapter we
discuss the basic principles of switch-level modeling. For most designers, it is adequate to
know only the basics. Detailed information on signal strengths and advanced net definitions
is provided in Appendix A, Strength Modeling and Advanced Net Definitions. Refer to the
Verilog HDL Language Reference Manual for complete details on switch-level modeling.
Learning Objectives

• Describe basic MOS switches nmos, pmos, and cmos.

• Understand modeling of bidirectional pass switches, power, and ground.
• Identify resistive MOS switches.
• Explain the method to specify delays on basic MOS switches and bidirectional
pass switches.
• Build basic switch-level circuits in Verilog, using available switches

11.1 Switch-Modeling Elements

Verilog provides various constructs to model switch-level circuits. Digital circuits
at MOS-transistor level are described using these elements.
11.1.1 MOS Switches

Two types of MOS switches can be defined with the keywords, nmos and pmos.//MOS switch keywords
nmos pmos Keyword nmos is used to model NMOS transistors; keyword pmos is used to model PMos
transistors. The symbols for nmos and pmos switches are shown in Figure 11-1.

In Verilog, nmos and pmos switches are instantiated as shown in Example 11-1.

nmos n1 (out, data, control); //instantiate a nmos switch

pmos p1(out, data, control); //instantiate a pmos switch

Since switches are Verilog primitives, like logic gates, the name of the instance isoptional. Therefore, it
is acceptable to instantiate a switch without assigning an instance name.
 nmos (out, data, control); //instantiate an nmos switch;no instance name
pmos (out, data, control); //instantiate a pmos switch;no instance name

Value of the out signal is determined from the values of data and control signals. Logic tables for out are
shown in Table 11-1. Some combinations of data and control signals cause the gates to output to either
a 1 or 0, or to an z value without a preference for either value. The symbol L stands for 0 or z; H stands
for1 or z.

Table 11-1 Logic Tables for NMOS and PMOS

Thus, the nmos switch conducts when its control signal is 1. If control signal is 0 , the output
assumes a high impedance value. Similarly, a pmos switch conducts if the control signal is o.
11.1.2 CMOS Switches
CMOS switches are declared with the keyword cmos. A cmos device can be modeled with a
nmos and a pmos device. The symbol for a cmos switch is shown in Figure 11-2.
A cmos switch is instantiated as shown in Example 11-2.
Example 11-2 Instantition of CMOS Switch
cmos c1(out, data, n control, p control);//instantiate cmos gate.
or
cmos (out, data, n control, p control); //no instance name given.
The ncontrol and pcontrol are normally complements of each other. When the ncontrol signal is 1 and
pcontrol signal is o, the switch conducts. If ncontrol signalis o and pcontrol is 1, the output of the switch
is high impedance value. The cmos gate is essentially a combination of two gates: one nmos and one
pmos. Thus the cmos instantiation shown above is equivalent to the following.
nmos (out, data, ncontrol); //instantiate a nmos switch
pmos (out, data, pcontrol); //instantiate a pmos switch
Since a cmos switch is derived from nmos and pmos switches, it is possible to derive the output
value from Table 11-1, given values of data, ncontrol, and pcontrol signals.

11.1.3 Bidirectional Switches

NMOS, PMOS and CMOS gates conduct from drain to source. It is important to have devices that
conduct in both directions. In such cases, signals on either sideof the device can be the driver signal.
Bidirectional switches are provided for this purpose. Three keywords are used to define bidirectional
switches: tran, tranif0 and tranif1.

tran tranifO tranif1

The tran switch acts as a buffer between the two signals inout1 and inout2. Either in out1 or inout2
can be the driver signal. The tranif0 switch connects the two signals inout1 and inout2 only if the
control signal is logical o. If the control signa lis a logical 1, the nondriver signal gets a high
impedance value z. The driver signal retains value from its driver. The tranif1 switch conducts if the
control signal is a logical 1. These switches are instantiated as shown in Example 11-3.
Example 11-3 Instantiation of Bidirectional Switches

tran t1(inout1, inout2); //instance name t1 is optional

tranif0 (inout1, inout2, control); //instance name is not specified
tranifl (inoutl, inout2, control); //instance name is not specified

Bidirectional switches are typically used to provide isolation between buses or signals.

11.1.4 Power and Ground

The power (Vdd, logic 1) and Ground (Vss, logic 0) sources are needed when transistor-level circuits
are designed. Power and ground sources are defined with keywords supply1 and supply0. Sources of
type supply1 are equivalent to Vdd in circuits and place a logical 1 on a net. Sources of the type
supply0 are equivalent to ground or Vss and place a logical o on a net. Both supply1 and supply0
place logical 1 and o continuously on nets throughout the simulation.
Sources rnmos
supply1 and supply0 are shown below.
rpmos //resistive nmos and pmos switches
rcmos //resistive cmos switch
rtran rtranif0 rtranifl //resistive bidirectional switches.

There are two main differences between regular switches and resistive switches their source-to-drain
impedances and the way they pass signal strengths. Refer to Appendix A, Strength Modeling and
Advanced Net Definitions for strength levels in Verilog. • Resistive devices have a high source-to-drain
impedance. Regular switches have a low source-to-drain impedance. Resistive switches reduce signal
The changes are shown below. Regular switches retain strength levels of signals from input to output.
The exception is that if the input is of strength supply, the output is of strength strong. Table 11-2 shows
the strength reduction due to resistive switches

11.1.6 Delay Specification on Switches

MOS and CMOS switches

Delays can be specified for signals that pass through these switch-level elements.Delays are
optional and appear immediately after the keyword for the switch. Delay specification is similar to
that discussed in Section 5.2.1, Rise, Fall, and Turnoff Delays. Zero, one, two or three delays can be
specified for switches according to Table 11-3.
Bidirectional pass switches Delay specification is interpreted slightly differently for bidirectional pass
switches. These switches do not delay signals passing through them. Instead, they have turn-on and
turn-off delays while switching. Zero, one, or two delays can be specified for bidirectional switches, as
shown in Table 11-4.
Specify blocks
Pin-to-pin delays and timing checks can also be specified for modules designed using switches. Pin-to-
pin timing is described, using specify blocks. Pin-to-pin delay specification is discussed in detail in
Chapter 10, Timing and Delays, and is identical for switch-level modules.
11.2 Examples
In this section, we discuss how to build practical digital circuits, using switch level
constructs.
11.2.1 CMOS Nor Gate
Though Verilog has a nor gate primitive, let us design our own nor gate, using CMOS
switches. The gate and the switch-level circuit diagram for the nor gate is shown in Figure
11-4.

Using the switch primitives discussed in Section 11.1, Switch-Modeling

Elements , the Verilog description of the circuit is shown in Example 11-4
below.
Example 11-4 Switch-Level Verilog for Nor Gate

//Define our own nor gate, my_nor

module my_nor (out, a, b);

output out;
input a, b;
//internal wires
wire c;

//set up power and ground lines

supplyl pwr; //pwr is connected to Vdd (power
supply)
supply0 gnd ; //gnd is connected to Vss (ground)

//instantiate pmos switches

pmos (c, pwr, b);
pmos (out, c, a);

//instantiate nmos switches

nmos (out, gnd, a):
nmos (out, gnd, b);
We can now test our nor gate, using the stimulus shown below.
//stimulus to test the gate
module stimulus;
reg A, B;
wire OUT;

//instantiate the my_nor module

my_nor n1(OUT, A, B);

//Apply stimulus
initial
Begin
//test all possible combinations
A = 1'bO; B = 1'b0;
#5 A = 1'b0; B = 1’bl;
#5 A = 1'bl; B = 1’b0;
#5 A = 1'b1; B = 1’bl;
end
//check results
initial
$monitor ($time, “ OUT = %b, A = %b, B = %b", OUT, A, B);
endmodule
The output of the simulation is shown below.

0 OUT = 1, A = 0, B = 0
5 OUT = 0, A = 0, B = 1
10 OUT = 0, A = 1, B = 0
15 OUT = 0, A = 1, B = 1

Thus we designed our own nor gate. If designers need to customize certain library blocks,
they use switch-level modeling.

11.2.2 2-to-1 Multiplexer

A 2-to-1 multiplexer can be defined with CMOS switches. We will use the my nor gate
declared in Section 11.2.1, CMOS Nor Gate to implement the not function. The circuit
diagram for the multiplexer is shown in Figure 11-5 below.

The 2-to-1 multiplexer passes the input 10 to output OUT if S = 0 and passes I1 to OUT if S
= 1. The switch-level description for the 2-to-1 multiplexer is shown in Example 11-4.
Example 11-4 Switch-Level Verilog Description of 2-to-1 Multiplexer

//Define a 2-to-1 multiplexer using switches

module my_mux (out, s, i0, i1) ;

output out;
input s, i0, i1;
Example 11-4 Switch-Level Verilog Description of 2-to-1 Multiplexer
(Continued)

//internal wire wire

sbar; //complement of s

//create the complement of s; use my_nor defined previously.

my_nor nt(sbar, S, s); //equivalent to a not gate

//instantiate cmos switches

cmos (out, i0, sbar, s);
cmos (out, il, s, sbar);
endmodule

The 2-to-1 multiplexer can be tested with a small stimulus. The stimulus is left as an
exercise to the reader.

11.2.3 Simple CMOS Flip-Flop

We designed combinatorial elements in the previous examples. Let us now define a

memory element which can store a value. The diagram for a level-sensitive CMOS flip-flop is
shown in Figure 11-6.
The switches C1 and C2 are CMOS switches, discussed in Section 11.1.2, CMOS Switches. Switch
C1 is open if clk = 1, and switch C2 is open if clk = 0. Complement of the clk is fed to the
ncontrol input of C2. The CMOS inverters can be defined by using MOS switches, as shown in
Figure 11-7.
We are now ready to write the Verilog description for the CMOS flip-flop. First , we need to
design our own inverter my_not by using switches. We can write the Verilog module
description for the CMOS inverter from the switch-level circuit diagram in Figure 11-7. The
Verilog description of the inverter is shown below.

Example 11-5 CMOS Inverter

//Define an inverter using MOS switches
module my_not(out, in);

output out;
input in;

//declare power and ground

supplyl pwr;
supply0 gnd;

//instantiate nmos and pmos switches

pmos (out, pwr, in);
nmos (out, gnd, in);
endmodule

Now, the CMOS flip-flop can be defined using the CMOS switches and my_not inverters. The Verilog
description for the CMOS flip-flop is shown in Example 11-6.
Example 11-6 CMOS Flip-flop

//Define a CMOS flip-flop

module cff ( q, qbar, d, clk);

output q, qbar;
input d, clk;

//internal nets
wire е;
wire nclk; //complement of clock

//instantiate the inverter

my_not nt(nclk, clk);
//instantiate CMOS switches
cmos (e, d, clk, nclk); //switch C1 closed i.e. e = d, when clk = 1.
cmos (e, q, nclk, clk); //switch C2 closed i.e. e = q, when clk = 0.

//instantiate the inverters

my_not nt1(qbar, e);
my_not nt2(q, qbar);
endmodule
We will leave it as an exercise to the reader to write a small stimulus module and simulate the
design to verify the load and store properties of the flip-flop.

11.3 Summary

We discussed the following aspects of Verilog in this chapter.

• Switch-level modeling is at a very low level of design abstraction. Designers use switch
modeling in rare cases when they need to customize a leaf cell . Verilog design at this level is
becoming less popular with increasing complexity of circuits.

• MOS, CMOS, bidirectional switches, and supply1 and supply0 sources can be used to design
any switch-level circuit. CMOS switches are a combination of MOS switches.

• Delays can be optionally specified for switch elements. Delays are interpreted differently for
bidirectional devices.
11.4 Exercises
1. Draw the circuit diagram for an xor gate, using nmos and pmos switches. Write the
Verilog description for the circuit. Apply stimulus and test the design
2. Draw the circuit diagram for and and or gates, using nmos and pmos switches. Write
the Verilog description for the circuits. Apply stimulus and test the design.
3. Design the 1-bit full-adder shown below using the xor, and, and or gates built in exercise
1 and exercise 2 above. Apply stimulus and test the design.
4. 11 Design a 4-bit bidirectional bus switch that has two buses, Bus A and Bus B , on
one side and a single bus, BUS, on the other side. A 1-bit control signal is used for
switching. Bus A and BUS are connected if control = 1. Bus B and BUS are connected if
control = 0. (Hint: Use the switches tranif0 and tranif1).Apply stimulus and test the
design.

5. Instantiate switches with the following delay specifications. Use your own
input/output port names.
a) A pmos switch with rise = 2 and fall = 3.
b) An nmos switch with rise = 4, fall = 6, turn-off = 5
c) А сmоs switch with delay = 6
d) A tranif1 switch with turn-on = 5, turn-off = 6
e) A tranif0 with delay = 3.