Combinational Circuits

+
HALF-ADDER
x

C S

• Half-adder: Performs the most basic digital arithmetic

operation, that is, the addition of two binary numbers.
The half-adder requires two outputs because the sum 1 + 1 is
•

binary 10. The two inputs are:

called S (for sum) and C (for carry out).
From the truth table write the Boolean function outputs for the sum
S and the carry out C:

S=x`y +xy` (Exclusive OR)

(Truth table for half-adder)
C=xy (AND)
x y C S
0 0 0 0
(Logic diagram)
0 1 0 1
1 0 0 1
1 1 1 0
Here is a proof of the Exclusive OR identity using truth table.
 FULL-ADDER

• To implement an arithmetic adder for multiple-bit inputs,

we need to treat the carry out from the lower bit as a third
input ( it becomes carry in for the current bit) in addition to
the two input bits at the current bit position.
X1 X0
Y1 Y0
+
Z1 Z0
S 1 C1 S0 C0
 Full- Adder
It adds 3-bits, it has 3-inputs and 2-outputs

We will use x, y and z for inputs and s for sum and c for carry are the
two outputs. x y z c s
The truth table 0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
Full Adder
S = x`y`z + x`yz` + xy`z` + xyz
k-map for s
y z 00 01 11 10
x
0 0 1 0 1

1 1 0 1 0
Full Adder
 K-map on C
y z 00 01 11 10
x
C=yz+xz+xy
0 0 0 1 0
But we would like to use the
previous logic gate XOR 1 0 1 1 1
 K-map on C

We can write C = x`yz + xy`z + xyz + xyz`

= z(x`y + xy`) + xy(z+z`)
= z (x  y) + xy (x  y) is already used for the sum S
Full Adder
Putting them together
we get: S= x  y  z
C= z (x  y) + xy

The logic diagram for the full adder

 NAND-ONLY LOGIC CIRCUITS

• Any logic circuits can be transformed to an

implementation where only NAND gates (and inverters)
are used.
• The general approach to finding a NAND-gate
realization: Use DeMorgan’s theorem to eliminate all the
OR operations.
 The NAND gate is functionally complete and can be used to
implement any Boolean function.

1. NAND Gate as Basic Logic Operations

NOT using NAND: A′=A NAND AA' = A \text{ NAND } AA′=A NAND A
AND sing NAND:
A⋅B=(A NAND B)’
OR using NAND (via De Morgan’s Theorem):

A+B=(A′ NAND B′)A + B = (A' \text{ NAND } B')A+B=(A′ NAND B′)

 NOR, XOR, XNOR, and other gates can also be implemented
using only NAND gates.

Why NAND?
•Universality: Since NAND is functionally complete, any logic function
can be built using just NAND gates.

Hardware Efficiency: In practical digital circuits (e.g., microprocessors),

•

NAND gates are often preferred due to their simple transistor

implementation.
 NAND-ONLY LOGIC CIRCUITS

(Example)
F = A + B • (C + D’)
= A + B • (C’D)’
Note that (C’D)’ = C + D’ and (A’X’)’ = A +
X
F = (A’ • (B • (C’D)’)’)’
Now there is no OR operation in the Boolean
expression. Note that
A NAND B = (AB)’
 F= (A’ • (B • (C’D)’)’)’
The logic circuit for this function is given by:

We can also use the same procedure to do NOR only gates.

Ch2. Decoder
Integrated Circuits
 An integrated circuit is a piece (also
called a chip) of silicon on which multiple
gates or transistors have been embedded

 These silicon pieces are mounted on a

plastic or ceramic package with pins along
the edges that can be soldered onto
circuit boards or inserted into appropriate
sockets
Integrated Circuits

 SSI, MSI, LSI: They perform small tasks such as addition

of few bits. small memories, small processors
 VLSI Tasks: - Large memory - Complex microprocessors,
CPUs
An SSI chip contains
independent NAND gates
Examples of
Combinational Circuits
 a) Decoders
 b) Encoders
 c) Multiplexers
 d) Demultiplexers
Decoder
 Accepts a value and decodes it

Output corresponds to value of n
inputs

 Consists of:

Inputs (n)

Outputs (2n , numbered from 0  2n - 1)

Selectors / Enable (active high or active
low)
The truth table of 2-to-4
Decoder
2-to-4 Decoder
2-to-4 Decoder
The truth table of 3-to-8
Decoder
A2 A1 A0 D0 D1 D2 D3 D4 D5 D6 D7

0 0 0 1
0 0 1 1
0 1 0 1

0 1 1 1

1 0 0 1

1 0 1 1
1 1 0 1

1 1 1 1
3-to-8 Decoder
3-to-8 Decoder with
Enable
2-to-4 Decoder: NAND
implementation
Decoder is enabled when E=0 and an output is
active if it is 0
2-4 Decoder with 2-input
and Enable
Decoder Expansion
 Decoder expansion
 Combine two or more small decoders

with enable inputs to form a larger

decoder

 3-to-8-line decoder constructed from

two 2-to-4-line decoders

The MSB is connected to the enable inputs

if A2=0, upper is enabled; if A2=1, lower is
enabled.
Decoder Expansion
 Combining two 2-4 decoders to
form one 3-8 decoder using
enable switch

The highest bit is used for the enables

Combinational Circuit Design
with Decoders
 Combinational circuit implementation
with decoders
 A decoder provide 2n minterms of n

input variables
 Since any Boolean function can be

expressed as a sum of minterms, one

can use a decoder and external OR
gates to implement any
combinational function.
 Combinational Circuit Design
with Decoders

Example Realize F (X,Y,Z) = Σ (1, 4, 7) with a decoder:

Designing Binary Adders with decoders

X Y Z C S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

C(X,Y,Z) = m(3,5,6,7) S(X,Y,Z) = S

m(1,2,4,7);
Example: design a full binary adder using
•

one decoder.
S(X,Y,Z) = m(1,2,4,7);
C(X,Y,Z) = m(3,5,6,7)
Chapter 2 Encoder
Encoders

 Perform the inverse operation of a

decoder
 2n (or less) input lines and n

output lines
Encoders
Encoders with OR gates
 Encoders

 Perform the inverse operation of a decoder

2n (or less) input lines and n output lines
Encoders

 Can be implemented with 3 OR gates

A0 = D1 + D3 + D5 + D7;
A1 = D2 + D3 + D6 + D7;
A2 = D4 + D5 + D6 + D7;
If more than 2 inputs are active
we need to use
priority encoder (priority for
inputs)
Priority Encoder

 Accepts multiple values and encodes them


Works when more than one input is active
 Consists of:

Inputs (2n)

Outputs
 when more than one output is active, sets

output to correspond to highest input

 V (indicates whether any of the inputs are

active)

Selectors / Enable (active high or active low)
D3 D2 D1 D0 A1 A2 V
0 0 0 0 x X 0
0 0 0 1 0 0 1
0 0 1 0 0 1 1
0 0 1 1 0 1 1
0 1 0 0 1 0 1
0 1 0 1 1 0 1
0 1 1 0 1 0 1
0 1 1 1 1 0 1
1 0 0 0 1 1 1
1 0 0 1 1 1 1
1 0 1 0 1 1 1
1 0 1 1 1 1 1
1 1 0 0 1 1 1
1 1 0 1 1 1 1
1 1 1 0 1 1 1
1 1 1 1 1 1 1
Priority Encoder
Priority Encoder
Chapter2 Digital
Components
Multiplexer (MUX)

A multiplexer can use addressing bits to

select one of several input bits to be the
output.

 A selector chooses a single data input

and passes it to the MUX output
 It has one output selected at a time.
 4 to 1 line multiplexer

4 to 1 line
multiplexer
S1 S0 F
2n MUX to 1
0 0 I0
n for this MUX is 2 0 1 I1

This means 2 1 0 I2

selection lines s0 1 1 I3

and s1
Multiplexer (MUX)
 Consists of:

Inputs (multiple) = 2n

Output (single)

Selectors (# depends on # of inputs) = n

Enable (active high or active low)
Function table with
enable
 Multiplexers versus
decoders
•A Multiplexer uses n binary select bits to choose
from a maximum of 2n unique input lines.
•Multiplexers and decoders both can decode

minterms.
•Decoders have n number of output lines while

multiplexers have only one output line.

•The decoded minterms are used to select data from

one of up to 2n unique data input lines.

•The output of the multiplexer is the data input

whose index is specified by the n bit code.

 Multiplexer Versus
I3
Decoder

I2

I1

I0
S1

S0

2-t0-4 Decoder
4-to-1 Multiplexer
Note that the multiplexer has an extra OR gate. A1 and A0 are
the two inputs in decoder. There are four inputs in multiplexer.
Function table with
enable
Cascading multiplexers

Using three 2-1 MUX

to make one 4-1 MUX

S1 S0 F
0 0 I0
0 1 I1
1 0 I2
1 1 I3
Example: Construct an
8-to-1 multiplexer using I0
2-to-1 multiplexers. I1

S2 S1 S0 F I2
0 0 0 I0 I3
2-1 F
0 0 1 I1 MUX

S E
0 1 0 I2
I4 S2 E
0 1 1 I3
I5
1 0 0 I4
1 0 1 I5
1 1 0 I6 I6
1 1 1 I7 I7
Example ( ) Construct 8-to-1 multiplexer using one 2-to-1 multiplexer and
two 4-to-1 multiplexers

S2 S1 S0 X
Quadruple 2-to-1 Line Multiplexer

Used to supply four bits to the

output. In this case two inputs four
bits each.
Quadruple 2-to-1 Line
Multiplexer

E S Y
(Enable) (Select) (Output)
0 X All 0’s

1 0 A

1 1 B
Subtraction using addition
 Conventional addition (using carry) is
easily
 implemented in digital computers.
 However; subtraction by borrowing is
difficult and inefficient for digital
computers.
 Much more efficient to implement
subtraction using ADDITION OF the
COMPLEMENTS of numbers.
 Complements of
numbers
(r-1 )’s Complement
•Given a number N in base r having n digits,
•the (r- 1)’s complement of N is defined as

(rn - 1) - N

For decimal numbers the

•

base or r = 10 and r- 1= 9, 9 9 9 9 9

so the 9’s complement of N

-
•
Digit Digit Next Next First
is (10n-1)-N n n-1 digit digit digit

99999……. - N
•
 9’s complement Examples
9 9 9 9 9 9

2- Find the 9’s complement of 546700 and - 5 4 6 7 0 0

12389
4 5 3 2 9 9
The 9’s complement of 546700 is 999999 -
546700= 453299
9 9 9 9 9

-
and the 9’s complement of 12389 is
99999- 12389 = 87610. 1 2 3 8 9

8 7 6 1 0
l’s complement
 For binary numbers, r = 2 and r —
1 = 1,
 r-1’s complement is the l’s
complement.
 The l’s complement of N is (2n - 1)
- N. Bit n-1 Bit n-2 ……. Bit 1 Bit 0

1 1 1 1 1

- Digit
n
Digit
n-1
Next
digit
Next
digit
First
digit
 l’s complement

Find r-1 complement for binary number N with four binary digits.
r-1 complement for binary means 2-1 complement or 1’s
complement.
n = 4, we have 24 = (10000)2 and 24 - 1 = (1111)2.

The l’s complement of N is (24 - 1) - N. = (1111) - N

 l’s complement

1 1 1 1 1 1 1

The complement 1’s of

- 1 0 1 1 0 0 1

1011001 is 0100110 0 1 0 0 1 1 0

1 1 1 1 1 1 1

The 1’s complement of

- 0 0 0 1 1 1 1

0001111 is 1110000 1 1 1 0 0 0 0
 r’s Complement
•Given a number N in base r having n digits,
•the r’s complement of N is defined as

rn - N.

For decimal numbers the

•

base or r = 10,
1 0 0 0 0 0
•so the 10’s complement of N
is 10n-N. - Digit
n
Digit
n-1
Next
digit
Next
digit
First
digit

100000……. - N
•
 10’s complement
Examples
Find the 10’s complement of
546700 and 12389 1 0 0 0 0 0 0

The 10’s complement of 546700 - 5 4 6 7 0 0

is 1000000 - 546700= 453300 4 5 3 3 0 0

and the 10’s complement of

12389 is 1 0 0 0 0 0

100000 - 12389 = 87611. - 1 2 3 8 9

Notice that it is the same as 9’s 8 7 6 1 1

complement + 1.
 2’s complement

For binary numbers, r = 2,

r’s complement is the 2’s complement.
The 2’s complement of N is 2n - N.

1 0 0 0 0 0

- Digit
n
Digit
n-1
Next
digit
Next
digit
First
digit
 2’s complement Example
1 0 0 0 0 0 0 0

The 2’s complement of

1011001 is 0100111
- 1 0 1 1 0 0 1

0 1 0 0 1 1 1

1 0 0 0 0 0 0 0

The 2’s complement of

0001111 is 1110001
- 0 0 0 1 1 1 1

1 1 1 0 0 0 1
 Fast Methods for 2’s
Complement

Method 1:
The 2’s complement of binary number is obtained by adding 1 to the
l’s complement value.
Example:
1’s complement of 101100 is 010011 (invert the 0’s and 1’s)
2’s complement of 101100 is 010011 + 1 = 010100
 Fast Methods for 2’s
Complement

Method 2:
The 2’s complement can be formed by leaving all least significant 0’s
and the first 1 unchanged, and then replacing l’s by 0’s and 0’s by l’s
in all other higher significant bits.

Example:
The 2’s complement of 1101100 is
0010100
Leave the two low-order 0’s and the first 1 unchanged, and then
replacing 1’s by 0’s and 0’s by 1’s in the four most significant bits.
 Examples
 Finding the 2’s complement of (01100101)2
 Method 1 – Simply complement each bit and
then add 1 to the result.
(01100101)2
[N] = 2’s complement = 1’s complement (10011010) 2
+1
=(10011011)2
 Method 2 – Starting with the least significant
bit, copy all the bits up to and including the first
1 bit and then complement the remaining bits.
N =01100101
[N] =10011011
Subtraction of Unsigned
Numbers
using r’s complement
Subtract N from M : M–N

 r’s complement N  (rn – N )

 add M to ( rn – N ) : Sum = M + ( r n – N)

 take r’s complement (If M  N, the

negative sign will produce an end carry 
rn we need to take the r’s complement
again.)
Subtraction of Unsigned
Numbers
using r’s complement
 (1) if M  N, ignore the carry
without taking complement of
sum.
 (2) if M < N, take the r’s
complement of sum and place
negative sign in front of sum. The
answer is negative.
Example 1 (Decimal unsigned numbers),

perform the subtraction 72532 - 13250 = 59282.

M > N : “Case 1” “Do not take complement of sum

and discard carry”
The 10’s complement of 13250 is 86750.
Therefore:
M= 72532
10’s complement of N =+86750
Sum= 159282
Discard end carry 105= - 100000
Answer = 59282 no complement
 Example 2;
Now consider an example with M <N.
The subtraction 13250 - 72532 produces negative 59282. Using
the procedure with complements, we have

M = 13250
10’s complement of N = +27468
Sum = 40718

Take 10’s complement of Sum = 100000

-40718
The number is : 59282
Place negative sign in front of the number: -59282