Digital Logic

& Circuits
Logic Gates: using RTL

Prepared by: Tawsif Ibne Alam

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RTL Logic
• The basic circuit of the RTL digital logic family is the NOR gate.
• The voltage levels for the circuit are 0.2 V for the low level and from
1 to 3.6 V for the high level.
• The fan-out of the RTL gate is limited by the value of the output
voltage when high.
• As the output is loaded with inputs of other gates, more current is
consumed by the load.
• Any voltage below 1 V in the output may not drive the next
transistor into saturation as required.
• The power dissipation of the RTL gate is about 12 mW.
• The propagation delay averages 25 ns.

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Disadvantages of RTL
Logic

• It’s relatively slow.

• Low noise immunity and noise margin.
• Low Fan-out (Approx. 3~5)
• Expensive due to fabricated of resistor.
• It can not operate above 4MHz.

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NOT Gate Using RTL Logic

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 NOT Gate Using RTL Logic

Operation Circuit

Input Transistor Output

Status
A= Low T1=OFF , Cutoff Region Q=+Vcc, High

A= High T1=ON , Saturation Region Q= VCE(SAT) =0.2 V, Low

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NAND Gate Using RTL Logic

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 NAND Gate Using RTL Logic

Operation Circuit
Input Transistor Output
Status
A=Low, B=Low T1= OFF, Cutoff Region Q= Vcc, High
T2= OFF, Cutoff Region
A=Low, B=High T1= OFF, Cutoff Region Q= Vcc, High
T2= ON, Saturation Region
A=High, B=Low T1= ON, Saturation Region Q= Vcc, High
T2= OFF, Cutoff Region
A=High, B=High T1= ON, Saturation Region Q= Ground, Low
T2= ON, Saturation Region

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 NOR Gate Using RTL Logic
• If any input of the RTL gate is high, the corresponding transistor is driven into saturation. This causes the output to be low,
regardless of the states of the other transistors.
• If all inputs are low at 0.2 V, all transistors are cut off because VBE < 0.6 V. This causes the output of the circuit to be high,
approaching the value of supply voltage VCC.

**Related Problems will be solved in class.

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 NOR Gate Using RTL Logic

Operation Circuit

Input Transistor Output

Status
All input = low All transistor OFF, Output = Vcc, High
Cutoff Region.
Any one input/Two Corresponding Output = VCE(SAT) = 0.2 V.
input/all input = High transistor turned ON, Low
Saturation Region

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DTL Logic
• The basic circuit in the DTL digital logic family is the NAND gate.
• Each input is associated with one diode.
• The diodes and the 5-kΩ resistor form an AND gate.
• The transistor serves as a current amplifier while inverting the digital
signal.
• The two voltage levels are 0.2 V for the low level and between 4 and
5 V for the high level.
• The power dissipation of a DTL gate is about 12 mW.
• The propagation delay averages 30 ns.
• The noise margin is about I V and a fan-out as high as 8 is possible.

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DTL Logic - Disadvantages
• Relatively lower speed.
• Propagation is higher than RTL.

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NAND Gate Using
DTL Logic
• If any input of the gate is low at 0.2 V, the
corresponding input diode conducts
current through Vcc and the 5-kΩ resistor
into the input node.
• The voltage at point P is equal to the input
voltage of 0.2 V plus a diode drop of 0.7 V,
for a total of 0.9 V.

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NAND Gate Using DTL
Logic
• In order for the transistor to start conducting, the voltage at point P must overcome a
potential of one VBE drop in Q 1 plus two diode drops across D 1 and D 2, or 3 X 0.6 = 1.8
V.
• Since the voltage at P is maintained at 0.9 V by the input conducting diode, the transistor
is cut off and the output voltage is high at 5 V.
• If all inputs of the gate are high, the transistor is driven into the saturation region.
• The voltage at P now is equal to VBE plus the two diode drops across D I and D 2, or 0.7 x 3
= 2.1 V.
• Since all inputs are high at 5 V and VP = 2.1 V, the input diodes are reverse biased and off.
• The base current is equal to the difference of currents flowing in the two 5-kΩ resistors
and is sufficient to drive the transistor into saturation.
• With the transistor saturated, the output drops to VCE of 0.2 V, which is the low level for
the gate.

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 NAND Gate Using DTL Logic

Operation Circuit

**For Q1 to conduct, VP > VBE(Q1) + (2×0.7)

= 0.7 V + 1.4 V = 2.1 V

Input Transistor & Diode Output

Status
Any Input = Corresponding input diode As VP< 2.1V.Q1 is OFF. Cutoff
Low(0.2V) forward biased. VP= (0.2+0.7)V region.
Y= Vcc=5V (High)
All input = All input diode reverse biased. Q1 is ON. Saturation region.
High (5 V) D1 & D2 forward biased. Y = VCE = 0.2 V (Low)
Q1 ON. Saturation region.
VP= VBE(Q1)+ VD1+ VD2
= 0.7+0.7+0.7 = 2.1 V

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 NAND Gate Using modified DTL Logic
• The fan-out of the DTL gate is limited by the maximum current that can flow in the collector of
the saturated transistor.
• The fan-out of a DTL gate may be increased by replacing one of the diodes in the base circuit with
a transistor.

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 NAND Gate Using modified DTL Logic

• Transistor Q1 is maintained in the active region when output transistor Q2 is saturated.

• As a consequence, the modified circuit can supply a larger amount of base current to the output
transistor.
• The output transistor can now draw a larger amount of collector current before it goes out of
saturation.
• Part of the collector current comes from the conducting diodes in the loading gates when Q 2 is
saturated.
• Thus, an increase in allowable collector saturated current allows more loads to be connected to
the output, which increases the fan-out capability of the gate.

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 NAND Gate Using HTL Logic
• Due to presence of electrical motor’s on-off control circuits, High voltage switches etc. are used in industrial
environment, Thereby noise level is very high.
• So DTL redesigned with a power supply of 5V and the D2 is replaced by a zener diode with a breakdown
voltage of 6.9 V.
• So HTL posses a high threshold of noise immunity.
• To conduct Q2, the emitter of Q1 must rise to a potential,
VBE (Q2) + VZ = 0.7+6.9 = 7.6 V
• So, Only if the noise signal is greater than 7.6 V , then it will
be able to change the state. Higher noise immunity.

Figure: 3 Input HTL NAND

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 TTL Logic
• The original basic TTL gate was a slight improvement over the DTL gate.
• As the TTL technology progressed, additional improvements were added to the point where this logic family
became the most widely used family in the design of digital systems.
• The propagation delay of a transistor circuit that goes into saturation depends mostly on two factors: storage
time and RC time constants.
• Reducing the storage time decreases the propagation delay. [ RC T P ]
• Reducing resistor values in the circuit reduces the RC time constants and decreases the propagation delay.
• Of course, the trade-off is higher power dissipation because lower resistances draw more current from the
power supply. The speed of the gate is inversely proportional to the propagation delay.
• In the low-power TTL gate, the resistor values are higher than in the standard gate to reduce the power
dissipation, but the propagation delay is increased. [ R so P D but TP ]
• In the high-speed TTL gate, resistor values are lowered to reduce the propagation delay, but the power
dissipation is increased. . [ R so TP but PD ]
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 TTL Logic
• The Schottky TTL gate was the next improvement in the technology.
• The effect of the Schottky transistor is to remove the storage time delay by preventing the transistor from
going into saturation.
• The low-power Schottky TTL sacrifices some speed for reduced power dissipation.
• It is equal to the standard TTL in propagation delay, but has only one fifth the power dissipation
• Recent innovations have led to the development of the advanced Schottky series.
• The advanced low-power Schottky has the lowest speed-power product and is the most efficient series. It is
replacing all other low· power versions in new designs.
• TTL gates in all the available series come in three different types of output configuration:
1. Open -collector output
2. Totem-pole output
3. Three-state (or tristate) output

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 Open Collector Output (NAND)
• The multiple emitters in transistor Q1 are connected to the inputs.
These emitters behave most of the time like the input diodes in the
DTL gate since they form a pn junction with their common base.
• The base-collector junction of Q1 acts as another pn junction
diode corresponding to D1 in the DTL gate.
• Transistor Q2 replaces the second diode, D2, in the DTL gate.
The output of the TTL gate is taken from the open collector of Q3.
• A resistor connected to Vcc must be inserted external to the IC
package for the output to "pull up" to the high voltage level when
Q 3 is off; otherwise, the output acts as an open circuit.

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 Open Collector Output (NAND)

Condition: Circuit
 For Q3 to start conducting, the path from Q1 to Q3
must overcome.
= One diode drop in B-C junction of Q1 + two VBE
drop in Q2 & Q3 = 3 × 0.7 = 2.1 V
Operation:
Input Transistor & Diode Output
Status

Any Input = Corresponding BE junction of Q1 is VBE (Q1)=0.9 V.

Low(0.2V) forward biased. Voltage at base of So,Q2& Q3 Cutoff.
Q1 = 0.2V (I/P) + 0.7 V (V BE)= 0.9V Y = Vcc = 5 V (High)
All input = All BE junction of Q1 is reversed VBE (Q1)=2.1 V.
High (5 V) biased. Q2 & Q3 saturation region. So,Q2& Q3 Saturates.
Y = VCE(Q3) = 0.2V (Low)

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 Open Collector Output (NAND)
Open-collector gates are used in three major applications:
1. Driving a lamp or relay
2. Performing wired logic
3. Construction of a common-bus system.
External resistor advantage:
• Without an external resistor, the output of the gate will be an open circuit when Q3 is off. An open circuit to
an input of a TTL gate behaves as if it has a high-level input (but a small amount of noise can change this to a
low level).
• So, External resistor is recommended because of the low noise immunity encountered.

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 Totem pole Output (NAND)
• The output impedance of a gate is normally a resistive plus a capacitive load.
• The capacitive load consists of the capacitance of the output transistor, the capacitance of the fan-out gates,
and any stray wiring capacitance.
• When the output changes from the low to the high state, the output transistor of the gate goes from
saturation to cutoff and the total load capacitance, C, charges exponentially from the low to the high voltage
level with a time constant equal to RC.
• For the open-collector gate, R is the external resistor marked RL.
typical operating value C = 15 pF and RL = 4 kΩ. Propagation delay, tP = 35ns.
• With an active pull-up circuit replacing the passive pull-up resistor RL , the propagation delay is reduced
to 10 ns.

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 Totem pole Output (NAND)
Condition Circuit
• The reason for placing the diode in the circuit is to provide a diode drop in
the output path and thus ensure that Q4 is cut off when Q3 is saturated.
• For Q3 to start conducting, the path from Q1 to Q3 must overcome.
= One diode drop in B-C junction of Q1 + two VBE
drop in Q2 & Q3 = 3 × 0.7 = 2.1 V
• To conduct Q4, base voltage must have = 0.7 (VBE of Q4)+ 0.7 (D1) = 1.4 V.
Input Transistor & Diode Output
Status
Any Input = Corresponding BE junction of Q1 is • Q2& Q3 Cutoff.
Low(0.2V) forward biased. Voltage at base of • Q4 Conducts. D1 Forward biased.
Q1 = 0.2V (I/P) + 0.7 V (V BE)= 0.9V • Y = (High)
Voltage at base of Q2 = 5V

All input = All BE junction of Q1 is reversed VBE (Q1)=2.1 V. So,Q2& Q3 Saturates.

High (5 V) biased. Q2 & Q3 saturation region. VB (Q4) = 0.9V . So, Q4 cutoff.
Q4 Cutoff region. Y = VCE(Q3) = 0.2V (Low)

**This configuration is called a totem-pole output because

transistor Q4 "sits" upon Q3.
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 Totem pole Output (NAND)
Advantage of totem pole output:
• When the output changes to the high state because one of the inputs drops to the low state, transistors Q2
and Q3 go into cutoff. However, the output remains momentarily low because the voltages across the load
capacitance cannot change instantaneously.
• The current needed to charge the load capacitance causes Q4 to momentarily saturate, and the output
voltage rises with a time constant RC.
• But R in this case is equal to 130Ω, plus the saturation resistance of Q4, plus the resistance of the diode, for a
total of approximately 150Ω.
• This value of R is much smaller than the passive pull-up resistance used in the open-collector circuit.
• As a consequence, the transition from the low to high level is much faster.

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 Schottky TTL Gate
• The Schottky diode is formed by the junction of a metal and semiconductor, in contrast to a conventional
diode, which is formed by the junction of p-type and n-type semiconductor material.
• A reduction in storage time results in a reduction of propagation delay. This is because the time needed for a
transistor to come out of saturation delays the switching of the transistor from the on condition to the off
condition
• Saturation can be eliminated by placing a Schottky diode between the base and collector of each saturated
transistor in the circuit.
• The voltage across a conducting Schottky diode is only 0.4 V.
• The presence of a Schottky diode between the base and collector prevents the transistor from going into
saturation. The resulting transistor is called a Schottky transistor.
• The use of Schottky transistors in a TTL decreases the propagation delay without a sacrifice of power
dissipation.

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 Schottky Diode TTL
Description Circuit
• The special symbol used for the Schottky transistors and diodes.
• An exception is made of Q4 since it does not saturate, but stays in the
active region.
• Resistor values have been reduced to further decrease the propagation
delay.
• Two new transistors, Q5 and Q6 have been added, and Schottky diodes
are inserted between each input terminal and ground. There is no
diode in the totem-pole circuit.
• The new combination of Q5 and Q4 still gives the two VBE drops
necessary to prevent Q4 from conducting when the output is low. This
combination comprises a double emitter-follower called a Darlington
pair. The Darlington pair provides a very high current gain and
extremely low resistance. This is exactly what is needed during the
low-to-high swing of the output, resulting in a decrease of propagation
delay.

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 Three-state Gate
• The outputs of two TTL gates with totem-pole structures cannot be connected together as in open-collector
outputs.
• However, a special type of totem-pole gate that allows the wired connection of outputs for the purpose of
forming a common-bus system. When a totem-pole output TTL gate has this property, it is called a three-
state (or tristate) gate.

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 Three-state Gate

Description Circuit
• A three-state gate exhibits three output states:
(1) A low-level state when the lower transistor in the totem-
pole is on and the upper transistor is off,
(2) A high-level state when the upper transistor in the
totem-pole is on and the lower transistor is off, and
(3) A third state when both transistors in the totem-pole are
off. The third state provides an open circuit or high-
impedance state that allows a direct wire connection of
many outputs to a common line. Three-state gates eliminate
the need for open-collector gates in bus configurations.

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CMOS inverter Fig (a) shows a CMOS
inverter schematic
Fig (b) shows a CMOS
inverter effective
resistance model
Fig (c) shows the inverter
switch level

Fig (a)
Fig (b) Fig (c)
•The pull-up network is made
up of only P-MOS
•The pull-down network is
made up of only N-MOS
 Points to Remember
• P-MOS is used for designing pull-up networks in combinational logic design with CMOS.

• N-MOS is used for designing pull-down networks in combinational logic design with

CMOS.

• P-MOS is responsible for driving the output to logic 1/high/ VDD.

• P-MOS is activated using a logic 0/LOW at its gate terminal

• N-MOS is responsible for driving the output to logic 0/LOW/GND

• N-MOS is activated by logic 1/HIGH at its gate terminal.

 Points to Note
• The pull-up inputs do not have any BAR
over them.
• The pull-up inputs appear the same way as
determined by the pull down network. In
this case just A and B. Not and .
 Points to Note
• The pull-up inputs do not have any
BAR over them.
• The pull-up inputs appear the same
way as determined by the pull down
network. In this case just A and B. Not
and .
 References

1. Thomas L. Floyd, “Digital Fundamentals” 8th edition, Prentice Hall – Pearson Education.
2. M. Morris Mano, “Digital Logic & Computer Design” Prentice Hall
3. https://www.electronics-tutorials.ws
4. https://www.tutorialspoint.com

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