Week_4
Week_4
Landscape
(CS 526)
Global Memory
Global Memory
- Power
- Performance
(Perf/Clock) ILP
The memory
hierarchy
• If simultaneous multithreading only:
– all caches shared
• Multi-core chips:
– L1 caches private
– L2 caches private in some architectures
and shared in others
CORE1
CORE0
• Each core is L1 cache L1 cache
hyper-threaded (SMT)
L2 cache
• Private L1 caches
memory
• Shared L2 caches
Designs with private L2
caches
CORE1
CORE0
CORE1
CORE0
L1 cache L1 cache L1 cache L1 cache
L3 cache L3 cache
memory
memory
Both L1 and L2 are private
Examples: AMD Opteron,
A design with L3 caches
AMD Athlon, Intel Pentium D
Example: Intel Itanium 2
Private vs Shared
caches?
• Advantages ???
Private vs Shared
caches
• Advantages of private:
– They are closer to core, so faster access
– Reduces contention
• Advantages of shared:
– Threads on different cores can share the same cache
data
– More cache space available if a single (or a few) high-
performance thread runs on the system