The major parts are

 central processing unit or CPU

 memory
 input and output circuitry or I/O.
Connecting these parts together are three sets of parallel lines called buses.
The three buses are
 address bus
 data bus and
 control bus.
i) MEMORY: The memory section usually consists of a mixture of RAM and ROM. It
may also have magnetic floppy disks, magnetic hard disks, or laser optical disks.
Memory has two purposes. The first purpose is to store the binary codes for the
sequence of instructions you want the computer to carry out. The second purpose of
the memory is to store the binary-coded data with which the computer is going to be
working.
ii) INPUT/OUTPUT: The input/output or I/O section allows the computer to take in
data from the outside world or send data to the outside world. These allow the user
and the computer to communicate with each other.
iii) CPU: The central processing unit or CPU controls the operation of the
computer.
 It fetches binary-coded instruction of the computer.
 It fetches binary-coded instructions from memory, decodes the instructions
into a series of simple actions, and carries out these actions.
 The CPU contains an arithmetic logic unit, or ALU. Which can perform add,
subtract, OR, AND, invert, or exclusive-OR operations on binary words when
instructed to do so.
 The CPU also contains an address counter which is used to hold the address of
the next instruction or data to be fetched from memory, general-purpose
registers which are used for temporary storage of binary data, and circuitry
which generates the control bus signals.
iv) ADDRESS BUS: The address bus consists of 16, 20, 24, or more parallel signal lines.
 On these lines the CPU sends out the address of the memory location that is to be
written to or read from.
 The number of address lines determines the number of memory locations that the
CPU can address.
 If the CPU has N address lines then it can directly address 2^N memory locations.

v) DATA BUS: The data bus consists of 8, 16, 32 or more parallel signal lines.
 As indicated by the double-ended arrows on the data bus line, the data bus
lines are bi-directional.
 This means that the CPU can read data in on these lines from memory or
from a port as well as send data out on these lines to memory location or to a
port.
 Many devices in a system will have their outputs connected to the data bus,
but the outputs of only one device at a time will be enabled.
vi) CONTROL BUS: The control bus consists of 4-10 parallel signal
lines.
 The CPU sends out signals on the control bus to enable the outputs
of addressed memory devices or port devices.
 Typical control bus signals are memory read, memory write, I/O
read, and I/O writer.
 To read a byte of data from a memory location, for example, the
CPU sends out the address of the desired byte on the address bus and
then sends out a memory read signal on the control bus.
History of mp
 8086 Microprocessor features:

1. It is 16-bit microprocessor
2. It has a 16-bit data bus, so it can read data from or write data
to memory and ports either 16-bit or 8-bit at a time.
3. It has 20 bit address bus and can access up to memory
locations (1 MB).
4. It can support up to 64K I/O ports
5. It provides 14, 16-bit registers
6. It has multiplexed address and data bus AD0-AD15 & A16-A19
7. It requires single phase clock with 33% duty cycle to
provide internal timing.
8. Prefetches up to 6 instruction bytes from memory and
queues them in order to speed up the processing.
9. 8086 supports 2 modes of operation
a. Minimum mode
b. Maximum mode
Intel 8086
internal
architecture
Architecture of 8086 microprocessor:
 As shown in the above figure, the 8086 CPU is divided into two independent functional parts
Bus Interface Unit(BIU)
Execution Unit(EU)
 Dividing the work between these two units’ speeds up processing.
Interface act as a mediator for execution parts to external device (RAM, ROM, I/O )
or it is a bridge between external device and processor.
Function of the Bus Interface Unit (BIU):
 Fetches instructions or data from memory
 Reads data from ports
 Write data to memory
 Writes data to ports.
 In simple words, the BIU handles all transfers of data and addresses on the
buses for the execution unit.

BIU consists of three functional parts

1.Instruction Pointer (IP)
2.Segment Register
3.Instruction Queue
1. Instruction pointer (IP)—16 bit register that store or keep the address of
memory location of next instruction to be executed.
2. Segment register: The memory space 1Mb of 8086 is segmented in to 4 blocks
(4 segment register). This 1 megabyte memory is divided into 16 logical
segments. Each blocks specified by register with maximum size of 64Kb. All are
16 bit register
The 4 segment registers are :
a.Code segment register (CS)
b.Data segment register (DS)
c.Stack segment register (SS)
d.Extra segment register (ES)
 Code segment register (CS): is used for addressing
memory location in the code segment of the memory,
where the executable program is stored.
 Data segment register (DS): points to the data segment
of the memory where the data is stored.
 Extra Segment Register (ES) : also refers to a segment in
the memory which is another data segment in the
memory.
 Stack Segment Register (SS): is used for addressing
stack segment of the memory. The stack segment is that
segment of memory which is used to store stack data
 Instruction
 Stack
 Data
3. Instruction queue:
 BIU performs its operation in parallel with EU
 BIU fetches instruction byte while execution unit is
executing operation.
 The pre-fetched instruction is send in group of high speed
register called instruction queue.
 It is a 6-byte queue (FIFO)
 The pre-Fetch queue is connected with the control
unit which is responsible for decoding op-code and
operands and telling the execution unit what to do with the
help of timing and control signals.
The Execution Unit (EU):
 The execution unit tells the BIU where to fetch instructions or data from,
 Decodes instructions, and Executes instructions.
 The EU contains control circuitry, which directs internal operations(to perform various
internal operations).
 A decoder in the EU translates instructions fetched from memory into a series of actions,
which the EU carries out.
 The EU has a 16-bit arithmetic logic unit (ALU) which can add, subtract, AND, OR, XOR,
increment, decrement, complement or shift binary numbers.
 The main functions of EU are:
- Decoding of Instructions
- Execution of instructions
Steps
EU extracts instructions from top of queue in BIU
Decodes the instructions
Generates operands if necessary
Passes operands to BIU
& requests it to perform read or write bus
cycles to
memory or I/O
Perform the operation specified by the
Functional parts of Execution Unit
(EU)
General Purpose Register (GPRs)
Pointer and Index Register
ALU
Flag Register
 Control Unit
General Purpose Register
 AX register: (Combination of AH and AL Registers)
It holds operands and results during multiplication and
division operations.
Also an accumulator during String operations.
 BX register: (Combination of BH and BL Registers)
It holds the memory address (offset address) in indirect
addressing modes.
 CX register: (Combination of CH and CL Registers)
It holds the count for instructions like a loop, rotates, shifts and string
operations.
 DX register: (Combination of DH and DL Registers)
It is used with AX to hold 32-bit values during multiplication
Pointers and Index Registers:
The index and pointer registers are given below:
BP—Base pointer
 SP—Stack pointer
 SI—Source index
 DI—Destination index
 The pointers registers contain offset within the particular segments.
 The pointer register SP contains offset within the stack segment.
 The index registers are used as general purpose registers as well as for offset
storage in case of indexed, base indexed and relative base indexed addressing
modes.
 The register SI is used to store the offset of source data in data segment.
 The register DI is used to store the offset of destination in data or extra segment.
 The Index registers are particularly useful for string manipulation
8086 flag register and its functions:
 The 8086 flag register contents indicate the results of computation in the ALU.
 It also contains some flag bits to control the CPU operations.
 A 16 bit flag register is used in 8086 (9 flags). It is divided into two parts .
o Condition code or status flags (6 flags)-
o Machine control flags (3 flags)-direction, interrupt enable and trap
 The condition code flag register is the lower byte of the 16-bit flag register. The
condition code flag register is identical to 8085 flag register, with an additional overflow
flag.
 The control flag register is the higher byte of the flag register. It contains three flags
namely direction flag (D), interrupt flag (I) and trap flag (T).
8086 HAS PIPELINING ARCHITECTURE:
 While the EU is decoding an instruction or executing an instruction, which does not
require use of the buses, the BIU fetches up to six instruction bytes for the following
instructions.
 The BIU stores these pre-fetched bytes in a first-in-first-out register set called a queue.
 When the EU is ready for its next instruction from the queue in the BIU. This is much
faster than sending out an address to the system memory and waiting for memory to send
back the next instruction byte or bytes.
 Except in the case of JMP and CALL instructions, where the queue must be dumped and
then reloaded starting from a new address, this pre-fetch and queue scheme greatly
speeds up processing.
 Fetching the next instruction while the current instruction executes is called pipelining.
Register organization:
 8086 has a powerful set of registers known as general purpose registers and special
purpose registers.
 All of them are 16-bit registers.
 General purpose registers:
 These registers can be used as either 8-bit registers or 16-bit registers.
 They may be either used for holding data, variables and intermediate results
temporarily or for other purposes like a counter or for storing offset address for some
particular addressing modes etc.

 Special purpose registers:

 These registers are used as segment registers, pointers, index registers or as offset storage
registers for particular addressing modes.
 The 8086 registers are classified into the following types:
General Data Registers
Segment Registers
Pointers and Index Registers
Flag Register
8086 PIN DIAGRAM

PIN DESCRIPTION
 AD0-AD15 (Bidirectional): Address/Data bus. These are low
order address bus. They are multiplexed with data.
 When AD lines are used to transmit memory address the symbol A
is used instead of AD, for example A0-A15.
 When data are transmitted over AD lines the symbol D is used in
place of AD, for example D0-D7, D8-D15 or D0-D15.
 A16-A19 (Output): High order addresses bus. These are
multiplexed with status signals. A16/S3, A17/S4, A18/S5,
A19/S6: The specified address lines are multiplexed with
corresponding status signals.
 BHE (Active Low)/S7 (Output): Bus High Enable/Status. During
T1 it is low. It is used to enable data onto the most significant
half of data bus, D8-D15. 8-bit device connected to upper half of
the data bus use BHE (Active Low) signal. It is multiplexed with
status signal S7. S7 signal is available during T2, T3 and T4.
 RD (Read) (Active Low): The signal is used for read operation. It
is an output signal. It is active when low.
 READY: This is the acknowledgement from the slow device or
memory that they have completed the data transfer. The signal
made available by the devices is synchronized by the 8284A
clock generator to provide ready input to the 8086. The signal is
INTR-Interrupt Request: This is a triggered input. This is sampled
during the last clock cycles of each instruction to determine the
availability of the request. If any interrupt request is pending, the
processor enters the interrupt acknowledge cycle. This can be internally
masked by resulting the interrupt enable flag. This signal is active high
and internally synchronized.
NMI (Input) –NON-MASKABLE INTERRUPT: It is an edge triggered input
which causes a type 2 interrupt. A subroutine is vectored to via an
interrupt vector lookup table located in system memory. NMI is not
mask-able internally by software. A transition from LOW to HIGH initiates
the interrupt at the end of the current instruction. This input is internally
INTA: INTA: Interrupt acknowledges. It is active LOW during T2, T
3 and T w of each interrupt acknowledge cycle.
MN/ MX MINIMUM / MAXIMUM: This pin signal indicates what
mode the processor is to operate in.
Q/GT RQ/GT0: REQUEST/GRANT: These pins are used by other
local bus masters to force the processor to release the local bus at
the end of the processor's current bus cycle. Each pin is
bidirectional with RQ/GT having higher priority than RQ /GT1.
LOCK: It’s an active low pin. It indicates that other system bus
masters are not to allowed to gain control of the system bus while
LOCK is active LOW. The LOCK signal remains active until the
TEST: This input is examined by a ‘WAIT’ instruction. If the TEST pin
goes low, execution will continue, else the processor remains in an
idle state. The input is synchronized internally during each clock cycle
on leading edge of clock.
CLK- Clock Input: The clock input provides the basic timing for
processor operation and bus control activity. It’s an asymmetric
square wave with 33% duty cycle.
RESET (Input) : RESET: causes the processor to immediately
terminate its present activity. The signal must be active HIGH for at
least four clock cycles.
Vcc – Power Supply ( +5V D.C.)
QS1, QS0 (Queue Status) These signals indicate the status of the
internal 8086 instruction queue according to the table shown
below
DT/R : DATA TRANSMIT/RECEIVE: This pin is needed in minimum
system that desires to use an 8286/8287 data bus transceiver. It is
used to control the direction of data flow through the transceiver.
DEN: DATA ENABLE .This pin is provided as an output enable for the
8286/8287 in a minimum system which uses the transceiver. DEN is
active LOW during each memory and I/O access and for INTA cycles.
HOLD/HOLDA: HOLD indicates that another master is requesting a
local bus .This is an active HIGH. The processor receiving the ``hold''
request will issue HLDA (HIGH) as an acknowledgement in the middle
of a T 4 or T 1 clock cycle.