Dma Controller.pptx
Dma Controller.pptx
CONTROLLE
R
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Introduction to
DMA
•• DMA (Direct Memory Access) allows peripherals to
transfer data directly to memory.
•• Reduces CPU involvement, improving system
efficiency.
•• Commonly used in hard drives, sound cards, and
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network adapters.
Functions of a 2025
DMA
Controller
•• Transfers data efficiently without CPU intervention.
•• Frees up CPU resources for other tasks.
•• Handles bulk data transfers efficiently.
•• Supports multiple channels for simultaneous
transfers.
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How DMA 2025
Works
1. CPU programs the DMA controller with source &
destination addresses.
•2. DMA controller takes control of the system bus.
•3. Data is transferred without CPU intervention.
•4. Once complete, DMA sends an interrupt to the
CPU.
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Examples
of DMA
Controller
s
•• Intel 8237: Classic DMA controller used in older PC architectures.
•• Modern DMA Controllers: Integrated into modern microcontrollers and
processors.
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1.Control Unit: This unit manages the overall operation of the DMA controller, including initiating and terminating data transfers.
2.Address Register: This register holds the memory address where data will be read from or written to. It is updated automatically after each data
transfer to point to the next address.
3.Data Register: This register temporarily holds the data being transferred between the memory and the peripheral.
4.Count Register: This register keeps track of the number of data units to be transferred. It decrements with each transfer until the transfer count
reaches zero.
5.Control Logic: This logic interprets commands from the CPU to start or stop the DMA operation and manages the priority of mu
6.Acknowledge Lines: These lines signal to the peripherals that their transfer request has been +------------------------------------------+
7. | DMA Controller |
8. +------------------------------------------+
9. | Address Register (Source/Dest) |
10. | Data Register (Buffer for Data) |
11. | Control Register (Mode, Status) |
12. | Status Register (Interrupts) |
13. +------------------------------------------+
14. | | |
15. | | |
16. v v v
17.+---------------+ +---------------+ +---------------+
18.| Memory | | Peripheral 1 | | Peripheral 2 |
19.+---------------+ +---------------+ +---------------+
Conclusion 2025
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